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[209.85.210.176]) by smtp.gmail.com with ESMTPSA id 21sm23328534pfh.103.2021.07.01.01.45.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Jul 2021 01:45:28 -0700 (PDT) Received: by mail-pf1-f176.google.com with SMTP id i6so5322442pfq.1; Thu, 01 Jul 2021 01:45:28 -0700 (PDT) X-Received: by 2002:a63:5b0e:: with SMTP id p14mr37904719pgb.110.1625129128125; Thu, 01 Jul 2021 01:45:28 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-2-zhiwei_liu@c-sky.com> <20304ba9-6f87-f7b9-a24d-15d4b3d3f75a@c-sky.com> In-Reply-To: <20304ba9-6f87-f7b9-a24d-15d4b3d3f75a@c-sky.com> From: Frank Chang Date: Thu, 1 Jul 2021 16:45:17 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus To: LIU Zhiwei Content-Type: multipart/alternative; boundary="000000000000656bf105c60bdce0" Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com, Alistair Francis , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000656bf105c60bdce0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=8820=E6=97= =A5 =E9=80=B1=E4=BA=8C =E4=B8=8A=E5=8D=888:49=E5=AF=AB=E9=81=93=EF=BC=9A > > On 2021/4/20 =E4=B8=8A=E5=8D=887:23, Alistair Francis wrote: > > On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote: > >> CSR mintstatus holds the active interrupt level for each supported > >> privilege mode. sintstatus, and user, uintstatus, provide restricted > >> views of mintstatus. > >> > >> Signed-off-by: LIU Zhiwei > >> --- > >> target/riscv/cpu.h | 2 ++ > >> target/riscv/cpu_bits.h | 11 +++++++++++ > >> target/riscv/csr.c | 26 ++++++++++++++++++++++++++ > >> 3 files changed, 39 insertions(+) > >> > >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >> index 0a33d387ba..1a44ca62c7 100644 > >> --- a/target/riscv/cpu.h > >> +++ b/target/riscv/cpu.h > >> @@ -159,6 +159,7 @@ struct CPURISCVState { > >> target_ulong mip; > >> > >> uint32_t miclaim; > >> + uint32_t mintstatus; /* clic-spec */ > >> > >> target_ulong mie; > >> target_ulong mideleg; > >> @@ -243,6 +244,7 @@ struct CPURISCVState { > >> > >> /* Fields from here on are preserved across CPU reset. */ > >> QEMUTimer *timer; /* Internal timer */ > >> + void *clic; /* clic interrupt controller */ > > This should be the CLIC type. > > OK. > > Actually there are many versions of CLIC in my branch as different > devices. But it is better to use CLIC type for the upstream version. > Hi Alistair and Zhiwei, Replacing void *clic with RISCVCLICState *clic may create a circular loop because CPURISCVState is also referenced in riscv_clic.h. However, I would like to ask what is the best approach to add the reference of CLIC device in CPURISCVState struct? There may be different kinds of CLIC devices. AFAK, there was another RFC patchset trying to add void *eclic for Nuclei processor into CPURISCVState struct: https://patchwork.kernel.org/project/qemu-devel/patch/20210507081654.11056-= 2-wangjunqiang@iscas.ac.cn/ Is it okay to add the device reference directly into CPURISCVState struct like that, or we should create some abstraction for these CLIC devices? (However, I'm not sure how big the differences are for these CLIC devices...) Thanks, Frank Chang > > > > >> }; > >> > >> OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, > >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > >> index caf4599207..c4ce6ec3d9 100644 > >> --- a/target/riscv/cpu_bits.h > >> +++ b/target/riscv/cpu_bits.h > >> @@ -165,6 +165,7 @@ > >> #define CSR_MCAUSE 0x342 > >> #define CSR_MTVAL 0x343 > >> #define CSR_MIP 0x344 > >> +#define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ > >> > >> /* Legacy Machine Trap Handling (priv v1.9.1) */ > >> #define CSR_MBADADDR 0x343 > >> @@ -183,6 +184,7 @@ > >> #define CSR_SCAUSE 0x142 > >> #define CSR_STVAL 0x143 > >> #define CSR_SIP 0x144 > >> +#define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ > >> > >> /* Legacy Supervisor Trap Handling (priv v1.9.1) */ > >> #define CSR_SBADADDR 0x143 > >> @@ -585,6 +587,15 @@ > >> #define SIP_STIP MIP_STIP > >> #define SIP_SEIP MIP_SEIP > >> > >> +/* mintstatus */ > >> +#define MINTSTATUS_MIL 0xff000000 /* mil[7:0] */ > >> +#define MINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ > >> +#define MINTSTATUS_UIL 0x000000ff /* uil[7:0] */ > >> + > >> +/* sintstatus */ > >> +#define SINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ > >> +#define SINTSTATUS_UIL 0x000000ff /* uil[7:0] */ > > The bit fields in the comments are out of date. > > I didn't notice it. Fix it in next version. > > Thanks. > > Zhiwei > > > > > Alistair > > > >> + > >> /* MIE masks */ > >> #define MIE_SEIE (1 << IRQ_S_EXT) > >> #define MIE_UEIE (1 << IRQ_U_EXT) > >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c > >> index d2585395bf..320b18ab60 100644 > >> --- a/target/riscv/csr.c > >> +++ b/target/riscv/csr.c > >> @@ -188,6 +188,12 @@ static int pmp(CPURISCVState *env, int csrno) > >> { > >> return -!riscv_feature(env, RISCV_FEATURE_PMP); > >> } > >> + > >> +static int clic(CPURISCVState *env, int csrno) > >> +{ > >> + return !!env->clic; > >> +} > >> + > >> #endif > >> > >> /* User Floating-Point CSRs */ > >> @@ -734,6 +740,12 @@ static int rmw_mip(CPURISCVState *env, int csrno, > target_ulong *ret_value, > >> return 0; > >> } > >> > >> +static int read_mintstatus(CPURISCVState *env, int csrno, target_ulon= g > *val) > >> +{ > >> + *val =3D env->mintstatus; > >> + return 0; > >> +} > >> + > >> /* Supervisor Trap Setup */ > >> static int read_sstatus(CPURISCVState *env, int csrno, target_ulong > *val) > >> { > >> @@ -893,6 +905,13 @@ static int rmw_sip(CPURISCVState *env, int csrno, > target_ulong *ret_value, > >> return ret; > >> } > >> > >> +static int read_sintstatus(CPURISCVState *env, int csrno, target_ulon= g > *val) > >> +{ > >> + target_ulong mask =3D SINTSTATUS_SIL | SINTSTATUS_UIL; > >> + *val =3D env->mintstatus & mask; > >> + return 0; > >> +} > >> + > >> /* Supervisor Protection and Translation */ > >> static int read_satp(CPURISCVState *env, int csrno, target_ulong *va= l) > >> { > >> @@ -1644,5 +1663,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { > >> [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_zero }= , > >> [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_zero }= , > >> [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }= , > >> + > >> + /* Machine Mode Core Level Interrupt Controller */ > >> + [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, > >> + > >> + /* Supervisor Mode Core Level Interrupt Controller */ > >> + [CSR_SINTSTATUS] =3D { "sintstatus", clic, read_sintstatus }, > >> + > >> #endif /* !CONFIG_USER_ONLY */ > >> }; > >> -- > >> 2.25.1 > >> > >> > > --000000000000656bf105c60bdce0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021= =E5=B9=B44=E6=9C=8820=E6=97=A5 =E9=80=B1=E4=BA=8C =E4=B8=8A=E5=8D=888:49=E5= =AF=AB=E9=81=93=EF=BC=9A

On 2021/4/20 =E4=B8=8A=E5=8D=887:23, Alistair Francis wrote:
> On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>> CSR mintstatus holds the active interrupt level for each supported=
>> privilege mode. sintstatus, and user, uintstatus, provide restrict= ed
>> views of mintstatus.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>>=C2=A0 =C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++ >>=C2=A0 =C2=A0target/riscv/cpu_bits.h | 11 +++++++++++
>>=C2=A0 =C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 26 ++++++++++= ++++++++++++++++
>>=C2=A0 =C2=A03 files changed, 39 insertions(+)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 0a33d387ba..1a44ca62c7 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -159,6 +159,7 @@ struct CPURISCVState {
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong mip;
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t miclaim;
>> +=C2=A0 =C2=A0 uint32_t mintstatus; /* clic-spec */
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong mie;
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong mideleg;
>> @@ -243,6 +244,7 @@ struct CPURISCVState {
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Fields from here on are preserved acr= oss CPU reset. */
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0QEMUTimer *timer; /* Internal timer */ >> +=C2=A0 =C2=A0 void *clic;=C2=A0 =C2=A0 =C2=A0 =C2=A0/* clic inter= rupt controller */
> This should be the CLIC type.

OK.

Actually there are many versions of CLIC in my branch as different
devices. But it is better to use CLIC type for the upstream version.

Hi Alistair and Zhiwei,

<= div>Replacing void *clic with=C2=A0RISCVCLICState *clic may create a circul= ar loop
because CPURISCVState is also referenced in riscv_clic.h.=

However, I would like to ask what is the best app= roach to add
the reference of CLIC device in CPURISCVState struct= ?

There may be different kinds of CLIC devices.
AFAK, there was another RFC patchset trying to add void *eclic
for Nuclei processor into CPURISCVState struct:
=
Is it okay to add the device reference directly into CPURISC= VState struct like that,
or we should create some abstraction for= these CLIC devices?
(However, I'm not sure how big the diffe= rences are for these CLIC devices...)

Thanks,<= /div>
Frank Chang
=C2=A0

>
>>=C2=A0 =C2=A0};
>>
>>=C2=A0 =C2=A0OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index caf4599207..c4ce6ec3d9 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -165,6 +165,7 @@
>>=C2=A0 =C2=A0#define CSR_MCAUSE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0= x342
>>=C2=A0 =C2=A0#define CSR_MTVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A00x343
>>=C2=A0 =C2=A0#define CSR_MIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A00x344
>> +#define CSR_MINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x346 /* clic-spec-dra= ft */
>>
>>=C2=A0 =C2=A0/* Legacy Machine Trap Handling (priv v1.9.1) */
>>=C2=A0 =C2=A0#define CSR_MBADADDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x343<= br> >> @@ -183,6 +184,7 @@
>>=C2=A0 =C2=A0#define CSR_SCAUSE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0= x142
>>=C2=A0 =C2=A0#define CSR_STVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A00x143
>>=C2=A0 =C2=A0#define CSR_SIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A00x144
>> +#define CSR_SINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x146 /* clic-spec-dra= ft */
>>
>>=C2=A0 =C2=A0/* Legacy Supervisor Trap Handling (priv v1.9.1) */ >>=C2=A0 =C2=A0#define CSR_SBADADDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x143<= br> >> @@ -585,6 +587,15 @@
>>=C2=A0 =C2=A0#define SIP_STIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MIP_STIP
>>=C2=A0 =C2=A0#define SIP_SEIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MIP_SEIP
>>
>> +/* mintstatus */
>> +#define MINTSTATUS_MIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00xff000000 /* mil[7:0] */
>> +#define MINTSTATUS_SIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x0000ff00 /* sil[7:0] */
>> +#define MINTSTATUS_UIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x000000ff /* uil[7:0] */
>> +
>> +/* sintstatus */
>> +#define SINTSTATUS_SIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x0000ff00 /* sil[7:0] */
>> +#define SINTSTATUS_UIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x000000ff /* uil[7:0] */
> The bit fields in the comments are out of date.

I didn't notice it.=C2=A0=C2=A0 Fix it in next version.

Thanks.

Zhiwei

>
> Alistair
>
>> +
>>=C2=A0 =C2=A0/* MIE masks */
>>=C2=A0 =C2=A0#define MIE_SEIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << IRQ_= S_EXT)
>>=C2=A0 =C2=A0#define MIE_UEIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << IRQ_= U_EXT)
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index d2585395bf..320b18ab60 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -188,6 +188,12 @@ static int pmp(CPURISCVState *env, int csrno)=
>>=C2=A0 =C2=A0{
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0return -!riscv_feature(env, RISCV_FEATUR= E_PMP);
>>=C2=A0 =C2=A0}
>> +
>> +static int clic(CPURISCVState *env, int csrno)
>> +{
>> +=C2=A0 =C2=A0 return !!env->clic;
>> +}
>> +
>>=C2=A0 =C2=A0#endif
>>
>>=C2=A0 =C2=A0/* User Floating-Point CSRs */
>> @@ -734,6 +740,12 @@ static int rmw_mip(CPURISCVState *env, int cs= rno, target_ulong *ret_value,
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
>>=C2=A0 =C2=A0}
>>
>> +static int read_mintstatus(CPURISCVState *env, int csrno, target_= ulong *val)
>> +{
>> +=C2=A0 =C2=A0 *val =3D env->mintstatus;
>> +=C2=A0 =C2=A0 return 0;
>> +}
>> +
>>=C2=A0 =C2=A0/* Supervisor Trap Setup */
>>=C2=A0 =C2=A0static int read_sstatus(CPURISCVState *env, int csrno,= target_ulong *val)
>>=C2=A0 =C2=A0{
>> @@ -893,6 +905,13 @@ static int rmw_sip(CPURISCVState *env, int cs= rno, target_ulong *ret_value,
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
>>=C2=A0 =C2=A0}
>>
>> +static int read_sintstatus(CPURISCVState *env, int csrno, target_= ulong *val)
>> +{
>> +=C2=A0 =C2=A0 target_ulong mask =3D SINTSTATUS_SIL | SINTSTATUS_U= IL;
>> +=C2=A0 =C2=A0 *val =3D env->mintstatus & mask;
>> +=C2=A0 =C2=A0 return 0;
>> +}
>> +
>>=C2=A0 =C2=A0/* Supervisor Protection and Translation */
>>=C2=A0 =C2=A0static int read_satp(CPURISCVState *env, int csrno, ta= rget_ulong *val)
>>=C2=A0 =C2=A0{
>> @@ -1644,5 +1663,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE= ] =3D {
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_MHPMCOUNTER29H] =3D { "mhpmcou= nter29h", any32,=C2=A0 read_zero },
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_MHPMCOUNTER30H] =3D { "mhpmcou= nter30h", any32,=C2=A0 read_zero },
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_MHPMCOUNTER31H] =3D { "mhpmcou= nter31h", any32,=C2=A0 read_zero },
>> +
>> +=C2=A0 =C2=A0 /* Machine Mode Core Level Interrupt Controller */<= br> >> +=C2=A0 =C2=A0 [CSR_MINTSTATUS] =3D { "mintstatus", clic= ,=C2=A0 read_mintstatus },
>> +
>> +=C2=A0 =C2=A0 /* Supervisor Mode Core Level Interrupt Controller = */
>> +=C2=A0 =C2=A0 [CSR_SINTSTATUS] =3D { "sintstatus", clic= ,=C2=A0 read_sintstatus },
>> +
>>=C2=A0 =C2=A0#endif /* !CONFIG_USER_ONLY */
>>=C2=A0 =C2=A0};
>> --
>> 2.25.1
>>
>>

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