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[209.85.216.51]) by smtp.gmail.com with ESMTPSA id u12sm4216666pgi.21.2021.10.15.02.02.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Oct 2021 02:02:53 -0700 (PDT) Received: by mail-pj1-f51.google.com with SMTP id np13so6748099pjb.4; Fri, 15 Oct 2021 02:02:52 -0700 (PDT) X-Received: by 2002:a17:902:e313:b0:13f:1866:aa86 with SMTP id q19-20020a170902e31300b0013f1866aa86mr9917755plc.55.1634288572477; Fri, 15 Oct 2021 02:02:52 -0700 (PDT) MIME-Version: 1.0 References: <20211015074627.3957162-1-frank.chang@sifive.com> In-Reply-To: <20211015074627.3957162-1-frank.chang@sifive.com> From: Frank Chang Date: Fri, 15 Oct 2021 17:02:41 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v8 00/78] support vector extension v1.0 To: Frank Chang Content-Type: multipart/alternative; boundary="000000000000d2b86505ce6075eb" Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000d2b86505ce6075eb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =E6=96=BC 2021=E5=B9=B410=E6=9C=8815=E6=97=A5 =E9= =80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:48=E5=AF=AB=E9=81=93=EF=BC=9A > From: Frank Chang > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > RVV v1.0 spec is now fronzen for public review: > https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 > > The port is available here: > https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v8 > > RVV v1.0 can be enabled with -cpu option: v=3Dtrue and specify vext_spec > option to v1.0 (i.e. vext_spec=3Dv1.0) > > Note: This patchset depends on other patchsets listed in Based-on > section below so it is not able to be built unless those patchsets > are applied. > > Changelog: > > v8 > * Use {get,dest}_gpr APIs. > * remove vector AMO instructions. > * rename vpopc.m to vcpop.m. > * rename vle1.v and vse1.v to vlm.v and vsm.v. > * rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm. > > v7 > * remove hardcoded GDB vector registers list. > * add vsetivli instruction. > * add vle1.v and vse1.v instructions. > > v6 > * add vector floating-point reciprocal estimate instruction. > * add vector floating-point reciprocal square-root estimate instruction= . > * update check rules for segment register groups, each segment register > group has to follow overlap rules. > * update viota.m instruction check rules. > > v5 > * refactor RVV v1.0 check functions. > (Thanks to Richard Henderson's bitwise tricks.) > * relax RV_VLEN_MAX to 1024-bits. > * implement vstart CSR's behaviors. > * trigger illegal instruction exception if frm is not valid for > vector floating-point instructions. > * rebase on riscv-to-apply.next. > > v4 > * remove explicit float flmul variable in DisasContext. > * replace floating-point calculations with shift operations to > improve performance. > * relax RV_VLEN_MAX to 512-bits. > > v3 > * apply nan-box helpers from Richard Henderson. > * remove fp16 api changes as they are sent independently in another > pathcset by Chih-Min Chao. > * remove all tail elements clear functions as tail elements can > retain unchanged for either VTA set to undisturbed or agnostic. > * add fp16 nan-box check generator function. > * add floating-point rounding mode enum. > * replace flmul arithmetic with shifts to avoid floating-point > conversions. > * add Zvqmac extension. > * replace gdbstub vector register xml files with dynamic generator. > * bumped to RVV v1.0. > * RVV v1.0 related changes: > * add vlre.v and vsr.v vector whole register > load/store instructions > * add vrgatherei16 instruction. > * rearranged bits in vtype to make vlmul bits into a contiguous > field. > > v2 > * drop v0.7.1 support. > * replace invisible return check macros with functions. > * move mark_vs_dirty() to translators. > * add SSTATUS_VS flag for s-mode. > * nan-box scalar fp register for floating-point operations. > * add gdbstub files for vector registers to allow system-mode > debugging with GDB. > > Based-on: <20211015065500.3850513-1-frank.chang@sifive.com> > Based-on: <20211015070307.3860984-1-frank.chang@sifive.com> > > Frank Chang (73): > target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh > target/riscv: drop vector 0.7.1 and add 1.0 support > target/riscv: Use FIELD_EX32() to extract wd field > target/riscv: rvv-1.0: introduce writable misa.v field > target/riscv: rvv-1.0: add translation-time vector context status > target/riscv: rvv-1.0: remove rvv related codes from fcsr registers > target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr > registers > target/riscv: rvv-1.0: remove MLEN calculations > target/riscv: rvv-1.0: add fractional LMUL > target/riscv: rvv-1.0: add VMA and VTA > target/riscv: rvv-1.0: update check functions > target/riscv: introduce more imm value modes in translator functions > target/riscv: rvv:1.0: add translation-time nan-box helper function > target/riscv: rvv-1.0: remove amo operations instructions > target/riscv: rvv-1.0: configure instructions > target/riscv: rvv-1.0: stride load and store instructions > target/riscv: rvv-1.0: index load and store instructions > target/riscv: rvv-1.0: fix address index overflow bug of indexed > load/store insns > target/riscv: rvv-1.0: fault-only-first unit stride load > target/riscv: rvv-1.0: load/store whole register instructions > target/riscv: rvv-1.0: update vext_max_elems() for load/store insns > target/riscv: rvv-1.0: take fractional LMUL into vector max elements > calculation > target/riscv: rvv-1.0: floating-point square-root instruction > target/riscv: rvv-1.0: floating-point classify instructions > target/riscv: rvv-1.0: count population in mask instruction > target/riscv: rvv-1.0: find-first-set mask bit instruction > target/riscv: rvv-1.0: set-X-first mask bit instructions > target/riscv: rvv-1.0: iota instruction > target/riscv: rvv-1.0: element index instruction > target/riscv: rvv-1.0: allow load element with sign-extended > target/riscv: rvv-1.0: register gather instructions > target/riscv: rvv-1.0: integer scalar move instructions > target/riscv: rvv-1.0: floating-point move instruction > target/riscv: rvv-1.0: floating-point scalar move instructions > target/riscv: rvv-1.0: whole register move instructions > target/riscv: rvv-1.0: integer extension instructions > target/riscv: rvv-1.0: single-width averaging add and subtract > instructions > target/riscv: rvv-1.0: single-width bit shift instructions > target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow > target/riscv: rvv-1.0: narrowing integer right shift instructions > target/riscv: rvv-1.0: widening integer multiply-add instructions > target/riscv: rvv-1.0: single-width saturating add and subtract > instructions > target/riscv: rvv-1.0: integer comparison instructions > target/riscv: rvv-1.0: floating-point compare instructions > target/riscv: rvv-1.0: mask-register logical instructions > target/riscv: rvv-1.0: slide instructions > target/riscv: rvv-1.0: floating-point slide instructions > target/riscv: rvv-1.0: narrowing fixed-point clip instructions > target/riscv: rvv-1.0: single-width floating-point reduction > target/riscv: rvv-1.0: widening floating-point reduction instructions > target/riscv: rvv-1.0: single-width scaling shift instructions > target/riscv: rvv-1.0: remove widening saturating scaled multiply-add > target/riscv: rvv-1.0: remove vmford.vv and vmford.vf > target/riscv: rvv-1.0: remove integer extract instruction > target/riscv: rvv-1.0: floating-point min/max instructions > target/riscv: introduce floating-point rounding mode enum > target/riscv: rvv-1.0: floating-point/integer type-convert > instructions > target/riscv: rvv-1.0: widening floating-point/integer type-convert > target/riscv: add "set round to odd" rounding mode helper function > target/riscv: rvv-1.0: narrowing floating-point/integer type-convert > target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits > target/riscv: rvv-1.0: implement vstart CSR > target/riscv: rvv-1.0: trigger illegal instruction exception if frm is > not valid > target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs > target/riscv: rvv-1.0: floating-point reciprocal square-root estimate > instruction > target/riscv: rvv-1.0: floating-point reciprocal estimate instruction > target/riscv: set mstatus.SD bit when writing fp CSRs > target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 > target/riscv: rvv-1.0: add vsetivli instruction > target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() > target/riscv: rvv-1.0: add vector unit-stride mask load/store insns > target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm > and vmorn.mm > target/riscv: rvv-1.0: update opivv_vadc_check() comment > > Greentime Hu (1): > target/riscv: rvv-1.0: add vlenb register > > Hsiangkai Wang (1): > target/riscv: gdb: support vector registers for rv64 & rv32 > > LIU Zhiwei (3): > target/riscv: rvv-1.0: add mstatus VS field > target/riscv: rvv-1.0: add sstatus VS field > target/riscv: rvv-1.0: add vcsr register > > target/riscv/cpu.c | 12 +- > target/riscv/cpu.h | 85 +- > target/riscv/cpu_bits.h | 10 + > target/riscv/cpu_helper.c | 15 +- > target/riscv/csr.c | 92 +- > target/riscv/fpu_helper.c | 17 +- > target/riscv/gdbstub.c | 184 ++ > target/riscv/helper.h | 435 ++- > target/riscv/insn32.decode | 294 +- > target/riscv/insn_trans/trans_rvv.c.inc | 2423 +++++++++------ > target/riscv/internals.h | 24 +- > target/riscv/translate.c | 74 +- > target/riscv/vector_helper.c | 3601 ++++++++++++----------- > 13 files changed, 4176 insertions(+), 3090 deletions(-) > > -- > 2.25.1 > > > I notice that there are couple of unexpected patches being incldued in this series: * [PATCH 18/76] target/riscv: rvv-1.0: configure instructions * [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions * [PATCH 20/76] target/riscv: rvv-1.0: index load and store instructions * [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns * [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load * [PATCH 23/76] target/riscv: rvv-1.0: amo operations It's probably because I had dirty content in my directory which I didn't aware of :( Please ignore them. Or I can resend the patchset if that's more convenient to review. Sorry for the confusion. Regards, Frank Chang --000000000000d2b86505ce6075eb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
<frank.chang@sifive.com> =E6=96=BC 2021=E5=B9=B410=E6=9C=8815=E6= =97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:48=E5=AF=AB=E9=81=93=EF=BC=9A=
From: Frank Chang <frank.chang@sifive.com>

This patchset implements the vector extension v1.0 for RISC-V on QEMU.

RVV v1.0 spec is now fronzen for public review:
https://github.com/riscv/riscv-v-spec/release= s/tag/v1.0

The port is available here:
https://github.com/sifive/qemu/tree/rvv-1.0-u= pstream-v8

RVV v1.0 can be enabled with -cpu option: v=3Dtrue and specify vext_spec option to v1.0 (i.e. vext_spec=3Dv1.0)

Note: This patchset depends on other patchsets listed in Based-on
=C2=A0 =C2=A0 =C2=A0 section below so it is not able to be built unless tho= se patchsets
=C2=A0 =C2=A0 =C2=A0 are applied.

Changelog:

v8
=C2=A0 * Use {get,dest}_gpr APIs.
=C2=A0 * remove vector AMO instructions.
=C2=A0 * rename vpopc.m to vcpop.m.
=C2=A0 * rename vle1.v and vse1.v to vlm.v and vsm.v.
=C2=A0 * rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm.

v7
=C2=A0 * remove hardcoded GDB vector registers list.
=C2=A0 * add vsetivli instruction.
=C2=A0 * add vle1.v and vse1.v instructions.

v6
=C2=A0 * add vector floating-point reciprocal estimate instruction.
=C2=A0 * add vector floating-point reciprocal square-root estimate instruct= ion.
=C2=A0 * update check rules for segment register groups, each segment regis= ter
=C2=A0 =C2=A0 group has to follow overlap rules.
=C2=A0 * update viota.m instruction check rules.

v5
=C2=A0 * refactor RVV v1.0 check functions.
=C2=A0 =C2=A0 (Thanks to Richard Henderson's bitwise tricks.)
=C2=A0 * relax RV_VLEN_MAX to 1024-bits.
=C2=A0 * implement vstart CSR's behaviors.
=C2=A0 * trigger illegal instruction exception if frm is not valid for
=C2=A0 =C2=A0 vector floating-point instructions.
=C2=A0 * rebase on riscv-to-apply.next.

v4
=C2=A0 * remove explicit float flmul variable in DisasContext.
=C2=A0 * replace floating-point calculations with shift operations to
=C2=A0 =C2=A0 improve performance.
=C2=A0 * relax RV_VLEN_MAX to 512-bits.

v3
=C2=A0 * apply nan-box helpers from Richard Henderson.
=C2=A0 * remove fp16 api changes as they are sent independently in another<= br> =C2=A0 =C2=A0 pathcset by Chih-Min Chao.
=C2=A0 * remove all tail elements clear functions as tail elements can
=C2=A0 =C2=A0 retain unchanged for either VTA set to undisturbed or agnosti= c.
=C2=A0 * add fp16 nan-box check generator function.
=C2=A0 * add floating-point rounding mode enum.
=C2=A0 * replace flmul arithmetic with shifts to avoid floating-point
=C2=A0 =C2=A0 conversions.
=C2=A0 * add Zvqmac extension.
=C2=A0 * replace gdbstub vector register xml files with dynamic generator.<= br> =C2=A0 * bumped to RVV v1.0.
=C2=A0 * RVV v1.0 related changes:
=C2=A0 =C2=A0 * add vl<nf>re<eew>.v and vs<nf>r.v vector = whole register
=C2=A0 =C2=A0 =C2=A0 load/store instructions
=C2=A0 =C2=A0 * add vrgatherei16 instruction.
=C2=A0 =C2=A0 * rearranged bits in vtype to make vlmul bits into a contiguo= us
=C2=A0 =C2=A0 =C2=A0 field.

v2
=C2=A0 * drop v0.7.1 support.
=C2=A0 * replace invisible return check macros with functions.
=C2=A0 * move mark_vs_dirty() to translators.
=C2=A0 * add SSTATUS_VS flag for s-mode.
=C2=A0 * nan-box scalar fp register for floating-point operations.
=C2=A0 * add gdbstub files for vector registers to allow system-mode
=C2=A0 =C2=A0 debugging with GDB.

Based-on: <20211015065500.3850513-1-frank.chang@sifive.com= >
Based-on: <20211015070307.3860984-1-frank.chang@sifive.com= >

Frank Chang (73):
=C2=A0 target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
=C2=A0 target/riscv: drop vector 0.7.1 and add 1.0 support
=C2=A0 target/riscv: Use FIELD_EX32() to extract wd field
=C2=A0 target/riscv: rvv-1.0: introduce writable misa.v field
=C2=A0 target/riscv: rvv-1.0: add translation-time vector context status =C2=A0 target/riscv: rvv-1.0: remove rvv related codes from fcsr registers<= br> =C2=A0 target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr =C2=A0 =C2=A0 registers
=C2=A0 target/riscv: rvv-1.0: remove MLEN calculations
=C2=A0 target/riscv: rvv-1.0: add fractional LMUL
=C2=A0 target/riscv: rvv-1.0: add VMA and VTA
=C2=A0 target/riscv: rvv-1.0: update check functions
=C2=A0 target/riscv: introduce more imm value modes in translator functions=
=C2=A0 target/riscv: rvv:1.0: add translation-time nan-box helper function<= br> =C2=A0 target/riscv: rvv-1.0: remove amo operations instructions
=C2=A0 target/riscv: rvv-1.0: configure instructions
=C2=A0 target/riscv: rvv-1.0: stride load and store instructions
=C2=A0 target/riscv: rvv-1.0: index load and store instructions
=C2=A0 target/riscv: rvv-1.0: fix address index overflow bug of indexed
=C2=A0 =C2=A0 load/store insns
=C2=A0 target/riscv: rvv-1.0: fault-only-first unit stride load
=C2=A0 target/riscv: rvv-1.0: load/store whole register instructions
=C2=A0 target/riscv: rvv-1.0: update vext_max_elems() for load/store insns<= br> =C2=A0 target/riscv: rvv-1.0: take fractional LMUL into vector max elements=
=C2=A0 =C2=A0 calculation
=C2=A0 target/riscv: rvv-1.0: floating-point square-root instruction
=C2=A0 target/riscv: rvv-1.0: floating-point classify instructions
=C2=A0 target/riscv: rvv-1.0: count population in mask instruction
=C2=A0 target/riscv: rvv-1.0: find-first-set mask bit instruction
=C2=A0 target/riscv: rvv-1.0: set-X-first mask bit instructions
=C2=A0 target/riscv: rvv-1.0: iota instruction
=C2=A0 target/riscv: rvv-1.0: element index instruction
=C2=A0 target/riscv: rvv-1.0: allow load element with sign-extended
=C2=A0 target/riscv: rvv-1.0: register gather instructions
=C2=A0 target/riscv: rvv-1.0: integer scalar move instructions
=C2=A0 target/riscv: rvv-1.0: floating-point move instruction
=C2=A0 target/riscv: rvv-1.0: floating-point scalar move instructions
=C2=A0 target/riscv: rvv-1.0: whole register move instructions
=C2=A0 target/riscv: rvv-1.0: integer extension instructions
=C2=A0 target/riscv: rvv-1.0: single-width averaging add and subtract
=C2=A0 =C2=A0 instructions
=C2=A0 target/riscv: rvv-1.0: single-width bit shift instructions
=C2=A0 target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow =C2=A0 target/riscv: rvv-1.0: narrowing integer right shift instructions =C2=A0 target/riscv: rvv-1.0: widening integer multiply-add instructions =C2=A0 target/riscv: rvv-1.0: single-width saturating add and subtract
=C2=A0 =C2=A0 instructions
=C2=A0 target/riscv: rvv-1.0: integer comparison instructions
=C2=A0 target/riscv: rvv-1.0: floating-point compare instructions
=C2=A0 target/riscv: rvv-1.0: mask-register logical instructions
=C2=A0 target/riscv: rvv-1.0: slide instructions
=C2=A0 target/riscv: rvv-1.0: floating-point slide instructions
=C2=A0 target/riscv: rvv-1.0: narrowing fixed-point clip instructions
=C2=A0 target/riscv: rvv-1.0: single-width floating-point reduction
=C2=A0 target/riscv: rvv-1.0: widening floating-point reduction instruction= s
=C2=A0 target/riscv: rvv-1.0: single-width scaling shift instructions
=C2=A0 target/riscv: rvv-1.0: remove widening saturating scaled multiply-ad= d
=C2=A0 target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
=C2=A0 target/riscv: rvv-1.0: remove integer extract instruction
=C2=A0 target/riscv: rvv-1.0: floating-point min/max instructions
=C2=A0 target/riscv: introduce floating-point rounding mode enum
=C2=A0 target/riscv: rvv-1.0: floating-point/integer type-convert
=C2=A0 =C2=A0 instructions
=C2=A0 target/riscv: rvv-1.0: widening floating-point/integer type-convert<= br> =C2=A0 target/riscv: add "set round to odd" rounding mode helper = function
=C2=A0 target/riscv: rvv-1.0: narrowing floating-point/integer type-convert=
=C2=A0 target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
=C2=A0 target/riscv: rvv-1.0: implement vstart CSR
=C2=A0 target/riscv: rvv-1.0: trigger illegal instruction exception if frm = is
=C2=A0 =C2=A0 not valid
=C2=A0 target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs =C2=A0 target/riscv: rvv-1.0: floating-point reciprocal square-root estimat= e
=C2=A0 =C2=A0 instruction
=C2=A0 target/riscv: rvv-1.0: floating-point reciprocal estimate instructio= n
=C2=A0 target/riscv: set mstatus.SD bit when writing fp CSRs
=C2=A0 target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
=C2=A0 target/riscv: rvv-1.0: add vsetivli instruction
=C2=A0 target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
=C2=A0 target/riscv: rvv-1.0: add vector unit-stride mask load/store insns<= br> =C2=A0 target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm
=C2=A0 =C2=A0 and vmorn.mm
=C2=A0 target/riscv: rvv-1.0: update opivv_vadc_check() comment

Greentime Hu (1):
=C2=A0 target/riscv: rvv-1.0: add vlenb register

Hsiangkai Wang (1):
=C2=A0 target/riscv: gdb: support vector registers for rv64 & rv32

LIU Zhiwei (3):
=C2=A0 target/riscv: rvv-1.0: add mstatus VS field
=C2=A0 target/riscv: rvv-1.0: add sstatus VS field
=C2=A0 target/riscv: rvv-1.0: add vcsr register

=C2=A0target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A012 +-
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A085 +-
=C2=A0target/riscv/cpu_bits.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A010 +
=C2=A0target/riscv/cpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 =C2=A015 +-
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A092 +-
=C2=A0target/riscv/fpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 =C2=A017 +-
=C2=A0target/riscv/gdbstub.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 184 ++
=C2=A0target/riscv/helper.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0|=C2=A0 435 ++-
=C2=A0target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 294 +-
=C2=A0target/riscv/insn_trans/trans_rvv.c.inc | 2423 +++++++++------
=C2=A0target/riscv/internals.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A024 +-
=C2=A0target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A074 +-
=C2=A0target/riscv/vector_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= | 3601 ++++++++++++-----------
=C2=A013 files changed, 4176 insertions(+), 3090 deletions(-)

--
2.25.1



I notice that there are couple of unex= pected patches being incldued in this series:

* [P= ATCH 18/76] target/riscv: rvv-1.0: configure instructions
* [PATCH 19/76= ] target/riscv: rvv-1.0: stride load and store instructions
* [PATCH 20/= 76] target/riscv: rvv-1.0: index load and store instructions
* [PATCH 21= /76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/= store insns
* [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit= stride load
* [PATCH 23/76] target/riscv: rvv-1.0: amo operations

It's probably because I had dirty content in my= directory which I didn't aware of :(
Please ignore them.
Or I can resend the patchset if that's more convenient to review= .
Sorry for the confusion.

Regards,
F= rank Chang
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