From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B1EAC48BE0 for ; Fri, 11 Jun 2021 09:09:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8ADBA6136D for ; Fri, 11 Jun 2021 09:09:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8ADBA6136D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lrdA2-0006h2-O9 for qemu-devel@archiver.kernel.org; Fri, 11 Jun 2021 05:09:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <0xc0de0125@gmail.com>) id 1lrd9A-0005GI-U5; Fri, 11 Jun 2021 05:08:12 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:41878) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <0xc0de0125@gmail.com>) id 1lrd97-000895-Og; Fri, 11 Jun 2021 05:08:12 -0400 Received: by mail-pj1-x1033.google.com with SMTP id go18-20020a17090b03d2b029016e4ae973f7so4535323pjb.0; Fri, 11 Jun 2021 02:08:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=t8dsnBK+yYuSt2z8xEUR2PLdfj5uW9XxKDHeZNXzwf8=; b=tDndlj9QtlWgnCricOo1je2HV3w2u5xsB385c4aeRtobwOPLLDiAS5R8Ahk+iD8RnK Aj1FuvV9PiT8McitEuUrvbQ+S6mg0rTrU209EBKbCBgnZU+gm3H3rBeQLxb4v52GX+2X 1lhpz3JwEqrDd+tXCnH6RlpuJXlZdoMgjQlXeBzs0E+g89KfoAleZypqnsRWeiI8dLSs wLgY4wNSgls1ln/uCmr3sfKoa4W+5tnpfS8Xd4BI2Gu1WGVBQ/9ggahutLJh9dHLGRi5 oSEAWF3wSiq6WW70RB9AjaydECqW1oWaDb3nKoxf5jz0zayfpziEAnHTVKy6TN5AVe/1 kALg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=t8dsnBK+yYuSt2z8xEUR2PLdfj5uW9XxKDHeZNXzwf8=; b=WLw+YOXGSSZHuyD/yWQrqk94qthExQSQWT4Xd4JEO6VQOkOFQEfzzbcVPYvELJwWK3 PCZyHIQWym224aWIJK4okQyHpIT+QfhHvixT8EHdRA6MKTVRGJMpF+8D04IPYyReJT91 bxKYbJtMkBbNsjx+G4eMjJhQUIwdqOH33oATQsPuUXU9R4NlgnF6HxyDHr5GfLFghVUD 6rTyj6h64eAvi3j+NbhqD3wmkJdUTRqBSaW0IgGNsV1GtHSMWoNPKGdyu6J1kGxm9VDy 6sKyPpeERrs7iJxRSVeRcAlkDtktQ97o5Qb1ZWgMtN+add4RsDPaIZxONHUE4wUmSH9a P+uA== X-Gm-Message-State: AOAM533DVyqZCAwFgWsOyRpvpgUwhUqMYCEqI43RatcGcBfcorUapluR PpRWEIKCmRv8nvJQLOffLDkiqAFa+vZaUtBKUXI= X-Google-Smtp-Source: ABdhPJztBpnUKbIqwUttPeUbqftWJ9o8HHwa8swyKaWWyn7BYagUxkx6WZNAuO6Vsh0GWSQBBO5qWgIGgckepdlKP5E= X-Received: by 2002:a17:902:c202:b029:10f:b7b4:35 with SMTP id 2-20020a170902c202b029010fb7b40035mr3105486pll.82.1623402487952; Fri, 11 Jun 2021 02:08:07 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-9-zhiwei_liu@c-sky.com> In-Reply-To: From: Frank Chang <0xc0de0125@gmail.com> Date: Fri, 11 Jun 2021 17:07:56 +0800 Message-ID: Subject: Re: [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode To: LIU Zhiwei Content-Type: multipart/alternative; boundary="0000000000009f383505c479d8b5" Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=0xc0de0125@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000009f383505c479d8b5 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B46=E6=9C=8811=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=884:56=E5=AF=AB=E9=81=93=EF=BC=9A > > On 6/11/21 4:42 PM, Frank Chang wrote: > > LIU Zhiwei =E6=96=BC 2021=E5=B9=B46=E6=9C=8811=E6= =97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=884:30=E5=AF=AB=E9=81=93=EF=BC=9A > >> >> On 6/11/21 4:15 PM, Frank Chang wrote: >> >> LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6= =97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:52=E5=AF=AB=E9=81=93=EF=BC=9A >> >>> The CSR can be used by software to service the next horizontal interrup= t >>> when it has greater level than the saved interrupt context >>> (held in xcause`.pil`) and greater level than the interrupt threshold o= f >>> the corresponding privilege mode, >>> >>> Signed-off-by: LIU Zhiwei >>> --- >>> target/riscv/cpu_bits.h | 16 ++++++ >>> target/riscv/csr.c | 114 ++++++++++++++++++++++++++++++++++++++++ >>> 2 files changed, 130 insertions(+) >>> >>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >>> index 7922097776..494e41edc9 100644 >>> --- a/target/riscv/cpu_bits.h >>> +++ b/target/riscv/cpu_bits.h >>> @@ -166,6 +166,7 @@ >>> #define CSR_MCAUSE 0x342 >>> #define CSR_MTVAL 0x343 >>> #define CSR_MIP 0x344 >>> +#define CSR_MNXTI 0x345 /* clic-spec-draft */ >>> #define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ >>> #define CSR_MINTTHRESH 0x347 /* clic-spec-draft */ >>> >>> @@ -187,6 +188,7 @@ >>> #define CSR_SCAUSE 0x142 >>> #define CSR_STVAL 0x143 >>> #define CSR_SIP 0x144 >>> +#define CSR_SNXTI 0x145 /* clic-spec-draft */ >>> #define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ >>> #define CSR_SINTTHRESH 0x147 /* clic-spec-draft */ >>> >>> @@ -596,10 +598,24 @@ >>> #define MINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ >>> #define MINTSTATUS_UIL 0x000000ff /* uil[7:0] */ >>> >>> +/* mcause */ >>> +#define MCAUSE_MINHV 0x40000000 /* minhv */ >>> +#define MCAUSE_MPP 0x30000000 /* mpp[1:0] */ >>> +#define MCAUSE_MPIE 0x08000000 /* mpie */ >>> +#define MCAUSE_MPIL 0x00ff0000 /* mpil[7:0] */ >>> +#define MCAUSE_EXCCODE 0x00000fff /* exccode[11:0] >>> */ >>> + >>> /* sintstatus */ >>> #define SINTSTATUS_SIL 0x0000ff00 /* sil[7:0] */ >>> #define SINTSTATUS_UIL 0x000000ff /* uil[7:0] */ >>> >>> +/* scause */ >>> +#define SCAUSE_SINHV 0x40000000 /* sinhv */ >>> +#define SCAUSE_SPP 0x10000000 /* spp */ >>> +#define SCAUSE_SPIE 0x08000000 /* spie */ >>> +#define SCAUSE_SPIL 0x00ff0000 /* spil[7:0] */ >>> +#define SCAUSE_EXCCODE 0x00000fff /* exccode[11:0] >>> */ >>> + >>> /* MIE masks */ >>> #define MIE_SEIE (1 << IRQ_S_EXT) >>> #define MIE_UEIE (1 << IRQ_U_EXT) >>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >>> index e12222b77f..72cba080bf 100644 >>> --- a/target/riscv/csr.c >>> +++ b/target/riscv/csr.c >>> @@ -774,6 +774,80 @@ static int rmw_mip(CPURISCVState *env, int csrno, >>> target_ulong *ret_value, >>> return 0; >>> } >>> >>> +static bool get_xnxti_status(CPURISCVState *env) >>> +{ >>> + CPUState *cs =3D env_cpu(env); >>> + int clic_irq, clic_priv, clic_il, pil; >>> + >>> + if (!env->exccode) { /* No interrupt */ >>> + return false; >>> + } >>> + /* The system is not in a CLIC mode */ >>> + if (!riscv_clic_is_clic_mode(env)) { >>> + return false; >>> + } else { >>> + riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il, >>> + &clic_irq); >>> + >>> + if (env->priv =3D=3D PRV_M) { >>> + pil =3D MAX(get_field(env->mcause, MCAUSE_MPIL), >>> env->mintthresh); >>> + } else if (env->priv =3D=3D PRV_S) { >>> + pil =3D MAX(get_field(env->scause, SCAUSE_SPIL), >>> env->sintthresh); >>> + } else { >>> + qemu_log_mask(LOG_GUEST_ERROR, >>> + "CSR: rmw xnxti with unsupported mode\n"); >>> + exit(1); >>> + } >>> + >>> + if ((clic_priv !=3D env->priv) || /* No horizontal interrupt *= / >>> + (clic_il <=3D pil) || /* No higher level interrupt */ >>> + (riscv_clic_shv_interrupt(env->clic, clic_priv, >>> cs->cpu_index, >>> + clic_irq))) { /* CLIC vector mod= e >>> */ >>> + return false; >>> + } else { >>> + return true; >>> + } >>> + } >>> +} >>> + >>> +static int rmw_mnxti(CPURISCVState *env, int csrno, target_ulong >>> *ret_value, >>> + target_ulong new_value, target_ulong write_mask) >>> +{ >>> + int clic_priv, clic_il, clic_irq; >>> + bool ready; >>> + CPUState *cs =3D env_cpu(env); >>> + if (write_mask) { >>> + env->mstatus |=3D new_value & (write_mask & 0b11111); >>> + } >>> + >>> + qemu_mutex_lock_iothread(); >>> >> >> Hi Zhiwei, >> >> May I ask what's the purpose to request the BQL here with >> *qemu_mutex_lock_iothread()*? >> Is there any critical data we need to protect in *rmw_mnxti()*? >> As far I see, *rmw_mnxti()* won't call *cpu_interrupt()* which need BQL >> to be held before calling. >> Am I missing anything? >> >> In my opinion, if you read or write any MMIO register, you need to hold >> the BQL. As you can quickly see, >> it calls riscv_clic_clean_pending. That's why it should hold the BQL. >> >> Zhiwei >> > > Oh, I see. > The MMIO register reads and writes should also be protected by BQL. > Thanks for the explanation. > > I am glad to know that you are reviewing this patch set. As Sifive > implements the initial v0.7 CLIC, I think you may need this patch set for > your SOC. > If you like to, I am happy to see that you connect this patch set to your > SOC, and resend it again. I can also provide the qtest of this patch set = if > you need. > > As you may see, the v6.1 soft freeze will come in July. I am afraid I > can't upstream a new SOC in so short time. > > Zhiwei > Thanks, I think we will leverage the hard works you have done into our implementation. However, I'm not sure I can catch up the deadline before v6.1's soft-freeze= . But I think I can help to review the patches, at least we can speed up the review process. Regarding qtest, I saw your head commit mentioned the repo you are using: [1]. Is it okay to just grab the qtest from this repo? [1]: https://github.com/romanheros/qemu/commit/bce1845ea9b079b4c360440292dc47725= d1b24ab Thanks, Frank Chang > > Regards, > Frank Chang > > >> >> Regard, >> Frank Chang >> >> >>> + ready =3D get_xnxti_status(env); >>> + if (ready) { >>> + riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il, >>> + &clic_irq); >>> + if (write_mask) { >>> + bool edge =3D riscv_clic_edge_triggered(env->clic, clic_pr= iv, >>> + cs->cpu_index, >>> clic_irq); >>> + if (edge) { >>> + riscv_clic_clean_pending(env->clic, clic_priv, >>> + cs->cpu_index, clic_irq); >>> + } >>> + env->mintstatus =3D set_field(env->mintstatus, >>> + MINTSTATUS_MIL, clic_il); >>> + env->mcause =3D set_field(env->mcause, MCAUSE_EXCCODE, >>> clic_irq); >>> + } >>> + if (ret_value) { >>> + *ret_value =3D (env->mtvt & ~0x3f) + sizeof(target_ulong) = * >>> clic_irq; >>> + } >>> + } else { >>> + if (ret_value) { >>> + *ret_value =3D 0; >>> + } >>> + } >>> + qemu_mutex_unlock_iothread(); >>> + return 0; >>> +} >>> + >>> static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong >>> *val) >>> { >>> *val =3D env->mintstatus; >>> @@ -982,6 +1056,44 @@ static int rmw_sip(CPURISCVState *env, int csrno, >>> target_ulong *ret_value, >>> return ret; >>> } >>> >>> +static int rmw_snxti(CPURISCVState *env, int csrno, target_ulong >>> *ret_value, >>> + target_ulong new_value, target_ulong write_mask) >>> +{ >>> + int clic_priv, clic_il, clic_irq; >>> + bool ready; >>> + CPUState *cs =3D env_cpu(env); >>> + if (write_mask) { >>> + env->mstatus |=3D new_value & (write_mask & 0b11111); >>> + } >>> + >>> + qemu_mutex_lock_iothread(); >>> + ready =3D get_xnxti_status(env); >>> + if (ready) { >>> + riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il, >>> + &clic_irq); >>> + if (write_mask) { >>> + bool edge =3D riscv_clic_edge_triggered(env->clic, clic_pr= iv, >>> + cs->cpu_index, >>> clic_irq); >>> + if (edge) { >>> + riscv_clic_clean_pending(env->clic, clic_priv, >>> + cs->cpu_index, clic_irq); >>> + } >>> + env->mintstatus =3D set_field(env->mintstatus, >>> + MINTSTATUS_SIL, clic_il); >>> + env->scause =3D set_field(env->scause, SCAUSE_EXCCODE, >>> clic_irq); >>> + } >>> + if (ret_value) { >>> + *ret_value =3D (env->stvt & ~0x3f) + sizeof(target_ulong) = * >>> clic_irq; >>> + } >>> + } else { >>> + if (ret_value) { >>> + *ret_value =3D 0; >>> + } >>> + } >>> + qemu_mutex_unlock_iothread(); >>> + return 0; >>> +} >>> + >>> static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong >>> *val) >>> { >>> target_ulong mask =3D SINTSTATUS_SIL | SINTSTATUS_UIL; >>> @@ -1755,6 +1867,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D = { >>> >>> /* Machine Mode Core Level Interrupt Controller */ >>> [CSR_MTVT] =3D { "mtvt", clic, read_mtvt, write_mtvt }, >>> + [CSR_MNXTI] =3D { "mnxti", clic, NULL, NULL, rmw_mnxti }, >>> [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, >>> [CSR_MINTTHRESH] =3D { "mintthresh", clic, read_mintthresh, >>> write_mintthresh }, >>> @@ -1766,6 +1879,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D = { >>> >>> /* Supervisor Mode Core Level Interrupt Controller */ >>> [CSR_STVT] =3D { "stvt", clic, read_stvt, write_stvt }, >>> + [CSR_SNXTI] =3D { "snxti", clic, NULL, NULL, rmw_snxti }, >>> >>> #endif /* !CONFIG_USER_ONLY */ >>> }; >>> -- >>> 2.25.1 >>> >>> >>> --0000000000009f383505c479d8b5 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B46=E6=9C= =8811=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=884:56=E5=AF=AB=E9=81=93= =EF=BC=9A
=20 =20 =20


On 6/11/21 4:42 PM, Frank Chang wrote:
=20
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B46=E6=9C=8811=E6=97=A5 =E9=80=B1=E4=BA=94 = =E4=B8=8B=E5=8D=884:30=E5=AF=AB=E9=81=93=EF=BC=9A


On 6/11/21 4:15 PM, Frank Chang wrote:
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97=A5 =E9=80=B1= =E4=BA=94 =E4=B8=8B=E5=8D=883:52=E5=AF=AB=E9=81=93=EF=BC=9A
The C= SR can be used by software to service the next horizontal interrupt
when it has greater level than the saved interrupt context
(held in xcause`.pil`) and greater level than the interrupt threshold of
the corresponding privilege mode,

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
=C2=A0target/riscv/cpu_bits.h |=C2=A0 16 ++++++
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 114 ++++++++++++++++++++++++++++++++++++++++
=C2=A02 files changed, 130 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7922097776..494e41edc9 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -166,6 +166,7 @@
=C2=A0#define CSR_MCAUSE=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 0x342
=C2=A0#define CSR_MTVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A00x343
=C2=A0#define CSR_MIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A00x344
+#define CSR_MNXTI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A00x345 /* clic-spec-draft */
=C2=A0#define CSR_MINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x34= 6 /* clic-spec-draft */
=C2=A0#define CSR_MINTTHRESH=C2=A0 =C2=A0 =C2=A0 0x34= 7 /* clic-spec-draft */

@@ -187,6 +188,7 @@
=C2=A0#define CSR_SCAUSE=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 0x142
=C2=A0#define CSR_STVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A00x143
=C2=A0#define CSR_SIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A00x144
+#define CSR_SNXTI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A00x145 /* clic-spec-draft */
=C2=A0#define CSR_SINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x14= 6 /* clic-spec-draft */
=C2=A0#define CSR_SINTTHRESH=C2=A0 =C2=A0 =C2=A0 0x14= 7 /* clic-spec-draft */

@@ -596,10 +598,24 @@
=C2=A0#define MINTSTATUS_SIL=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x0000ff00 /* sil[7:0] */
=C2=A0#define MINTSTATUS_UIL=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x000000ff /* uil[7:0] */

+/* mcause */
+#define MCAUSE_MINHV=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x40000000 /* minhv */
+#define MCAUSE_MPP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x30000000 /* mpp[1:0] */
+#define MCAUSE_MPIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x08000000 /* mpie */
+#define MCAUSE_MPIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x00ff0000 /* mpil[7:0] */
+#define MCAUSE_EXCCODE=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x00000fff /* exccode[11:0] */
+
=C2=A0/* sintstatus */
=C2=A0#define SINTSTATUS_SIL=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x0000ff00 /* sil[7:0] */
=C2=A0#define SINTSTATUS_UIL=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x000000ff /* uil[7:0] */

+/* scause */
+#define SCAUSE_SINHV=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x40000000 /* sinhv */
+#define SCAUSE_SPP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x10000000 /* spp */
+#define SCAUSE_SPIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x08000000 /* spie */
+#define SCAUSE_SPIL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x00ff0000 /* spil[7:0] */
+#define SCAUSE_EXCCODE=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x00000fff /* exccode[11:0] */
+
=C2=A0/* MIE masks */
=C2=A0#define MIE_SEIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << IRQ_S_EXT)
=C2=A0#define MIE_UEIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << IRQ_U_EXT)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e12222b77f..72cba080bf 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -774,6 +774,80 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}

+static bool get_xnxti_status(CPURISCVState *env)
+{
+=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
+=C2=A0 =C2=A0 int clic_irq, clic_priv, clic_il, pil;=
+
+=C2=A0 =C2=A0 if (!env->exccode) { /* No interrup= t */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 /* The system is not in a CLIC mode */=
+=C2=A0 =C2=A0 if (!riscv_clic_is_clic_mode(env)) { +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &cli= c_irq);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (env->priv =3D=3D = PRV_M) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pil =3D MA= X(get_field(env->mcause, MCAUSE_MPIL), env->mintthresh);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (env->priv = =3D=3D PRV_S) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pil =3D MA= X(get_field(env->scause, SCAUSE_SPIL), env->sintthresh);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_m= ask(LOG_GUEST_ERROR,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "CSR: rmw xnxti with unsupported mode\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((clic_priv !=3D env-= >priv) || /* No horizontal interrupt */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (clic_il &= lt;=3D pil) || /* No higher level interrupt */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (riscv_clic_shv_interrupt(env->clic, clic_priv, cs->cpu_index,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 clic_irq))) { /* CLIC vector mode */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return fal= se;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return tru= e;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+}
+
+static int rmw_mnxti(CPURISCVState *env, int csrno, target_ulong *ret_value,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0target_ulong new_value, target_ulong write_mask)
+{
+=C2=A0 =C2=A0 int clic_priv, clic_il, clic_irq;
+=C2=A0 =C2=A0 bool ready;
+=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
+=C2=A0 =C2=A0 if (write_mask) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mstatus |=3D new= _value & (write_mask & 0b11111);
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 qemu_mutex_lock_iothread();

Hi Zhiwei,

May I ask what's the purpose to request the BQ= L here with=C2=A0qemu_mutex_lock_iothread()?
Is there any critical data we need to protect in=C2=A0rmw_mnxti()?
As far I see,=C2=A0rmw_mnxti() won't ca= ll cpu_interrupt() which need BQL to be held before calling.
Am I missing anything?
In my opinion, if you read or write any=C2=A0 MMIO register, you need to hold the BQL. As you can quickly see,
it calls riscv_clic_clean_pending. That's why it should hold the BQL.

Zhiwei

Oh, I see.
The MMIO register reads and writes should also be protected by BQL.
Thanks for the explanation.

I am glad to know that you are reviewing this patch set. As Sifive implements the initial v0.7 CLIC, I think you may need this patch set for your SOC.
If you like to, I am happy to see that you connect this patch set to your SOC, and resend it again. I can also provide the qtest of this patch set if you need.

As you may see, the v6.1 soft freeze will come in July. I am afraid I can't upstream a new SOC in so short time.

Zhiwei

Thanks, I think we will levera= ge the hard works you have done into our implementation.
However,= I'm not sure I can catch up the deadline before v6.1's soft-freeze= .
But I think I can help to review the patches, at least we can s= peed up the review process.

Regarding qtest, I saw= your head commit mentioned the repo you are using: [1].
Is it ok= ay to just grab the qtest from this repo?

[1]:=C2=A0https://github.com/romanheros/qemu/commit/= bce1845ea9b079b4c360440292dc47725d1b24ab

T= hanks,
Frank Chang
=C2=A0


Regards,
Frank Chang
=C2=A0

Regard,
Frank Chang
=C2=A0
+=C2= =A0 =C2=A0 ready =3D get_xnxti_status(env);
+=C2=A0 =C2=A0 if (ready) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &cli= c_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (write_mask) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool edge = =3D riscv_clic_edge_triggered(env->clic, clic_priv, +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cs->cpu_index, clic_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (edge) = {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 riscv_clic_clean_pending(env->clic, clic_priv,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0cs->cpu_index, clic_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mi= ntstatus =3D set_field(env->mintstatus,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 MINTSTATUS_MIL, clic_il);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mc= ause =3D set_field(env->mcause, MCAUSE_EXCCODE, clic_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret_value) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *ret_value= =3D (env->mtvt & ~0x3f) + sizeof(target_ulong) * clic_irq;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret_value) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *ret_value= =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 qemu_mutex_unlock_iothread();
+=C2=A0 =C2=A0 return 0;
+}
+
=C2=A0static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *val)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0*val =3D env->mintstatus;
@@ -982,6 +1056,44 @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
=C2=A0 =C2=A0 =C2=A0return ret;
=C2=A0}

+static int rmw_snxti(CPURISCVState *env, int csrno, target_ulong *ret_value,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0target_ulong new_value, target_ulong write_mask)
+{
+=C2=A0 =C2=A0 int clic_priv, clic_il, clic_irq;
+=C2=A0 =C2=A0 bool ready;
+=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
+=C2=A0 =C2=A0 if (write_mask) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mstatus |=3D new= _value & (write_mask & 0b11111);
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 qemu_mutex_lock_iothread();
+=C2=A0 =C2=A0 ready =3D get_xnxti_status(env);
+=C2=A0 =C2=A0 if (ready) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_clic_decode_exccode(env->exccode, &clic_priv, &clic_il,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &cli= c_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (write_mask) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool edge = =3D riscv_clic_edge_triggered(env->clic, clic_priv, +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cs->cpu_index, clic_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (edge) = {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 riscv_clic_clean_pending(env->clic, clic_priv,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0cs->cpu_index, clic_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mi= ntstatus =3D set_field(env->mintstatus,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 MINTSTATUS_SIL, clic_il);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->sc= ause =3D set_field(env->scause, SCAUSE_EXCCODE, clic_irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret_value) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *ret_value= =3D (env->stvt & ~0x3f) + sizeof(target_ulong) * clic_irq;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret_value) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *ret_value= =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 qemu_mutex_unlock_iothread();
+=C2=A0 =C2=A0 return 0;
+}
+
=C2=A0static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *val)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0target_ulong mask =3D SINTSTATUS_= SIL | SINTSTATUS_UIL;
@@ -1755,6 +1867,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {

=C2=A0 =C2=A0 =C2=A0/* Machine Mode Core Level Interr= upt Controller */
=C2=A0 =C2=A0 =C2=A0[CSR_MTVT] =3D { "mtvt"= , clic,=C2=A0 read_mtvt,=C2=A0 write_mtvt=C2=A0 =C2=A0 =C2=A0 },
+=C2=A0 =C2=A0 [CSR_MNXTI] =3D { "mnxti", c= lic,=C2=A0 NULL,=C2=A0 NULL,=C2=A0 rmw_mnxti=C2=A0 =C2=A0},
=C2=A0 =C2=A0 =C2=A0[CSR_MINTSTATUS] =3D { "mint= status", clic,=C2=A0 read_mintstatus },
=C2=A0 =C2=A0 =C2=A0[CSR_MINTTHRESH] =3D { "mint= thresh", clic,=C2=A0 read_mintthresh,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 write_mintthresh },
@@ -1766,6 +1879,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {

=C2=A0 =C2=A0 =C2=A0/* Supervisor Mode Core Level Int= errupt Controller */
=C2=A0 =C2=A0 =C2=A0[CSR_STVT] =3D { "stvt"= , clic,=C2=A0 read_stvt, write_stvt=C2=A0 =C2=A0 =C2=A0 =C2=A0},
+=C2=A0 =C2=A0 [CSR_SNXTI] =3D { "snxti", c= lic,=C2=A0 NULL,=C2=A0 NULL,=C2=A0 rmw_snxti=C2=A0 =C2=A0},

=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
--
2.25.1


--0000000000009f383505c479d8b5--