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Tue, 27 Apr 2021 00:14:00 -0700 (PDT) MIME-Version: 1.0 References: <20210421041400.22243-1-frank.chang@sifive.com> <20210421041400.22243-3-frank.chang@sifive.com> In-Reply-To: From: Frank Chang <0xc0de0125@gmail.com> Date: Tue, 27 Apr 2021 15:13:49 +0800 Message-ID: Subject: Re: [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros To: Alistair Francis Content-Type: multipart/alternative; boundary="0000000000009cb02105c0ef0146" Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=0xc0de0125@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000009cb02105c0ef0146 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Alistair Francis =E6=96=BC 2021=E5=B9=B44=E6=9C=8827= =E6=97=A5 =E9=80=B1=E4=BA=8C =E4=B8=8B=E5=8D=882:05=E5=AF=AB=E9=81=93=EF=BC= =9A > On Wed, Apr 21, 2021 at 2:14 PM wrote: > > > > From: Kito Cheng > > > > Signed-off-by: Kito Cheng > > Signed-off-by: Frank Chang > > Reviewed-by: Richard Henderson > > --- > > target/riscv/insn32-64.decode | 4 +++ > > target/riscv/insn32.decode | 7 +++- > > target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++ > > target/riscv/translate.c | 42 ++++++++++++++++++++++ > > 4 files changed, 99 insertions(+), 1 deletion(-) > > create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc > > > > diff --git a/target/riscv/insn32-64.decode > b/target/riscv/insn32-64.decode > > index 8157dee8b7c..f4c42720fc7 100644 > > --- a/target/riscv/insn32-64.decode > > +++ b/target/riscv/insn32-64.decode > > @@ -86,3 +86,7 @@ fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 > > hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 > > hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 > > hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s > > + > > +# *** RV64B Standard Extension (in addition to RV32B) *** > > +clzw 0110000 00000 ..... 001 ..... 0011011 @r2 > > +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > > index 3823b3ea800..8fe838cf0d0 100644 > > --- a/target/riscv/insn32.decode > > +++ b/target/riscv/insn32.decode > > @@ -40,6 +40,7 @@ > > &i imm rs1 rd > > &j imm rd > > &r rd rs1 rs2 > > +&r2 rd rs1 > > &s imm rs1 rs2 > > &u imm rd > > &shift shamt rs1 rd > > @@ -67,7 +68,7 @@ > > @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %r= d > > @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd > > @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd > > -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd > > +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd > > @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %= rd > > @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd > > @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd > > @@ -592,3 +593,7 @@ vcompress_vm 010111 - ..... ..... 010 ..... > 1010111 @r > > > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > > + > > +# *** RV32B Standard Extension *** > > +clz 011000 000000 ..... 001 ..... 0010011 @r2 > > +ctz 011000 000001 ..... 001 ..... 0010011 @r2 > > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc > b/target/riscv/insn_trans/trans_rvb.c.inc > > new file mode 100644 > > index 00000000000..76788c2f353 > > --- /dev/null > > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > > @@ -0,0 +1,47 @@ > > +/* > > + * RISC-V translation routines for the RVB Standard Extension. > > + * > > + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com > > + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com > > + * > > + * This program is free software; you can redistribute it and/or modif= y > it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2 or later, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but > WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY = or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License > along with > > + * this program. If not, see . > > + */ > > + > > +static bool trans_clz(DisasContext *ctx, arg_clz *a) > > +{ > > + REQUIRE_EXT(ctx, RVB); > > + return gen_unary(ctx, a, gen_clz); > > +} > > + > > +static bool trans_ctz(DisasContext *ctx, arg_ctz *a) > > +{ > > + REQUIRE_EXT(ctx, RVB); > > + return gen_unary(ctx, a, gen_ctz); > > +} > > + > > +/* RV64-only instructions */ > > +#ifdef TARGET_RISCV64 > > + > > +static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > > +{ > > + REQUIRE_EXT(ctx, RVB); > > + return gen_unary(ctx, a, gen_clzw); > > +} > > + > > +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) > > +{ > > + REQUIRE_EXT(ctx, RVB); > > + return gen_unary(ctx, a, gen_ctzw); > > +} > > + > > +#endif > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > > index 2f9f5ccc621..4648c422f42 100644 > > --- a/target/riscv/translate.c > > +++ b/target/riscv/translate.c > > @@ -536,6 +536,23 @@ static bool gen_arith_div_uw(DisasContext *ctx, > arg_r *a, > > > > #endif > > > > +#ifdef TARGET_RISCV64 > > Thanks for the patches! > > Unfortunately this will need to be rebased and updated. We don't want > any more #ifdef's on the RISC-V xlen. The idea is to make the XLEN not > just a compile time constant. > > The latest riscv-to-apply.next tree has changes to allow you to do > this. See this commit for what this will look like: > > https://github.com/alistair23/qemu/commit/4965ae3f6f3838e651d1a33050b15b4= ca3d822a0 > > The changes should be in master after the 6.0 release. > > Alistair > Thanks, I will rebase my patchset. Frank Chang > > > + > > +static void gen_ctzw(TCGv ret, TCGv arg1) > > +{ > > + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32)); > > + tcg_gen_ctzi_i64(ret, ret, 64); > > +} > > + > > +static void gen_clzw(TCGv ret, TCGv arg1) > > +{ > > + tcg_gen_ext32u_i64(ret, arg1); > > + tcg_gen_clzi_i64(ret, ret, 64); > > + tcg_gen_subi_i64(ret, ret, 32); > > +} > > + > > +#endif > > + > > static bool gen_arith(DisasContext *ctx, arg_r *a, > > void(*func)(TCGv, TCGv, TCGv)) > > { > > @@ -581,6 +598,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase= , > target_ulong pc) > > return cpu_ldl_code(env, pc); > > } > > > > +static void gen_ctz(TCGv ret, TCGv arg1) > > +{ > > + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); > > +} > > + > > +static void gen_clz(TCGv ret, TCGv arg1) > > +{ > > + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); > > +} > > + > > +static bool gen_unary(DisasContext *ctx, arg_r2 *a, > > + void(*func)(TCGv, TCGv)) > > +{ > > + TCGv source =3D tcg_temp_new(); > > + > > + gen_get_gpr(source, a->rs1); > > + > > + (*func)(source, source); > > + > > + gen_set_gpr(a->rd, source); > > + tcg_temp_free(source); > > + return true; > > +} > > + > > /* Include insn module translation function */ > > #include "insn_trans/trans_rvi.c.inc" > > #include "insn_trans/trans_rvm.c.inc" > > @@ -589,6 +630,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, > target_ulong pc) > > #include "insn_trans/trans_rvd.c.inc" > > #include "insn_trans/trans_rvh.c.inc" > > #include "insn_trans/trans_rvv.c.inc" > > +#include "insn_trans/trans_rvb.c.inc" > > #include "insn_trans/trans_privileged.c.inc" > > > > /* Include the auto-generated decoder for 16 bit insn */ > > -- > > 2.17.1 > > > > > > --0000000000009cb02105c0ef0146 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Alistair Francis <alistair23@gmail.com> =E6=96=BC 2021=E5=B9=B44= =E6=9C=8827=E6=97=A5 =E9=80=B1=E4=BA=8C =E4=B8=8B=E5=8D=882:05=E5=AF=AB=E9= =81=93=EF=BC=9A
On Wed, Apr 21, 2021 at 2:14 PM <frank.chang@sifive.com&= gt; wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>=C2=A0 target/riscv/insn32-64.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0|=C2=A0 4 +++
>=C2=A0 target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 7 +++-
>=C2=A0 target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++= ++++++
>=C2=A0 target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 | 42 ++++++++++++++++++++++
>=C2=A0 4 files changed, 99 insertions(+), 1 deletion(-)
>=C2=A0 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.de= code
> index 8157dee8b7c..f4c42720fc7 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -86,3 +86,7 @@ fmv_d_x=C2=A0 =C2=A0 1111001=C2=A0 00000 ..... 000 .= .... 1010011 @r2
>=C2=A0 hlv_wu=C2=A0 =C2=A0 0110100=C2=A0 00001=C2=A0 =C2=A0..... 100 ..= ... 1110011 @r2
>=C2=A0 hlv_d=C2=A0 =C2=A0 =C2=A00110110=C2=A0 00000=C2=A0 =C2=A0..... 1= 00 ..... 1110011 @r2
>=C2=A0 hsv_d=C2=A0 =C2=A0 =C2=A00110111=C2=A0 .....=C2=A0 =C2=A0..... 1= 00 00000 1110011 @r2_s
> +
> +# *** RV64B Standard Extension (in addition to RV32B) ***
> +clzw=C2=A0 =C2=A0 =C2=A0 =C2=A00110000 00000 ..... 001 ..... 0011011 = @r2
> +ctzw=C2=A0 =C2=A0 =C2=A0 =C2=A00110000 00001 ..... 001 ..... 0011011 = @r2
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 3823b3ea800..8fe838cf0d0 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -40,6 +40,7 @@
>=C2=A0 &i=C2=A0 =C2=A0 imm rs1 rd
>=C2=A0 &j=C2=A0 =C2=A0 imm rd
>=C2=A0 &r=C2=A0 =C2=A0 rd rs1 rs2
> +&r2=C2=A0 =C2=A0rd rs1
>=C2=A0 &s=C2=A0 =C2=A0 imm rs1 rs2
>=C2=A0 &u=C2=A0 =C2=A0 imm rd
>=C2=A0 &shift=C2=A0 =C2=A0 =C2=A0shamt rs1 rd
> @@ -67,7 +68,7 @@
>=C2=A0 @r4_rm=C2=A0 =C2=A0..... ..=C2=A0 ..... ..... ... ..... ....... = %rs3 %rs2 %rs1 %rm %rd
>=C2=A0 @r_rm=C2=A0 =C2=A0 .......=C2=A0 =C2=A0..... ..... ... ..... ...= .... %rs2 %rs1 %rm %rd
>=C2=A0 @r2_rm=C2=A0 =C2=A0.......=C2=A0 =C2=A0..... ..... ... ..... ...= .... %rs1 %rm %rd
> -@r2=C2=A0 =C2=A0 =C2=A0 .......=C2=A0 =C2=A0..... ..... ... ..... ...= .... %rs1 %rd
> +@r2=C2=A0 =C2=A0 =C2=A0 .......=C2=A0 =C2=A0..... ..... ... ..... ...= .... &r2 %rs1 %rd
>=C2=A0 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm = %nf %rs1 %rd
>=C2=A0 @r2_vm=C2=A0 =C2=A0...... vm:1 ..... ..... ... ..... ....... &am= p;rmr %rs2 %rd
>=C2=A0 @r1_vm=C2=A0 =C2=A0...... vm:1 ..... ..... ... ..... ....... %rd=
> @@ -592,3 +593,7 @@ vcompress_vm=C2=A0 =C2=A0 010111 - ..... ..... 010= ..... 1010111 @r
>
>=C2=A0 vsetvli=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00 ........... ..... 111= ..... 1010111=C2=A0 @r2_zimm
>=C2=A0 vsetvl=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 1000000 ..... ..... 111= ..... 1010111=C2=A0 @r
> +
> +# *** RV32B Standard Extension ***
> +clz=C2=A0 =C2=A0 =C2=A0 =C2=A0 011000 000000 ..... 001 ..... 0010011 = @r2
> +ctz=C2=A0 =C2=A0 =C2=A0 =C2=A0 011000 000001 ..... 001 ..... 0010011 = @r2
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/in= sn_trans/trans_rvb.c.inc
> new file mode 100644
> index 00000000000..76788c2f353
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -0,0 +1,47 @@
> +/*
> + * RISC-V translation routines for the RVB Standard Extension.
> + *
> + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> + *
> + * This program is free software; you can redistribute it and/or modi= fy it
> + * under the terms and conditions of the GNU General Public License,<= br> > + * version 2 or later, as published by the Free Software Foundation.<= br> > + *
> + * This program is distributed in the hope it will be useful, but WIT= HOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY= or
> + * FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU General Public= License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License = along with
> + * this program.=C2=A0 If not, see <http://www.gnu.org/licenses= />.
> + */
> +
> +static bool trans_clz(DisasContext *ctx, arg_clz *a)
> +{
> +=C2=A0 =C2=A0 REQUIRE_EXT(ctx, RVB);
> +=C2=A0 =C2=A0 return gen_unary(ctx, a, gen_clz);
> +}
> +
> +static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> +{
> +=C2=A0 =C2=A0 REQUIRE_EXT(ctx, RVB);
> +=C2=A0 =C2=A0 return gen_unary(ctx, a, gen_ctz);
> +}
> +
> +/* RV64-only instructions */
> +#ifdef TARGET_RISCV64
> +
> +static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> +{
> +=C2=A0 =C2=A0 REQUIRE_EXT(ctx, RVB);
> +=C2=A0 =C2=A0 return gen_unary(ctx, a, gen_clzw);
> +}
> +
> +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> +{
> +=C2=A0 =C2=A0 REQUIRE_EXT(ctx, RVB);
> +=C2=A0 =C2=A0 return gen_unary(ctx, a, gen_ctzw);
> +}
> +
> +#endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2f9f5ccc621..4648c422f42 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -536,6 +536,23 @@ static bool gen_arith_div_uw(DisasContext *ctx, a= rg_r *a,
>
>=C2=A0 #endif
>
> +#ifdef TARGET_RISCV64

Thanks for the patches!

Unfortunately this will need to be rebased and updated. We don't want any more #ifdef's on the RISC-V xlen. The idea is to make the XLEN not<= br> just a compile time constant.

The latest riscv-to-apply.next tree has changes to allow you to do
this. See this commit for what this will look like:
https://github.com= /alistair23/qemu/commit/4965ae3f6f3838e651d1a33050b15b4ca3d822a0

The changes should be in master after the 6.0 release.

Alistair

Thanks, I will rebase my patch= set.

Frank Chang
=C2=A0

> +
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> +=C2=A0 =C2=A0 tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32)); > +=C2=A0 =C2=A0 tcg_gen_ctzi_i64(ret, ret, 64);
> +}
> +
> +static void gen_clzw(TCGv ret, TCGv arg1)
> +{
> +=C2=A0 =C2=A0 tcg_gen_ext32u_i64(ret, arg1);
> +=C2=A0 =C2=A0 tcg_gen_clzi_i64(ret, ret, 64);
> +=C2=A0 =C2=A0 tcg_gen_subi_i64(ret, ret, 32);
> +}
> +
> +#endif
> +
>=C2=A0 static bool gen_arith(DisasContext *ctx, arg_r *a,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 void(*func)(TCGv, TCGv, TCGv))
>=C2=A0 {
> @@ -581,6 +598,30 @@ static uint32_t opcode_at(DisasContextBase *dcbas= e, target_ulong pc)
>=C2=A0 =C2=A0 =C2=A0 return cpu_ldl_code(env, pc);
>=C2=A0 }
>
> +static void gen_ctz(TCGv ret, TCGv arg1)
> +{
> +=C2=A0 =C2=A0 tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static void gen_clz(TCGv ret, TCGv arg1)
> +{
> +=C2=A0 =C2=A0 tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static bool gen_unary(DisasContext *ctx, arg_r2 *a,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 void(*func)(TCGv, TCGv))
> +{
> +=C2=A0 =C2=A0 TCGv source =3D tcg_temp_new();
> +
> +=C2=A0 =C2=A0 gen_get_gpr(source, a->rs1);
> +
> +=C2=A0 =C2=A0 (*func)(source, source);
> +
> +=C2=A0 =C2=A0 gen_set_gpr(a->rd, source);
> +=C2=A0 =C2=A0 tcg_temp_free(source);
> +=C2=A0 =C2=A0 return true;
> +}
> +
>=C2=A0 /* Include insn module translation function */
>=C2=A0 #include "insn_trans/trans_rvi.c.inc"
>=C2=A0 #include "insn_trans/trans_rvm.c.inc"
> @@ -589,6 +630,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase= , target_ulong pc)
>=C2=A0 #include "insn_trans/trans_rvd.c.inc"
>=C2=A0 #include "insn_trans/trans_rvh.c.inc"
>=C2=A0 #include "insn_trans/trans_rvv.c.inc"
> +#include "insn_trans/trans_rvb.c.inc"
>=C2=A0 #include "insn_trans/trans_privileged.c.inc"
>
>=C2=A0 /* Include the auto-generated decoder for 16 bit insn */
> --
> 2.17.1
>
>

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