LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:52寫道：

> The machine mode mclicbase CSR is an XLEN-bit read-only register providing
> the base address of CLIC memory mapped registers.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
>  hw/intc/riscv_clic.c | 1 +
>  target/riscv/cpu.h   | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/hw/intc/riscv_clic.c b/hw/intc/riscv_clic.c
> index 8ad534c506..e902dd4062 100644
> --- a/hw/intc/riscv_clic.c
> +++ b/hw/intc/riscv_clic.c
> @@ -715,6 +715,7 @@ static void riscv_clic_realize(DeviceState *dev, Error
> **errp)
>                                           &cpu->env, 1);
>          qdev_connect_gpio_out(dev, i, irq);
>          cpu->env.clic = clic;
> +        cpu->env.mclicbase = clic->mclicbase;
>      }
>  }
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b5fd796f98..b0b8565649 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -162,6 +162,7 @@ struct CPURISCVState {
>      uint32_t miclaim;
>      uint32_t mintstatus; /* clic-spec */
>      target_ulong mintthresh; /* clic-spec */
> +    target_ulong mclicbase; /* clic-spec */
>
>      target_ulong mie;
>      target_ulong mideleg;
> --
> 2.25.1
>
>
>
Is it because current spec doesn't specify the number of mclicbase CSR
(0x3??)
so you are not adding it into csr.c?

If so,

Reviewed-by: Frank Chang <frank.chang@sifive.com>