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Sun, 26 Mar 2023 12:04:18 -0700 (PDT) MIME-Version: 1.0 References: <20230317001203.18425-1-strahinja.p.jankovic@gmail.com> <20230317001203.18425-2-strahinja.p.jankovic@gmail.com> In-Reply-To: <20230317001203.18425-2-strahinja.p.jankovic@gmail.com> From: Niek Linnenbank Date: Sun, 26 Mar 2023 21:04:07 +0200 Message-ID: Subject: Re: [PATCH v2 1/4] hw/watchdog: Allwinner WDT emulation for system reset To: Strahinja Jankovic Cc: Peter Maydell , Beniamino Galvani , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Strahinja Jankovic Content-Type: multipart/alternative; boundary="00000000000019a3d005f7d24b99" Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=nieklinnenbank@gmail.com; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --00000000000019a3d005f7d24b99 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Strahinja, On Fri, Mar 17, 2023 at 1:13=E2=80=AFAM Strahinja Jankovic < strahinjapjankovic@gmail.com> wrote: > This patch adds basic support for Allwinner WDT. > Both sun4i and sun6i variants are supported. > However, interrupt generation is not supported, so WDT can be used only t= o > trigger system reset. > > Signed-off-by: Strahinja Jankovic > > --- > hw/watchdog/Kconfig | 4 + > hw/watchdog/allwinner-wdt.c | 416 ++++++++++++++++++++++++++++ > hw/watchdog/meson.build | 1 + > hw/watchdog/trace-events | 7 + > include/hw/watchdog/allwinner-wdt.h | 123 ++++++++ > 5 files changed, 551 insertions(+) > create mode 100644 hw/watchdog/allwinner-wdt.c > create mode 100644 include/hw/watchdog/allwinner-wdt.h > > diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig > index 66e1d029e3..861fd00334 100644 > --- a/hw/watchdog/Kconfig > +++ b/hw/watchdog/Kconfig > @@ -20,3 +20,7 @@ config WDT_IMX2 > > config WDT_SBSA > bool > + > +config ALLWINNER_WDT > + bool > + select PTIMER > diff --git a/hw/watchdog/allwinner-wdt.c b/hw/watchdog/allwinner-wdt.c > new file mode 100644 > index 0000000000..45a4a36ba7 > --- /dev/null > +++ b/hw/watchdog/allwinner-wdt.c > @@ -0,0 +1,416 @@ > +/* > + * Allwinner Watchdog emulation > + * > + * Copyright (C) 2023 Strahinja Jankovic > + * > + * This file is derived from Allwinner RTC, > + * by Niek Linnenbank. > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "qemu/units.h" > +#include "qemu/module.h" > +#include "trace.h" > +#include "hw/sysbus.h" > +#include "hw/registerfields.h" > +#include "hw/watchdog/allwinner-wdt.h" > +#include "sysemu/watchdog.h" > +#include "migration/vmstate.h" > + > +/* WDT registers */ > +enum { > + REG_IRQ_EN =3D 0, /* Watchdog interrupt enable */ > + REG_IRQ_STA, /* Watchdog interrupt status */ > + REG_CTRL, /* Watchdog control register */ > + REG_CFG, /* Watchdog configuration register */ > + REG_MODE, /* Watchdog mode register */ > +}; > + > +/* Universal WDT register flags */ > +#define WDT_RESTART_MASK (1 << 0) > +#define WDT_EN_MASK (1 << 0) > + > +/* sun4i specific WDT register flags */ > +#define RST_EN_SUN4I_MASK (1 << 1) > +#define INTV_VALUE_SUN4I_SHIFT (3) > +#define INTV_VALUE_SUN4I_MASK (0xfu << INTV_VALUE_SUN4I_SHIFT) > + > +/* sun6i specific WDT register flags */ > +#define RST_EN_SUN6I_MASK (1 << 0) > +#define KEY_FIELD_SUN6I_SHIFT (1) > +#define KEY_FIELD_SUN6I_MASK (0xfffu << KEY_FIELD_SUN6I_SHIFT) > +#define KEY_FIELD_SUN6I (0xA57u) > +#define INTV_VALUE_SUN6I_SHIFT (4) > +#define INTV_VALUE_SUN6I_MASK (0xfu << INTV_VALUE_SUN6I_SHIFT) > + > +/* Map of INTV_VALUE to 0.5s units. */ > +static const uint8_t allwinner_wdt_count_map[] =3D { > + 1, > + 2, > + 4, > + 6, > + 8, > + 10, > + 12, > + 16, > + 20, > + 24, > + 28, > + 32 > +}; > + > +/* WDT sun4i register map (offset to name) */ > +const uint8_t allwinner_wdt_sun4i_regmap[] =3D { > + [0x0000] =3D REG_CTRL, > + [0x0004] =3D REG_MODE, > +}; > + > +/* WDT sun6i register map (offset to name) */ > +const uint8_t allwinner_wdt_sun6i_regmap[] =3D { > + [0x0000] =3D REG_IRQ_EN, > + [0x0004] =3D REG_IRQ_STA, > + [0x0010] =3D REG_CTRL, > + [0x0014] =3D REG_CFG, > + [0x0018] =3D REG_MODE, > +}; > + > +static bool allwinner_wdt_sun4i_read(AwWdtState *s, uint32_t offset) > +{ > + /* no sun4i specific registers currently implemented */ > + return false; > +} > + > +static bool allwinner_wdt_sun4i_write(AwWdtState *s, uint32_t offset, > + uint32_t data) > +{ > + /* no sun4i specific registers currently implemented */ > + return false; > +} > + > +static bool allwinner_wdt_sun4i_can_reset_system(AwWdtState *s) > +{ > + if (s->regs[REG_MODE] & RST_EN_SUN6I_MASK) { > Should this function use the RST_EN_SUN4I_MASK instead? > + return true; > + } else { > + return false; > + } > +} > + > +static bool allwinner_wdt_sun4i_is_key_valid(AwWdtState *s, uint32_t val= ) > +{ > + /* sun4i has no key */ > + return true; > +} > + > +static uint8_t allwinner_wdt_sun4i_get_intv_value(AwWdtState *s) > +{ > + return ((s->regs[REG_MODE] & INTV_VALUE_SUN4I_MASK) >> > + INTV_VALUE_SUN4I_SHIFT); > +} > + > +static bool allwinner_wdt_sun6i_read(AwWdtState *s, uint32_t offset) > +{ > + const AwWdtClass *c =3D AW_WDT_GET_CLASS(s); > + > + switch (c->regmap[offset]) { > + case REG_IRQ_EN: > + case REG_IRQ_STA: > + case REG_CFG: > + return true; > + default: > + break; > + } > + return false; > +} > + > +static bool allwinner_wdt_sun6i_write(AwWdtState *s, uint32_t offset, > + uint32_t data) > +{ > + const AwWdtClass *c =3D AW_WDT_GET_CLASS(s); > + > + switch (c->regmap[offset]) { > + case REG_IRQ_EN: > + case REG_IRQ_STA: > + case REG_CFG: > + return true; > + default: > + break; > + } > + return false; > +} > + > +static bool allwinner_wdt_sun6i_can_reset_system(AwWdtState *s) > +{ > + if (s->regs[REG_CFG] & RST_EN_SUN6I_MASK) { > + return true; > + } else { > + return false; > + } > +} > + > +static bool allwinner_wdt_sun6i_is_key_valid(AwWdtState *s, uint32_t val= ) > +{ > + uint16_t key =3D (val & KEY_FIELD_SUN6I_MASK) >> KEY_FIELD_SUN6I_SHI= FT; > + return (key =3D=3D KEY_FIELD_SUN6I); > +} > + > +static uint8_t allwinner_wdt_sun6i_get_intv_value(AwWdtState *s) > +{ > + return ((s->regs[REG_MODE] & INTV_VALUE_SUN6I_MASK) >> > + INTV_VALUE_SUN6I_SHIFT); > +} > + > +static void allwinner_wdt_update_timer(AwWdtState *s) > +{ > + const AwWdtClass *c =3D AW_WDT_GET_CLASS(s); > + uint8_t count =3D c->get_intv_value(s); > + > + ptimer_transaction_begin(s->timer); > + ptimer_stop(s->timer); > + > + /* Use map to convert. */ > + if (count < sizeof(allwinner_wdt_count_map)) { > + ptimer_set_count(s->timer, allwinner_wdt_count_map[count]); > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: incorrect INTV_VALUE > 0x%02x\n", > + __func__, count); > + } > + > + ptimer_run(s->timer, 1); > + ptimer_transaction_commit(s->timer); > + > + trace_allwinner_wdt_update_timer(count); > +} > + > +static uint64_t allwinner_wdt_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + AwWdtState *s =3D AW_WDT(opaque); > + const AwWdtClass *c =3D AW_WDT_GET_CLASS(s); > + uint64_t r; > + > + if (offset >=3D c->regmap_size) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset > 0x%04x\n", > + __func__, (uint32_t)offset); > + return 0; > + } > + > + switch (c->regmap[offset]) { > + case REG_CTRL: > + case REG_MODE: > + r =3D s->regs[c->regmap[offset]]; > + break; > + default: > + if (!c->read(s, offset)) { > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register > 0x%04x\n", > + __func__, (uint32_t)offset); > + return 0; > + } > + r =3D s->regs[c->regmap[offset]]; > + break; > + } > + > + trace_allwinner_wdt_read(offset, r, size); > + > + return r; > +} > + > +static void allwinner_wdt_write(void *opaque, hwaddr offset, > + uint64_t val, unsigned size) > +{ > + AwWdtState *s =3D AW_WDT(opaque); > + const AwWdtClass *c =3D AW_WDT_GET_CLASS(s); > + uint32_t old_val; > + > + if (offset >=3D c->regmap_size) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset > 0x%04x\n", > + __func__, (uint32_t)offset); > + return; > + } > + > + trace_allwinner_wdt_write(offset, val, size); > + > + switch (c->regmap[offset]) { > + case REG_CTRL: > + if (c->is_key_valid(s, val)) { > + if (val & WDT_RESTART_MASK) { > + /* Kick timer */ > + allwinner_wdt_update_timer(s); > + } > + } > + break; > + case REG_MODE: > + old_val =3D s->regs[REG_MODE]; > + s->regs[REG_MODE] =3D (uint32_t)val; > + > + /* Check for rising edge on WDOG_MODE_EN */ > + if ((s->regs[REG_MODE] & ~old_val) & WDT_EN_MASK) { > + allwinner_wdt_update_timer(s); > + } > + break; > + default: > + if (!c->write(s, offset, val)) { > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register > 0x%04x\n", > + __func__, (uint32_t)offset); > + } > + s->regs[c->regmap[offset]] =3D (uint32_t)val; > + break; > + } > +} > + > +static const MemoryRegionOps allwinner_wdt_ops =3D { > + .read =3D allwinner_wdt_read, > + .write =3D allwinner_wdt_write, > + .endianness =3D DEVICE_NATIVE_ENDIAN, > + .valid =3D { > + .min_access_size =3D 4, > + .max_access_size =3D 4, > + }, > + .impl.min_access_size =3D 4, > +}; > + > +static void allwinner_wdt_expired(void *opaque) > +{ > + AwWdtState *s =3D AW_WDT(opaque); > + const AwWdtClass *c =3D AW_WDT_GET_CLASS(s); > + > + bool enabled =3D s->regs[REG_MODE] & WDT_EN_MASK; > + bool reset_enabled =3D c->can_reset_system(s); > + > + trace_allwinner_wdt_expired(enabled, reset_enabled); > + > + /* Perform watchdog action if watchdog is enabled and can trigger > reset */ > + if (enabled && reset_enabled) { > + watchdog_perform_action(); > + } > +} > + > +static void allwinner_wdt_reset_enter(Object *obj, ResetType type) > +{ > + AwWdtState *s =3D AW_WDT(obj); > + > + trace_allwinner_wdt_reset_enter(); > + > + /* Clear registers */ > + memset(s->regs, 0, sizeof(s->regs)); > +} > + > +static const VMStateDescription allwinner_wdt_vmstate =3D { > + .name =3D "allwinner-wdt", > + .version_id =3D 1, > + .minimum_version_id =3D 1, > + .fields =3D (VMStateField[]) { > + VMSTATE_PTIMER(timer, AwWdtState), > + VMSTATE_UINT32_ARRAY(regs, AwWdtState, AW_WDT_REGS_NUM), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void allwinner_wdt_init(Object *obj) > +{ > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); > + AwWdtState *s =3D AW_WDT(obj); > + const AwWdtClass *c =3D AW_WDT_GET_CLASS(s); > + > + /* Memory mapping */ > + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_wdt_ops, s, > + TYPE_AW_WDT, c->regmap_size * 4); > + sysbus_init_mmio(sbd, &s->iomem); > +} > + > +static void allwinner_wdt_realize(DeviceState *dev, Error **errp) > +{ > + AwWdtState *s =3D AW_WDT(dev); > + > + s->timer =3D ptimer_init(allwinner_wdt_expired, s, > + PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | > + PTIMER_POLICY_NO_IMMEDIATE_RELOAD | > + PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); > + > + ptimer_transaction_begin(s->timer); > + /* Set to 2Hz (0.5s period); other periods are multiples of 0.5s. */ > + ptimer_set_freq(s->timer, 2); > + ptimer_set_limit(s->timer, 0xff, 1); > + ptimer_transaction_commit(s->timer); > +} > + > +static void allwinner_wdt_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + ResettableClass *rc =3D RESETTABLE_CLASS(klass); > + > + rc->phases.enter =3D allwinner_wdt_reset_enter; > + dc->realize =3D allwinner_wdt_realize; > + dc->vmsd =3D &allwinner_wdt_vmstate; > +} > + > +static void allwinner_wdt_sun4i_class_init(ObjectClass *klass, void *dat= a) > +{ > + AwWdtClass *awc =3D AW_WDT_CLASS(klass); > + > + awc->regmap =3D allwinner_wdt_sun4i_regmap; > + awc->regmap_size =3D sizeof(allwinner_wdt_sun4i_regmap); > + awc->read =3D allwinner_wdt_sun4i_read; > + awc->write =3D allwinner_wdt_sun4i_write; > + awc->can_reset_system =3D allwinner_wdt_sun4i_can_reset_system; > + awc->is_key_valid =3D allwinner_wdt_sun4i_is_key_valid; > + awc->get_intv_value =3D allwinner_wdt_sun4i_get_intv_value; > +} > + > +static void allwinner_wdt_sun6i_class_init(ObjectClass *klass, void *dat= a) > +{ > + AwWdtClass *awc =3D AW_WDT_CLASS(klass); > + > + awc->regmap =3D allwinner_wdt_sun6i_regmap; > + awc->regmap_size =3D sizeof(allwinner_wdt_sun6i_regmap); > + awc->read =3D allwinner_wdt_sun6i_read; > + awc->write =3D allwinner_wdt_sun6i_write; > + awc->can_reset_system =3D allwinner_wdt_sun6i_can_reset_system; > + awc->is_key_valid =3D allwinner_wdt_sun6i_is_key_valid; > + awc->get_intv_value =3D allwinner_wdt_sun6i_get_intv_value; > +} > + > +static const TypeInfo allwinner_wdt_info =3D { > + .name =3D TYPE_AW_WDT, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_init =3D allwinner_wdt_init, > + .instance_size =3D sizeof(AwWdtState), > + .class_init =3D allwinner_wdt_class_init, > + .class_size =3D sizeof(AwWdtClass), > + .abstract =3D true, > +}; > + > +static const TypeInfo allwinner_wdt_sun4i_info =3D { > + .name =3D TYPE_AW_WDT_SUN4I, > + .parent =3D TYPE_AW_WDT, > + .class_init =3D allwinner_wdt_sun4i_class_init, > +}; > + > +static const TypeInfo allwinner_wdt_sun6i_info =3D { > + .name =3D TYPE_AW_WDT_SUN6I, > + .parent =3D TYPE_AW_WDT, > + .class_init =3D allwinner_wdt_sun6i_class_init, > +}; > + > +static void allwinner_wdt_register(void) > +{ > + type_register_static(&allwinner_wdt_info); > + type_register_static(&allwinner_wdt_sun4i_info); > + type_register_static(&allwinner_wdt_sun6i_info); > +} > + > +type_init(allwinner_wdt_register) > diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build > index 8974b5cf4c..5dcd4fbe2f 100644 > --- a/hw/watchdog/meson.build > +++ b/hw/watchdog/meson.build > @@ -1,4 +1,5 @@ > softmmu_ss.add(files('watchdog.c')) > +softmmu_ss.add(when: 'CONFIG_ALLWINNER_WDT', if_true: > files('allwinner-wdt.c')) > softmmu_ss.add(when: 'CONFIG_CMSDK_APB_WATCHDOG', if_true: > files('cmsdk-apb-watchdog.c')) > softmmu_ss.add(when: 'CONFIG_WDT_IB6300ESB', if_true: > files('wdt_i6300esb.c')) > softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c')) > diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events > index 54371ae075..2739570652 100644 > --- a/hw/watchdog/trace-events > +++ b/hw/watchdog/trace-events > @@ -1,5 +1,12 @@ > # See docs/devel/tracing.rst for syntax documentation. > > +# allwinner-wdt.c > +allwinner_wdt_read(uint64_t offset, uint64_t data, unsigned size) > "Allwinner watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u= " > +allwinner_wdt_write(uint64_t offset, uint64_t data, unsigned size) > "Allwinner watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %= u" > +allwinner_wdt_reset_enter(void) "Allwinner watchdog: reset" > +allwinner_wdt_update_timer(uint8_t count) "Allwinner watchdog: count %" > PRIu8 > +allwinner_wdt_expired(bool enabled, bool reset_enabled) "Allwinner > watchdog: enabled %u reset_enabled %u" > + > # cmsdk-apb-watchdog.c > cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) > "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u= " > cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) > "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %= u" > diff --git a/include/hw/watchdog/allwinner-wdt.h > b/include/hw/watchdog/allwinner-wdt.h > new file mode 100644 > index 0000000000..7fe41e20f2 > --- /dev/null > +++ b/include/hw/watchdog/allwinner-wdt.h > @@ -0,0 +1,123 @@ > +/* > + * Allwinner Watchdog emulation > + * > + * Copyright (C) 2023 Strahinja Jankovic > + * > + * This file is derived from Allwinner RTC, > + * by Niek Linnenbank. > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#ifndef HW_WATCHDOG_ALLWINNER_WDT_H > +#define HW_WATCHDOG_ALLWINNER_WDT_H > + > +#include "qom/object.h" > +#include "hw/ptimer.h" > +#include "hw/sysbus.h" > + > +/* > + * This is a model of the Allwinner watchdog. > + * Since watchdog registers belong to the timer module (and are shared > with the > + * RTC module), the interrupt line from watchdog is not handled right no= w. > + * In QEMU, we just wire up the watchdog reset to > watchdog_perform_action(), > + * at least for the moment. > + */ > + > +#define TYPE_AW_WDT "allwinner-wdt" > + > +/** Allwinner WDT sun4i family (A10, A12), also sun7i (A20) */ > +#define TYPE_AW_WDT_SUN4I TYPE_AW_WDT "-sun4i" > + > +/** Allwinner WDT sun6i family and newer (A31, H2+, H3, etc) */ > +#define TYPE_AW_WDT_SUN6I TYPE_AW_WDT "-sun6i" > + > +/** Number of WDT registers */ > +#define AW_WDT_REGS_NUM (5) > + > +OBJECT_DECLARE_TYPE(AwWdtState, AwWdtClass, AW_WDT) > + > +/** > + * Allwinner WDT object instance state. > + */ > +struct AwWdtState { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + MemoryRegion iomem; > + struct ptimer_state *timer; > + > + uint32_t regs[AW_WDT_REGS_NUM]; > +}; > + > +/** > + * Allwinner WDT class-level struct. > + * > + * This struct is filled by each sunxi device specific code > + * such that the generic code can use this struct to support > + * all devices. > + */ > +struct AwWdtClass { > + /*< private >*/ > + SysBusDeviceClass parent_class; > + /*< public >*/ > + > + /** Defines device specific register map */ > + const uint8_t *regmap; > + > + /** Size of the regmap in bytes */ > + size_t regmap_size; > + > + /** > + * Read device specific register > + * > + * @offset: register offset to read > + * @return true if register read successful, false otherwise > + */ > + bool (*read)(AwWdtState *s, uint32_t offset); > + > + /** > + * Write device specific register > + * > + * @offset: register offset to write > + * @data: value to set in register > + * @return true if register write successful, false otherwise > + */ > + bool (*write)(AwWdtState *s, uint32_t offset, uint32_t data); > + > + /** > + * Check if watchdog can generate system reset > + * > + * @return true if watchdog can generate system reset > + */ > + bool (*can_reset_system)(AwWdtState *s); > + > + /** > + * Check if provided key is valid > + * > + * @value: value written to register > + * @return true if key is valid, false otherwise > + */ > + bool (*is_key_valid)(AwWdtState *s, uint32_t val); > + > + /** > + * Get current INTV_VALUE setting > + * > + * @return current INTV_VALUE (0-15) > + */ > + uint8_t (*get_intv_value)(AwWdtState *s); > +}; > + > +#endif /* HW_WATCHDOG_ALLWINNER_WDT_H */ > -- > 2.30.2 > > I've verified with U-boot manually that the watchdog also is able to reset the core on the H3: ... =3D> mw.l 0x01c20cb4 0x1 1 allwinner_wdt_write Allwinner watchdog write: offset 0x14 data 0x1 size 4 =3D> mw.l 0x01c20cb8 0x1 1 allwinner_wdt_write Allwinner watchdog write: offset 0x18 data 0x1 size 4 allwinner_wdt_update_timer Allwinner watchdog: count 0 =3D> allwinner_wdt_expired Allwinner watchdog: enabled 1 reset_enabled 1 allwinner_wdt_reset_enter Allwinner watchdog: reset U-Boot SPL 2020.04-armbian (Sep 02 2020 - 10:16:13 +0200) DRAM: 1024 MiB ... So looks good to me! Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank Regards, Niek --=20 Niek Linnenbank --00000000000019a3d005f7d24b99 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Strahinja,




On Fri, Mar 17, 2023 at 1:13=E2=80=AFAM Strahinja Jankovic= <strahinjapjankovic@gma= il.com> wrote:
This patch adds basic support for Allwinner WDT.
Both sun4i and sun6i variants are supported.
However, interrupt generation is not supported, so WDT can be used only to = trigger system reset.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

---
=C2=A0hw/watchdog/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 =C2=A04 +
=C2=A0hw/watchdog/allwinner-wdt.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 416 ++= ++++++++++++++++++++++++++
=C2=A0hw/watchdog/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0|=C2=A0 =C2=A01 +
=C2=A0hw/watchdog/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= =C2=A0 =C2=A07 +
=C2=A0include/hw/watchdog/allwinner-wdt.h | 123 ++++++++
=C2=A05 files changed, 551 insertions(+)
=C2=A0create mode 100644 hw/watchdog/allwinner-wdt.c
=C2=A0create mode 100644 include/hw/watchdog/allwinner-wdt.h

diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
index 66e1d029e3..861fd00334 100644
--- a/hw/watchdog/Kconfig
+++ b/hw/watchdog/Kconfig
@@ -20,3 +20,7 @@ config WDT_IMX2

=C2=A0config WDT_SBSA
=C2=A0 =C2=A0 =C2=A0bool
+
+config ALLWINNER_WDT
+=C2=A0 =C2=A0 bool
+=C2=A0 =C2=A0 select PTIMER
diff --git a/hw/watchdog/allwinner-wdt.c b/hw/watchdog/allwinner-wdt.c
new file mode 100644
index 0000000000..45a4a36ba7
--- /dev/null
+++ b/hw/watchdog/allwinner-wdt.c
@@ -0,0 +1,416 @@
+/*
+ * Allwinner Watchdog emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com&g= t;
+ *
+ *=C2=A0 This file is derived from Allwinner RTC,
+ *=C2=A0 by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.=C2=A0 If not, see <http://www.gnu.org/li= censes/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qemu/module.h"
+#include "trace.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/watchdog/allwinner-wdt.h"
+#include "sysemu/watchdog.h"
+#include "migration/vmstate.h"
+
+/* WDT registers */
+enum {
+=C2=A0 =C2=A0 REG_IRQ_EN =3D 0,=C2=A0 =C2=A0 =C2=A0/* Watchdog interrupt e= nable */
+=C2=A0 =C2=A0 REG_IRQ_STA,=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Watchdog interrup= t status */
+=C2=A0 =C2=A0 REG_CTRL,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Watchdo= g control register */
+=C2=A0 =C2=A0 REG_CFG,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Watchdo= g configuration register */
+=C2=A0 =C2=A0 REG_MODE,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Watchdo= g mode register */
+};
+
+/* Universal WDT register flags */
+#define WDT_RESTART_MASK=C2=A0 =C2=A0 (1 << 0)
+#define WDT_EN_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)
+
+/* sun4i specific WDT register flags */
+#define RST_EN_SUN4I_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 1)
+#define INTV_VALUE_SUN4I_SHIFT=C2=A0 (3)
+#define INTV_VALUE_SUN4I_MASK=C2=A0 =C2=A0(0xfu << INTV_VALUE_SUN4I_= SHIFT)
+
+/* sun6i specific WDT register flags */
+#define RST_EN_SUN6I_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)
+#define KEY_FIELD_SUN6I_SHIFT=C2=A0 =C2=A0(1)
+#define KEY_FIELD_SUN6I_MASK=C2=A0 =C2=A0 (0xfffu << KEY_FIELD_SUN6I= _SHIFT)
+#define KEY_FIELD_SUN6I=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0xA57u)
+#define INTV_VALUE_SUN6I_SHIFT=C2=A0 (4)
+#define INTV_VALUE_SUN6I_MASK=C2=A0 =C2=A0(0xfu << INTV_VALUE_SUN6I_= SHIFT)
+
+/* Map of INTV_VALUE to 0.5s units. */
+static const uint8_t allwinner_wdt_count_map[] =3D {
+=C2=A0 =C2=A0 1,
+=C2=A0 =C2=A0 2,
+=C2=A0 =C2=A0 4,
+=C2=A0 =C2=A0 6,
+=C2=A0 =C2=A0 8,
+=C2=A0 =C2=A0 10,
+=C2=A0 =C2=A0 12,
+=C2=A0 =C2=A0 16,
+=C2=A0 =C2=A0 20,
+=C2=A0 =C2=A0 24,
+=C2=A0 =C2=A0 28,
+=C2=A0 =C2=A0 32
+};
+
+/* WDT sun4i register map (offset to name) */
+const uint8_t allwinner_wdt_sun4i_regmap[] =3D {
+=C2=A0 =C2=A0 [0x0000] =3D REG_CTRL,
+=C2=A0 =C2=A0 [0x0004] =3D REG_MODE,
+};
+
+/* WDT sun6i register map (offset to name) */
+const uint8_t allwinner_wdt_sun6i_regmap[] =3D {
+=C2=A0 =C2=A0 [0x0000] =3D REG_IRQ_EN,
+=C2=A0 =C2=A0 [0x0004] =3D REG_IRQ_STA,
+=C2=A0 =C2=A0 [0x0010] =3D REG_CTRL,
+=C2=A0 =C2=A0 [0x0014] =3D REG_CFG,
+=C2=A0 =C2=A0 [0x0018] =3D REG_MODE,
+};
+
+static bool allwinner_wdt_sun4i_read(AwWdtState *s, uint32_t offset)
+{
+=C2=A0 =C2=A0 /* no sun4i specific registers currently implemented */
+=C2=A0 =C2=A0 return false;
+}
+
+static bool allwinner_wdt_sun4i_write(AwWdtState *s, uint32_t offset,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t data)<= br> +{
+=C2=A0 =C2=A0 /* no sun4i specific registers currently implemented */
+=C2=A0 =C2=A0 return false;
+}
+
+static bool allwinner_wdt_sun4i_can_reset_system(AwWdtState *s)
+{
+=C2=A0 =C2=A0 if (s->regs[REG_MODE] & RST_EN_SUN6I_MASK) {

Should this function use the RST_EN_SUN4I_MASK = instead?
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;
+=C2=A0 =C2=A0 }
+}
+
+static bool allwinner_wdt_sun4i_is_key_valid(AwWdtState *s, uint32_t val)<= br> +{
+=C2=A0 =C2=A0 /* sun4i has no key */
+=C2=A0 =C2=A0 return true;
+}
+
+static uint8_t allwinner_wdt_sun4i_get_intv_value(AwWdtState *s)
+{
+=C2=A0 =C2=A0 return ((s->regs[REG_MODE] & INTV_VALUE_SUN4I_MASK) &= gt;>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 INTV_VALUE_SUN4I_SHIFT);
+}
+
+static bool allwinner_wdt_sun6i_read(AwWdtState *s, uint32_t offset)
+{
+=C2=A0 =C2=A0 const AwWdtClass *c =3D AW_WDT_GET_CLASS(s);
+
+=C2=A0 =C2=A0 switch (c->regmap[offset]) {
+=C2=A0 =C2=A0 case REG_IRQ_EN:
+=C2=A0 =C2=A0 case REG_IRQ_STA:
+=C2=A0 =C2=A0 case REG_CFG:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 return false;
+}
+
+static bool allwinner_wdt_sun6i_write(AwWdtState *s, uint32_t offset,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t data)<= br> +{
+=C2=A0 =C2=A0 const AwWdtClass *c =3D AW_WDT_GET_CLASS(s);
+
+=C2=A0 =C2=A0 switch (c->regmap[offset]) {
+=C2=A0 =C2=A0 case REG_IRQ_EN:
+=C2=A0 =C2=A0 case REG_IRQ_STA:
+=C2=A0 =C2=A0 case REG_CFG:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 return false;
+}
+
+static bool allwinner_wdt_sun6i_can_reset_system(AwWdtState *s)
+{
+=C2=A0 =C2=A0 if (s->regs[REG_CFG] & RST_EN_SUN6I_MASK) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;
+=C2=A0 =C2=A0 }
+}
+
+static bool allwinner_wdt_sun6i_is_key_valid(AwWdtState *s, uint32_t val)<= br> +{
+=C2=A0 =C2=A0 uint16_t key =3D (val & KEY_FIELD_SUN6I_MASK) >> K= EY_FIELD_SUN6I_SHIFT;
+=C2=A0 =C2=A0 return (key =3D=3D KEY_FIELD_SUN6I);
+}
+
+static uint8_t allwinner_wdt_sun6i_get_intv_value(AwWdtState *s)
+{
+=C2=A0 =C2=A0 return ((s->regs[REG_MODE] & INTV_VALUE_SUN6I_MASK) &= gt;>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 INTV_VALUE_SUN6I_SHIFT);
+}
+
+static void allwinner_wdt_update_timer(AwWdtState *s)
+{
+=C2=A0 =C2=A0 const AwWdtClass *c =3D AW_WDT_GET_CLASS(s);
+=C2=A0 =C2=A0 uint8_t count =3D c->get_intv_value(s);
+
+=C2=A0 =C2=A0 ptimer_transaction_begin(s->timer);
+=C2=A0 =C2=A0 ptimer_stop(s->timer);
+
+=C2=A0 =C2=A0 /* Use map to convert. */
+=C2=A0 =C2=A0 if (count < sizeof(allwinner_wdt_count_map)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ptimer_set_count(s->timer, allwinner_wdt_co= unt_map[count]);
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: incor= rect INTV_VALUE 0x%02x\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 __func__, count);<= br> +=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 ptimer_run(s->timer, 1);
+=C2=A0 =C2=A0 ptimer_transaction_commit(s->timer);
+
+=C2=A0 =C2=A0 trace_allwinner_wdt_update_timer(count);
+}
+
+static uint64_t allwinner_wdt_read(void *opaque, hwaddr offset,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned = size)
+{
+=C2=A0 =C2=A0 AwWdtState *s =3D AW_WDT(opaque);
+=C2=A0 =C2=A0 const AwWdtClass *c =3D AW_WDT_GET_CLASS(s);
+=C2=A0 =C2=A0 uint64_t r;
+
+=C2=A0 =C2=A0 if (offset >=3D c->regmap_size) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-o= f-bounds offset 0x%04x\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 __func__, (uint32_t)offset);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 switch (c->regmap[offset]) {
+=C2=A0 =C2=A0 case REG_CTRL:
+=C2=A0 =C2=A0 case REG_MODE:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r =3D s->regs[c->regmap[offset]];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!c->read(s, offset)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_UNIMP, "%= s: unimplemented register 0x%04x\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 __func__, (uint32_t)offset);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r =3D s->regs[c->regmap[offset]];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 trace_allwinner_wdt_read(offset, r, size);
+
+=C2=A0 =C2=A0 return r;
+}
+
+static void allwinner_wdt_write(void *opaque, hwaddr offset,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t val, unsigned = size)
+{
+=C2=A0 =C2=A0 AwWdtState *s =3D AW_WDT(opaque);
+=C2=A0 =C2=A0 const AwWdtClass *c =3D AW_WDT_GET_CLASS(s);
+=C2=A0 =C2=A0 uint32_t old_val;
+
+=C2=A0 =C2=A0 if (offset >=3D c->regmap_size) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-o= f-bounds offset 0x%04x\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 __func__, (uint32_t)offset);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0trace_allwinner_wdt_write(offset, val, size);
+
+=C2=A0 =C2=A0 switch (c->regmap[offset]) {
+=C2=A0 =C2=A0 case REG_CTRL:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (c->is_key_valid(s, val)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (val & WDT_RESTART_MASK) = {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Kick timer */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 allwinner_wdt_upda= te_timer(s);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case REG_MODE:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 old_val =3D s->regs[REG_MODE];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[REG_MODE] =3D (uint32_t)val;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Check for rising edge on WDOG_MODE_EN */ +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((s->regs[REG_MODE] & ~old_val) &= ; WDT_EN_MASK) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 allwinner_wdt_update_timer(s); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!c->write(s, offset, val)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_UNIMP, "%= s: unimplemented register 0x%04x\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 __func__, (uint32_t)offset);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[c->regmap[offset]] =3D (uint32_t= )val;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+}
+
+static const MemoryRegionOps allwinner_wdt_ops =3D {
+=C2=A0 =C2=A0 .read =3D allwinner_wdt_read,
+=C2=A0 =C2=A0 .write =3D allwinner_wdt_write,
+=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
+=C2=A0 =C2=A0 .valid =3D {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 4,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4,
+=C2=A0 =C2=A0 },
+=C2=A0 =C2=A0 .impl.min_access_size =3D 4,
+};
+
+static void allwinner_wdt_expired(void *opaque)
+{
+=C2=A0 =C2=A0 AwWdtState *s =3D AW_WDT(opaque);
+=C2=A0 =C2=A0 const AwWdtClass *c =3D AW_WDT_GET_CLASS(s);
+
+=C2=A0 =C2=A0 bool enabled =3D s->regs[REG_MODE] & WDT_EN_MASK;
+=C2=A0 =C2=A0 bool reset_enabled =3D c->can_reset_system(s);
+
+=C2=A0 =C2=A0 trace_allwinner_wdt_expired(enabled, reset_enabled);
+
+=C2=A0 =C2=A0 /* Perform watchdog action if watchdog is enabled and can tr= igger reset */
+=C2=A0 =C2=A0 if (enabled && reset_enabled) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 watchdog_perform_action();
+=C2=A0 =C2=A0 }
+}
+
+static void allwinner_wdt_reset_enter(Object *obj, ResetType type)
+{
+=C2=A0 =C2=A0 AwWdtState *s =3D AW_WDT(obj);
+
+=C2=A0 =C2=A0 trace_allwinner_wdt_reset_enter();
+
+=C2=A0 =C2=A0 /* Clear registers */
+=C2=A0 =C2=A0 memset(s->regs, 0, sizeof(s->regs));
+}
+
+static const VMStateDescription allwinner_wdt_vmstate =3D {
+=C2=A0 =C2=A0 .name =3D "allwinner-wdt",
+=C2=A0 =C2=A0 .version_id =3D 1,
+=C2=A0 =C2=A0 .minimum_version_id =3D 1,
+=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_PTIMER(timer, AwWdtState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(regs, AwWdtState, AW_WDT_= REGS_NUM),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
+=C2=A0 =C2=A0 }
+};
+
+static void allwinner_wdt_init(Object *obj)
+{
+=C2=A0 =C2=A0 SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+=C2=A0 =C2=A0 AwWdtState *s =3D AW_WDT(obj);
+=C2=A0 =C2=A0 const AwWdtClass *c =3D AW_WDT_GET_CLASS(s);
+
+=C2=A0 =C2=A0 /* Memory mapping */
+=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, OBJECT(s), &allw= inner_wdt_ops, s,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 TYPE_AW_WDT, c->regmap_size * 4);
+=C2=A0 =C2=A0 sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void allwinner_wdt_realize(DeviceState *dev, Error **errp)
+{
+=C2=A0 =C2=A0 AwWdtState *s =3D AW_WDT(dev);
+
+=C2=A0 =C2=A0 s->timer =3D ptimer_init(allwinner_wdt_expired, s,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+
+=C2=A0 =C2=A0 ptimer_transaction_begin(s->timer);
+=C2=A0 =C2=A0 /* Set to 2Hz (0.5s period); other periods are multiples of = 0.5s. */
+=C2=A0 =C2=A0 ptimer_set_freq(s->timer, 2);
+=C2=A0 =C2=A0 ptimer_set_limit(s->timer, 0xff, 1);
+=C2=A0 =C2=A0 ptimer_transaction_commit(s->timer);
+}
+
+static void allwinner_wdt_class_init(ObjectClass *klass, void *data)
+{
+=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(klass);
+=C2=A0 =C2=A0 ResettableClass *rc =3D RESETTABLE_CLASS(klass);
+
+=C2=A0 =C2=A0 rc->phases.enter =3D allwinner_wdt_reset_enter;
+=C2=A0 =C2=A0 dc->realize =3D allwinner_wdt_realize;
+=C2=A0 =C2=A0 dc->vmsd =3D &allwinner_wdt_vmstate;
+}
+
+static void allwinner_wdt_sun4i_class_init(ObjectClass *klass, void *data)=
+{
+=C2=A0 =C2=A0 AwWdtClass *awc =3D AW_WDT_CLASS(klass);
+
+=C2=A0 =C2=A0 awc->regmap =3D allwinner_wdt_sun4i_regmap;
+=C2=A0 =C2=A0 awc->regmap_size =3D sizeof(allwinner_wdt_sun4i_regmap);<= br> +=C2=A0 =C2=A0 awc->read =3D allwinner_wdt_sun4i_read;
+=C2=A0 =C2=A0 awc->write =3D allwinner_wdt_sun4i_write;
+=C2=A0 =C2=A0 awc->can_reset_system =3D allwinner_wdt_sun4i_can_reset_s= ystem;
+=C2=A0 =C2=A0 awc->is_key_valid =3D allwinner_wdt_sun4i_is_key_valid; +=C2=A0 =C2=A0 awc->get_intv_value =3D allwinner_wdt_sun4i_get_intv_valu= e;
+}
+
+static void allwinner_wdt_sun6i_class_init(ObjectClass *klass, void *data)=
+{
+=C2=A0 =C2=A0 AwWdtClass *awc =3D AW_WDT_CLASS(klass);
+
+=C2=A0 =C2=A0 awc->regmap =3D allwinner_wdt_sun6i_regmap;
+=C2=A0 =C2=A0 awc->regmap_size =3D sizeof(allwinner_wdt_sun6i_regmap);<= br> +=C2=A0 =C2=A0 awc->read =3D allwinner_wdt_sun6i_read;
+=C2=A0 =C2=A0 awc->write =3D allwinner_wdt_sun6i_write;
+=C2=A0 =C2=A0 awc->can_reset_system =3D allwinner_wdt_sun6i_can_reset_s= ystem;
+=C2=A0 =C2=A0 awc->is_key_valid =3D allwinner_wdt_sun6i_is_key_valid; +=C2=A0 =C2=A0 awc->get_intv_value =3D allwinner_wdt_sun6i_get_intv_valu= e;
+}
+
+static const TypeInfo allwinner_wdt_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_WDT,
+=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEVICE,<= br> +=C2=A0 =C2=A0 .instance_init =3D allwinner_wdt_init,
+=C2=A0 =C2=A0 .instance_size =3D sizeof(AwWdtState),
+=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D allwinner_wdt_class_init,
+=C2=A0 =C2=A0 .class_size=C2=A0 =C2=A0 =3D sizeof(AwWdtClass),
+=C2=A0 =C2=A0 .abstract=C2=A0 =C2=A0 =C2=A0 =3D true,
+};
+
+static const TypeInfo allwinner_wdt_sun4i_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_WDT_SUN4= I,
+=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_WDT,
+=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D allwinner_wdt_sun4i_class_init,=
+};
+
+static const TypeInfo allwinner_wdt_sun6i_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_WDT_SUN6= I,
+=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_AW_WDT,
+=C2=A0 =C2=A0 .class_init=C2=A0 =C2=A0 =3D allwinner_wdt_sun6i_class_init,=
+};
+
+static void allwinner_wdt_register(void)
+{
+=C2=A0 =C2=A0 type_register_static(&allwinner_wdt_info);
+=C2=A0 =C2=A0 type_register_static(&allwinner_wdt_sun4i_info);
+=C2=A0 =C2=A0 type_register_static(&allwinner_wdt_sun6i_info);
+}
+
+type_init(allwinner_wdt_register)
diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build
index 8974b5cf4c..5dcd4fbe2f 100644
--- a/hw/watchdog/meson.build
+++ b/hw/watchdog/meson.build
@@ -1,4 +1,5 @@
=C2=A0softmmu_ss.add(files('watchdog.c'))
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_WDT', if_true: files('a= llwinner-wdt.c'))
=C2=A0softmmu_ss.add(when: 'CONFIG_CMSDK_APB_WATCHDOG', if_true: fi= les('cmsdk-apb-watchdog.c'))
=C2=A0softmmu_ss.add(when: 'CONFIG_WDT_IB6300ESB', if_true: files(&= #39;wdt_i6300esb.c'))
=C2=A0softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('= wdt_ib700.c'))
diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events
index 54371ae075..2739570652 100644
--- a/hw/watchdog/trace-events
+++ b/hw/watchdog/trace-events
@@ -1,5 +1,12 @@
=C2=A0# See docs/devel/tracing.rst for syntax documentation.

+# allwinner-wdt.c
+allwinner_wdt_read(uint64_t offset, uint64_t data, unsigned size) "Al= lwinner watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64= " size %u"
+allwinner_wdt_write(uint64_t offset, uint64_t data, unsigned size) "A= llwinner watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx= 64 " size %u"
+allwinner_wdt_reset_enter(void) "Allwinner watchdog: reset"
+allwinner_wdt_update_timer(uint8_t count) "Allwinner watchdog: count = %" PRIu8
+allwinner_wdt_expired(bool enabled, bool reset_enabled) "Allwinner wa= tchdog: enabled %u reset_enabled %u"
+
=C2=A0# cmsdk-apb-watchdog.c
=C2=A0cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size= ) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%&qu= ot; PRIx64 " size %u"
=C2=A0cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned siz= e) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%&= quot; PRIx64 " size %u"
diff --git a/include/hw/watchdog/allwinner-wdt.h b/include/hw/watchdog/allw= inner-wdt.h
new file mode 100644
index 0000000000..7fe41e20f2
--- /dev/null
+++ b/include/hw/watchdog/allwinner-wdt.h
@@ -0,0 +1,123 @@
+/*
+ * Allwinner Watchdog emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com&g= t;
+ *
+ *=C2=A0 This file is derived from Allwinner RTC,
+ *=C2=A0 by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.=C2=A0 If not, see <http://www.gnu.org/li= censes/>.
+ */
+
+#ifndef HW_WATCHDOG_ALLWINNER_WDT_H
+#define HW_WATCHDOG_ALLWINNER_WDT_H
+
+#include "qom/object.h"
+#include "hw/ptimer.h"
+#include "hw/sysbus.h"
+
+/*
+ * This is a model of the Allwinner watchdog.
+ * Since watchdog registers belong to the timer module (and are shared wit= h the
+ * RTC module), the interrupt line from watchdog is not handled right now.=
+ * In QEMU, we just wire up the watchdog reset to watchdog_perform_action(= ),
+ * at least for the moment.
+ */
+
+#define TYPE_AW_WDT=C2=A0 =C2=A0 "allwinner-wdt"
+
+/** Allwinner WDT sun4i family (A10, A12), also sun7i (A20) */
+#define TYPE_AW_WDT_SUN4I=C2=A0 =C2=A0 TYPE_AW_WDT "-sun4i"
+
+/** Allwinner WDT sun6i family and newer (A31, H2+, H3, etc) */
+#define TYPE_AW_WDT_SUN6I=C2=A0 =C2=A0 TYPE_AW_WDT "-sun6i"
+
+/** Number of WDT registers */
+#define AW_WDT_REGS_NUM=C2=A0 =C2=A0 =C2=A0 (5)
+
+OBJECT_DECLARE_TYPE(AwWdtState, AwWdtClass, AW_WDT)
+
+/**
+ * Allwinner WDT object instance state.
+ */
+struct AwWdtState {
+=C2=A0 =C2=A0 /*< private >*/
+=C2=A0 =C2=A0 SysBusDevice parent_obj;
+
+=C2=A0 =C2=A0 /*< public >*/
+=C2=A0 =C2=A0 MemoryRegion iomem;
+=C2=A0 =C2=A0 struct ptimer_state *timer;
+
+=C2=A0 =C2=A0 uint32_t regs[AW_WDT_REGS_NUM];
+};
+
+/**
+ * Allwinner WDT class-level struct.
+ *
+ * This struct is filled by each sunxi device specific code
+ * such that the generic code can use this struct to support
+ * all devices.
+ */
+struct AwWdtClass {
+=C2=A0 =C2=A0 /*< private >*/
+=C2=A0 =C2=A0 SysBusDeviceClass parent_class;
+=C2=A0 =C2=A0 /*< public >*/
+
+=C2=A0 =C2=A0 /** Defines device specific register map */
+=C2=A0 =C2=A0 const uint8_t *regmap;
+
+=C2=A0 =C2=A0 /** Size of the regmap in bytes */
+=C2=A0 =C2=A0 size_t regmap_size;
+
+=C2=A0 =C2=A0 /**
+=C2=A0 =C2=A0 =C2=A0* Read device specific register
+=C2=A0 =C2=A0 =C2=A0*
+=C2=A0 =C2=A0 =C2=A0* @offset: register offset to read
+=C2=A0 =C2=A0 =C2=A0* @return true if register read successful, false othe= rwise
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 bool (*read)(AwWdtState *s, uint32_t offset);
+
+=C2=A0 =C2=A0 /**
+=C2=A0 =C2=A0 =C2=A0* Write device specific register
+=C2=A0 =C2=A0 =C2=A0*
+=C2=A0 =C2=A0 =C2=A0* @offset: register offset to write
+=C2=A0 =C2=A0 =C2=A0* @data: value to set in register
+=C2=A0 =C2=A0 =C2=A0* @return true if register write successful, false oth= erwise
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 bool (*write)(AwWdtState *s, uint32_t offset, uint32_t data)= ;
+
+=C2=A0 =C2=A0 /**
+=C2=A0 =C2=A0 =C2=A0* Check if watchdog can generate system reset
+=C2=A0 =C2=A0 =C2=A0*
+=C2=A0 =C2=A0 =C2=A0* @return true if watchdog can generate system reset +=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 bool (*can_reset_system)(AwWdtState *s);
+
+=C2=A0 =C2=A0 /**
+=C2=A0 =C2=A0 =C2=A0* Check if provided key is valid
+=C2=A0 =C2=A0 =C2=A0*
+=C2=A0 =C2=A0 =C2=A0* @value: value written to register
+=C2=A0 =C2=A0 =C2=A0* @return true if key is valid, false otherwise
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 bool (*is_key_valid)(AwWdtState *s, uint32_t val);
+
+=C2=A0 =C2=A0 /**
+=C2=A0 =C2=A0 =C2=A0* Get current INTV_VALUE setting
+=C2=A0 =C2=A0 =C2=A0*
+=C2=A0 =C2=A0 =C2=A0* @return current INTV_VALUE (0-15)
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 uint8_t (*get_intv_value)(AwWdtState *s);
+};
+
+#endif /* HW_WATCHDOG_ALLWINNER_WDT_H */
--
2.30.2


I've verified with U-boot manual= ly that the watchdog also is able to reset the core on the H3:
...
=3D> mw.l 0x01c20cb4 0x1 1
allwinner_w= dt_write Allwinner watchdog write: offset 0x14 data 0x1 size 4
=3D> m= w.l 0x01c20cb8 0x1 1
allwinner_wdt_write Allwinner watchdog write: offse= t 0x18 data 0x1 size 4
allwinner_wdt_update_timer Allwinner watchdog: co= unt 0
=3D> allwinner_wdt_expired Allwinner watchdog: enabled 1 reset_= enabled 1
allwinner_wdt_reset_enter Allwinner watchdog: reset

U-B= oot SPL 2020.04-armbian (Sep 02 2020 - 10:16:13 +0200)
DRAM: 1024 MiB
...

So looks good to me!

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnen= bank <nieklinnenbank@gmail.c= om>

Regards,
Niek
--
Niek Linnenbank

<= /div>
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