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From: Niek Linnenbank <nieklinnenbank@gmail.com>
To: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Cc: "b.galvani@gmail.com" <b.galvani@gmail.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 04/10] arm: allwinner-h3: add USB host controller
Date: Wed, 4 Dec 2019 21:20:33 +0100
Message-ID: <CAPan3WrXiz-DxQ+ZV6F3bSPXMTeOLehD8i85WqqT3xPddPBwsw@mail.gmail.com> (raw)
In-Reply-To: <CAL1e-=gVMXsWKAdo8c8QtjAYeK6p0AyTmi_a-sFHL2x4wGq6Vg@mail.gmail.com>

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On Wed, Dec 4, 2019 at 5:11 PM Aleksandar Markovic <
aleksandar.m.mail@gmail.com> wrote:

>
>
> On Monday, December 2, 2019, Niek Linnenbank <nieklinnenbank@gmail.com>
> wrote:
>
>> The Allwinner H3 System on Chip contains multiple USB 2.0 bus
>> connections which provide software access using the Enhanced
>> Host Controller Interface (EHCI) and Open Host Controller
>> Interface (OHCI) interfaces. This commit adds support for
>> both interfaces in the Allwinner H3 System on Chip.
>>
>> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
>> ---
>
>
> Niek, hi!
>
> I would like to clarify a detail here:
>
> The spec of the SoC enumerates (in 8.5.2.4. USB Host Register List) a
> number of registers for reading various USB-related states, but also for
> setting some of USB features.
>
> Does this series cover these registers, and interaction with them? If yes,
> how and where? If not, do you think it is not necessary at all? Or perhaps
> that it is a non-crucial limitation of this series?
>

Hello Aleksandar!

Very good question, I will try to explain what I did to support USB for the
Allwinner H3 emulation.
EHCI and OHCI are both standardized interfaces to the USB bus and both
provide their own standardized software interface.
Because they are standards, operatings system drivers can implement a
generic driver which uses the defined interface and
re-use it in multiple boards/platforms. Things that can be different
between boards are, for example the base address in
memory where the registers are provided.

In QEMU I found that both the OHCI and EHCI host controllers are already
emulated and used by other boards as well. For example,
you can find the OHCI registers from 8.5.2.4 implemented in the file
hw/usb/hcd-ohci.c:1515 in ohci_mem_read(). So for the Allwinner
H3 I simply had to define the base address for both controllers and create
the objects. At that point, the Linux kernel can access
the USB bus with the generic EHCI/OHCI platform drivers. In the Linux code,
you can see in the file ./arch/arm/boot/dts/sunxi-h3-h5.dtsi:281
the definitions named ehci0-ehci3 and ohci0-ohci3 where it specifies in the
device tree configuration to load the generic drivers.


>
> Thanks in advance, and congrats for your, it seems, first submission!
>
>
Thank you Aleksandar! Indeed, it is my first submission. I will do my best
to
update the patches to comply with the QEMU coding style and best practises.

Regards,
Niek


> Aleksandar
>
>
>  hw/arm/allwinner-h3.c    | 20 ++++++++++++++++++++
>>  hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++
>>  hw/usb/hcd-ehci.h        |  1 +
>>  3 files changed, 38 insertions(+)
>>
>> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
>> index 5566e979ec..afeb49c0ac 100644
>> --- a/hw/arm/allwinner-h3.c
>> +++ b/hw/arm/allwinner-h3.c
>> @@ -26,6 +26,7 @@
>>  #include "hw/sysbus.h"
>>  #include "hw/arm/allwinner-h3.h"
>>  #include "hw/misc/unimp.h"
>> +#include "hw/usb/hcd-ehci.h"
>>  #include "sysemu/sysemu.h"
>>
>>  static void aw_h3_init(Object *obj)
>> @@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error
>> **errp)
>>      }
>>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, AW_H3_CCU_BASE);
>>
>> +    /* Universal Serial Bus */
>> +    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_EHCI0]);
>> +    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_EHCI1]);
>> +    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_EHCI2]);
>> +    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_EHCI3]);
>> +
>> +    sysbus_create_simple("sysbus-ohci", AW_H3_OHCI0_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_OHCI0]);
>> +    sysbus_create_simple("sysbus-ohci", AW_H3_OHCI1_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_OHCI1]);
>> +    sysbus_create_simple("sysbus-ohci", AW_H3_OHCI2_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_OHCI2]);
>> +    sysbus_create_simple("sysbus-ohci", AW_H3_OHCI3_BASE,
>> +                         s->irq[AW_H3_GIC_SPI_OHCI3]);
>> +
>>      /* UART */
>>      if (serial_hd(0)) {
>>          serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2,
>> diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
>> index 020211fd10..174c3446ef 100644
>> --- a/hw/usb/hcd-ehci-sysbus.c
>> +++ b/hw/usb/hcd-ehci-sysbus.c
>> @@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = {
>>      .class_init    = ehci_exynos4210_class_init,
>>  };
>>
>> +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
>> +{
>> +    SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
>> +    DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> +    sec->capsbase = 0x0;
>> +    sec->opregbase = 0x10;
>> +    set_bit(DEVICE_CATEGORY_USB, dc->categories);
>> +}
>> +
>> +static const TypeInfo ehci_aw_h3_type_info = {
>> +    .name          = TYPE_AW_H3_EHCI,
>> +    .parent        = TYPE_SYS_BUS_EHCI,
>> +    .class_init    = ehci_aw_h3_class_init,
>> +};
>> +
>>  static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
>>  {
>>      SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
>> @@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void)
>>      type_register_static(&ehci_platform_type_info);
>>      type_register_static(&ehci_xlnx_type_info);
>>      type_register_static(&ehci_exynos4210_type_info);
>> +    type_register_static(&ehci_aw_h3_type_info);
>>      type_register_static(&ehci_tegra2_type_info);
>>      type_register_static(&ehci_ppc4xx_type_info);
>>      type_register_static(&ehci_fusbh200_type_info);
>> diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
>> index 0298238f0b..edb59311c4 100644
>> --- a/hw/usb/hcd-ehci.h
>> +++ b/hw/usb/hcd-ehci.h
>> @@ -342,6 +342,7 @@ typedef struct EHCIPCIState {
>>  #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
>>  #define TYPE_PLATFORM_EHCI "platform-ehci-usb"
>>  #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
>> +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
>>  #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
>>  #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
>>  #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
>> --
>> 2.17.1
>>
>>
>>

-- 
Niek Linnenbank

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<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Dec 4, 2019 at 5:11 PM Aleksandar Markovic &lt;<a href="mailto:aleksandar.m.mail@gmail.com">aleksandar.m.mail@gmail.com</a>&gt; wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br><br>On Monday, December 2, 2019, Niek Linnenbank &lt;<a href="mailto:nieklinnenbank@gmail.com" target="_blank">nieklinnenbank@gmail.com</a>&gt; wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">The Allwinner H3 System on Chip contains multiple USB 2.0 bus<br>
connections which provide software access using the Enhanced<br>
Host Controller Interface (EHCI) and Open Host Controller<br>
Interface (OHCI) interfaces. This commit adds support for<br>
both interfaces in the Allwinner H3 System on Chip.<br>
<br>
Signed-off-by: Niek Linnenbank &lt;<a href="mailto:nieklinnenbank@gmail.com" target="_blank">nieklinnenbank@gmail.com</a>&gt;<br>
---</blockquote><div><br></div><div>Niek, hi!</div><div><br></div><div>I would like to clarify a detail here:</div><div><br></div><div>The spec of the SoC enumerates (in 8.5.2.4. USB Host Register List) a number of registers for reading various USB-related states, but also for setting some of USB features.</div><div> </div><div>Does this series cover these registers, and interaction with them? If yes, how and where? If not, do you think it is not necessary at all? Or perhaps that it is a non-crucial limitation of this series?</div></blockquote><div><br></div><div>Hello Aleksandar!</div><div><br></div><div>Very good question, I will try to explain what I did to support USB for the Allwinner H3 emulation.</div><div>EHCI and OHCI are both standardized interfaces to the USB bus and both provide their own standardized software interface.</div><div>Because they are standards, operatings system drivers can implement a generic driver which uses the defined interface and</div><div>re-use it in multiple boards/platforms. Things that can be different between boards are, for example the base address in</div><div>memory where the registers are provided.</div><div><br></div><div>In QEMU I found that both the OHCI and EHCI host controllers are already emulated and used by other boards as well. For example,</div><div>you can find the OHCI registers from 8.5.2.4 implemented in the file hw/usb/hcd-ohci.c:1515 in ohci_mem_read(). So for the Allwinner</div><div>H3 I simply had to define the base address for both controllers and create the objects. At that point, the Linux kernel can access</div><div>the USB bus with the generic EHCI/OHCI platform drivers. In the Linux code, you can see in the file ./arch/arm/boot/dts/sunxi-h3-h5.dtsi:281</div><div>the definitions named ehci0-ehci3 and ohci0-ohci3 where it specifies in the device tree configuration to load the generic drivers.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div><br></div><div>Thanks in advance, and congrats for your, it seems, first submission!</div><div><br></div></blockquote><div><br></div><div>Thank you Aleksandar! Indeed, it is my first submission. I will do my best to</div><div>update the patches to comply with the QEMU coding style and best practises.</div><div><br></div><div>Regards,</div><div>Niek<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div></div><div>Aleksandar</div><div><br></div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
 hw/arm/allwinner-h3.c    | 20 ++++++++++++++++++++<br>
 hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++<br>
 hw/usb/hcd-ehci.h        |  1 +<br>
 3 files changed, 38 insertions(+)<br>
<br>
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c<br>
index 5566e979ec..afeb49c0ac 100644<br>
--- a/hw/arm/allwinner-h3.c<br>
+++ b/hw/arm/allwinner-h3.c<br>
@@ -26,6 +26,7 @@<br>
 #include &quot;hw/sysbus.h&quot;<br>
 #include &quot;hw/arm/allwinner-h3.h&quot;<br>
 #include &quot;hw/misc/unimp.h&quot;<br>
+#include &quot;hw/usb/hcd-ehci.h&quot;<br>
 #include &quot;sysemu/sysemu.h&quot;<br>
<br>
 static void aw_h3_init(Object *obj)<br>
@@ -183,6 +184,25 @@ static void aw_h3_realize(DeviceState *dev, Error **errp)<br>
     }<br>
     sysbus_mmio_map(SYS_BUS_DEVICE(&amp;s-&gt;ccu), 0, AW_H3_CCU_BASE);<br>
<br>
+    /* Universal Serial Bus */<br>
+    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI0_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_EHCI0]);<br>
+    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI1_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_EHCI1]);<br>
+    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI2_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_EHCI2]);<br>
+    sysbus_create_simple(TYPE_AW_H3_EHCI, AW_H3_EHCI3_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_EHCI3]);<br>
+<br>
+    sysbus_create_simple(&quot;sysbus-ohci&quot;, AW_H3_OHCI0_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_OHCI0]);<br>
+    sysbus_create_simple(&quot;sysbus-ohci&quot;, AW_H3_OHCI1_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_OHCI1]);<br>
+    sysbus_create_simple(&quot;sysbus-ohci&quot;, AW_H3_OHCI2_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_OHCI2]);<br>
+    sysbus_create_simple(&quot;sysbus-ohci&quot;, AW_H3_OHCI3_BASE,<br>
+                         s-&gt;irq[AW_H3_GIC_SPI_OHCI3]);<br>
+<br>
     /* UART */<br>
     if (serial_hd(0)) {<br>
         serial_mm_init(get_system_memory(), AW_H3_UART0_REG_BASE, 2,<br>
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c<br>
index 020211fd10..174c3446ef 100644<br>
--- a/hw/usb/hcd-ehci-sysbus.c<br>
+++ b/hw/usb/hcd-ehci-sysbus.c<br>
@@ -145,6 +145,22 @@ static const TypeInfo ehci_exynos4210_type_info = {<br>
     .class_init    = ehci_exynos4210_class_init,<br>
 };<br>
<br>
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)<br>
+{<br>
+    SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);<br>
+    DeviceClass *dc = DEVICE_CLASS(oc);<br>
+<br>
+    sec-&gt;capsbase = 0x0;<br>
+    sec-&gt;opregbase = 0x10;<br>
+    set_bit(DEVICE_CATEGORY_USB, dc-&gt;categories);<br>
+}<br>
+<br>
+static const TypeInfo ehci_aw_h3_type_info = {<br>
+    .name          = TYPE_AW_H3_EHCI,<br>
+    .parent        = TYPE_SYS_BUS_EHCI,<br>
+    .class_init    = ehci_aw_h3_class_init,<br>
+};<br>
+<br>
 static void ehci_tegra2_class_init(ObjectClass *oc, void *data)<br>
 {<br>
     SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);<br>
@@ -267,6 +283,7 @@ static void ehci_sysbus_register_types(void)<br>
     type_register_static(&amp;ehci_platform_type_info);<br>
     type_register_static(&amp;ehci_xlnx_type_info);<br>
     type_register_static(&amp;ehci_exynos4210_type_info);<br>
+    type_register_static(&amp;ehci_aw_h3_type_info);<br>
     type_register_static(&amp;ehci_tegra2_type_info);<br>
     type_register_static(&amp;ehci_ppc4xx_type_info);<br>
     type_register_static(&amp;ehci_fusbh200_type_info);<br>
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h<br>
index 0298238f0b..edb59311c4 100644<br>
--- a/hw/usb/hcd-ehci.h<br>
+++ b/hw/usb/hcd-ehci.h<br>
@@ -342,6 +342,7 @@ typedef struct EHCIPCIState {<br>
 #define TYPE_SYS_BUS_EHCI &quot;sysbus-ehci-usb&quot;<br>
 #define TYPE_PLATFORM_EHCI &quot;platform-ehci-usb&quot;<br>
 #define TYPE_EXYNOS4210_EHCI &quot;exynos4210-ehci-usb&quot;<br>
+#define TYPE_AW_H3_EHCI &quot;aw-h3-ehci-usb&quot;<br>
 #define TYPE_TEGRA2_EHCI &quot;tegra2-ehci-usb&quot;<br>
 #define TYPE_PPC4xx_EHCI &quot;ppc4xx-ehci-usb&quot;<br>
 #define TYPE_FUSBH200_EHCI &quot;fusbh200-ehci-usb&quot;<br>
-- <br>
2.17.1<br>
<br>
<br>
</blockquote>
</blockquote></div><br clear="all"><br>-- <br><div dir="ltr" class="gmail_signature"><div dir="ltr"><div>Niek Linnenbank<br><br></div></div></div></div>

  reply index

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-02 21:09 [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine Niek Linnenbank
2019-12-02 21:09 ` [PATCH 01/10] hw: arm: add Allwinner H3 System-on-Chip Niek Linnenbank
2019-12-04 16:53   ` Philippe Mathieu-Daudé
2019-12-04 20:44     ` Niek Linnenbank
2019-12-10  9:02   ` Philippe Mathieu-Daudé
2019-12-10 19:17     ` Niek Linnenbank
2019-12-02 21:09 ` [PATCH 02/10] hw: arm: add Xunlong Orange Pi PC machine Niek Linnenbank
2019-12-03  9:17   ` Philippe Mathieu-Daudé
2019-12-03 19:33     ` Niek Linnenbank
2019-12-04  9:03       ` Philippe Mathieu-Daudé
2019-12-04 19:50         ` Niek Linnenbank
2019-12-05 22:15     ` Niek Linnenbank
2019-12-06  5:41       ` Philippe Mathieu-Daudé
2019-12-06 22:15         ` Niek Linnenbank
2019-12-10  8:59           ` Philippe Mathieu-Daudé
2019-12-10 19:14             ` Niek Linnenbank
2019-12-02 21:09 ` [PATCH 03/10] arm: allwinner-h3: add Clock Control Unit Niek Linnenbank
2019-12-02 21:09 ` [PATCH 04/10] arm: allwinner-h3: add USB host controller Niek Linnenbank
2019-12-04 16:11   ` Aleksandar Markovic
2019-12-04 20:20     ` Niek Linnenbank [this message]
2019-12-10  7:56   ` Philippe Mathieu-Daudé
2019-12-10  8:29     ` Gerd Hoffmann
2019-12-10 19:11       ` Niek Linnenbank
2019-12-02 21:09 ` [PATCH 05/10] arm: allwinner-h3: add System Control module Niek Linnenbank
2019-12-02 21:09 ` [PATCH 06/10] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() Niek Linnenbank
2019-12-06 14:24   ` Peter Maydell
2019-12-06 20:01     ` Niek Linnenbank
2019-12-02 21:09 ` [PATCH 07/10] arm: allwinner-h3: add CPU Configuration module Niek Linnenbank
2019-12-02 21:09 ` [PATCH 08/10] arm: allwinner-h3: add Security Identifier device Niek Linnenbank
2019-12-06 14:27   ` Peter Maydell
2019-12-06 16:35     ` Philippe Mathieu-Daudé
2019-12-06 20:20       ` Niek Linnenbank
2019-12-02 21:09 ` [PATCH 09/10] arm: allwinner-h3: add SD/MMC host controller Niek Linnenbank
2019-12-02 21:09 ` [PATCH 10/10] arm: allwinner-h3: add EMAC ethernet device Niek Linnenbank
2019-12-03  9:33   ` KONRAD Frederic
2019-12-03 19:41     ` Niek Linnenbank
2019-12-04 15:14     ` Philippe Mathieu-Daudé
2019-12-04 15:22       ` KONRAD Frederic
2019-12-03  8:47 ` [PATCH 00/10] Add Allwinner H3 SoC and Orange Pi PC Machine Philippe Mathieu-Daudé
2019-12-03 19:25   ` Niek Linnenbank
2019-12-10  8:40     ` Philippe Mathieu-Daudé
2019-12-09 21:37   ` Niek Linnenbank
2019-12-10  8:26     ` Philippe Mathieu-Daudé
2019-12-10 20:12       ` Niek Linnenbank
2019-12-03  9:02 ` Philippe Mathieu-Daudé
2019-12-03 19:32   ` Niek Linnenbank
2019-12-06 14:16     ` Peter Maydell
2019-12-09 22:24       ` Aleksandar Markovic
2019-12-10 10:34 ` KONRAD Frederic
2019-12-10 19:55   ` Niek Linnenbank

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Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git