* [PATCH v2 00/48] tcg: optimize redundant sign extensions
@ 2021-10-07 19:54 Richard Henderson
2021-10-07 19:54 ` [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask" Richard Henderson
` (49 more replies)
0 siblings, 50 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
But targets like Alpha, MIPS, and RISC-V do sign-extensions instead.
The last 5 patches address this.
But before that, split the quite massive tcg_optimize function.
Changes for v2:
* Rebase, adjusting MemOpIdx renaming.
* Apply r-b and some feedback (f4bug).
r~
Richard Henderson (48):
tcg/optimize: Rename "mask" to "z_mask"
tcg/optimize: Split out OptContext
tcg/optimize: Remove do_default label
tcg/optimize: Change tcg_opt_gen_{mov,movi} interface
tcg/optimize: Move prev_mb into OptContext
tcg/optimize: Split out init_arguments
tcg/optimize: Split out copy_propagate
tcg/optimize: Split out fold_call
tcg/optimize: Drop nb_oargs, nb_iargs locals
tcg/optimize: Change fail return for do_constant_folding_cond*
tcg/optimize: Return true from tcg_opt_gen_{mov,movi}
tcg/optimize: Split out finish_folding
tcg/optimize: Use a boolean to avoid a mass of continues
tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}
tcg/optimize: Split out fold_const{1,2}
tcg/optimize: Split out fold_setcond2
tcg/optimize: Split out fold_brcond2
tcg/optimize: Split out fold_brcond
tcg/optimize: Split out fold_setcond
tcg/optimize: Split out fold_mulu2_i32
tcg/optimize: Split out fold_addsub2_i32
tcg/optimize: Split out fold_movcond
tcg/optimize: Split out fold_extract2
tcg/optimize: Split out fold_extract, fold_sextract
tcg/optimize: Split out fold_deposit
tcg/optimize: Split out fold_count_zeros
tcg/optimize: Split out fold_bswap
tcg/optimize: Split out fold_dup, fold_dup2
tcg/optimize: Split out fold_mov
tcg/optimize: Split out fold_xx_to_i
tcg/optimize: Split out fold_xx_to_x
tcg/optimize: Split out fold_xi_to_i
tcg/optimize: Add type to OptContext
tcg/optimize: Split out fold_to_not
tcg/optimize: Split out fold_sub_to_neg
tcg/optimize: Split out fold_xi_to_x
tcg/optimize: Split out fold_ix_to_i
tcg/optimize: Split out fold_masks
tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies
tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
tcg/optimize: Sink commutative operand swapping into fold functions
tcg/optimize: Add more simplifications for orc
tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values
tcg/optimize: Optimize sign extensions
tcg/optimize: Propagate sign info for logical operations
tcg/optimize: Propagate sign info for setcond
tcg/optimize: Propagate sign info for bit counting
tcg/optimize: Propagate sign info for shifting
tcg/optimize.c | 2602 +++++++++++++++++++++++++++++-------------------
1 file changed, 1585 insertions(+), 1017 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask"
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-19 15:23 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 02/48] tcg/optimize: Split out OptContext Richard Henderson
` (48 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Prepare for tracking different masks by renaming this one.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 142 +++++++++++++++++++++++++------------------------
1 file changed, 72 insertions(+), 70 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c239c3bd07..148e360fc6 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -41,7 +41,7 @@ typedef struct TempOptInfo {
TCGTemp *prev_copy;
TCGTemp *next_copy;
uint64_t val;
- uint64_t mask;
+ uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
} TempOptInfo;
static inline TempOptInfo *ts_info(TCGTemp *ts)
@@ -81,7 +81,7 @@ static void reset_ts(TCGTemp *ts)
ti->next_copy = ts;
ti->prev_copy = ts;
ti->is_const = false;
- ti->mask = -1;
+ ti->z_mask = -1;
}
static void reset_temp(TCGArg arg)
@@ -111,14 +111,14 @@ static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts)
if (ts->kind == TEMP_CONST) {
ti->is_const = true;
ti->val = ts->val;
- ti->mask = ts->val;
+ ti->z_mask = ts->val;
if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
/* High bits of a 32-bit quantity are garbage. */
- ti->mask |= ~0xffffffffull;
+ ti->z_mask |= ~0xffffffffull;
}
} else {
ti->is_const = false;
- ti->mask = -1;
+ ti->z_mask = -1;
}
}
@@ -186,7 +186,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
const TCGOpDef *def;
TempOptInfo *di;
TempOptInfo *si;
- uint64_t mask;
+ uint64_t z_mask;
TCGOpcode new_op;
if (ts_are_copies(dst_ts, src_ts)) {
@@ -210,12 +210,12 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
op->args[0] = dst;
op->args[1] = src;
- mask = si->mask;
+ z_mask = si->z_mask;
if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
/* High bits of the destination are now garbage. */
- mask |= ~0xffffffffull;
+ z_mask |= ~0xffffffffull;
}
- di->mask = mask;
+ di->z_mask = z_mask;
if (src_ts->type == dst_ts->type) {
TempOptInfo *ni = ts_info(si->next_copy);
@@ -621,7 +621,7 @@ void tcg_optimize(TCGContext *s)
}
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
- uint64_t mask, partmask, affected, tmp;
+ uint64_t z_mask, partmask, affected, tmp;
int nb_oargs, nb_iargs;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
@@ -855,170 +855,172 @@ void tcg_optimize(TCGContext *s)
/* Simplify using known-zero bits. Currently only ops with a single
output argument is supported. */
- mask = -1;
+ z_mask = -1;
affected = -1;
switch (opc) {
CASE_OP_32_64(ext8s):
- if ((arg_info(op->args[1])->mask & 0x80) != 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x80) != 0) {
break;
}
QEMU_FALLTHROUGH;
CASE_OP_32_64(ext8u):
- mask = 0xff;
+ z_mask = 0xff;
goto and_const;
CASE_OP_32_64(ext16s):
- if ((arg_info(op->args[1])->mask & 0x8000) != 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) {
break;
}
QEMU_FALLTHROUGH;
CASE_OP_32_64(ext16u):
- mask = 0xffff;
+ z_mask = 0xffff;
goto and_const;
case INDEX_op_ext32s_i64:
- if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
break;
}
QEMU_FALLTHROUGH;
case INDEX_op_ext32u_i64:
- mask = 0xffffffffU;
+ z_mask = 0xffffffffU;
goto and_const;
CASE_OP_32_64(and):
- mask = arg_info(op->args[2])->mask;
+ z_mask = arg_info(op->args[2])->z_mask;
if (arg_is_const(op->args[2])) {
and_const:
- affected = arg_info(op->args[1])->mask & ~mask;
+ affected = arg_info(op->args[1])->z_mask & ~z_mask;
}
- mask = arg_info(op->args[1])->mask & mask;
+ z_mask = arg_info(op->args[1])->z_mask & z_mask;
break;
case INDEX_op_ext_i32_i64:
- if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
+ if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
break;
}
QEMU_FALLTHROUGH;
case INDEX_op_extu_i32_i64:
/* We do not compute affected as it is a size changing op. */
- mask = (uint32_t)arg_info(op->args[1])->mask;
+ z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
break;
CASE_OP_32_64(andc):
/* Known-zeros does not imply known-ones. Therefore unless
op->args[2] is constant, we can't infer anything from it. */
if (arg_is_const(op->args[2])) {
- mask = ~arg_info(op->args[2])->mask;
+ z_mask = ~arg_info(op->args[2])->z_mask;
goto and_const;
}
/* But we certainly know nothing outside args[1] may be set. */
- mask = arg_info(op->args[1])->mask;
+ z_mask = arg_info(op->args[1])->z_mask;
break;
case INDEX_op_sar_i32:
if (arg_is_const(op->args[2])) {
tmp = arg_info(op->args[2])->val & 31;
- mask = (int32_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
case INDEX_op_sar_i64:
if (arg_is_const(op->args[2])) {
tmp = arg_info(op->args[2])->val & 63;
- mask = (int64_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
case INDEX_op_shr_i32:
if (arg_is_const(op->args[2])) {
tmp = arg_info(op->args[2])->val & 31;
- mask = (uint32_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
case INDEX_op_shr_i64:
if (arg_is_const(op->args[2])) {
tmp = arg_info(op->args[2])->val & 63;
- mask = (uint64_t)arg_info(op->args[1])->mask >> tmp;
+ z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp;
}
break;
case INDEX_op_extrl_i64_i32:
- mask = (uint32_t)arg_info(op->args[1])->mask;
+ z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
break;
case INDEX_op_extrh_i64_i32:
- mask = (uint64_t)arg_info(op->args[1])->mask >> 32;
+ z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32;
break;
CASE_OP_32_64(shl):
if (arg_is_const(op->args[2])) {
tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
- mask = arg_info(op->args[1])->mask << tmp;
+ z_mask = arg_info(op->args[1])->z_mask << tmp;
}
break;
CASE_OP_32_64(neg):
/* Set to 1 all bits to the left of the rightmost. */
- mask = -(arg_info(op->args[1])->mask
- & -arg_info(op->args[1])->mask);
+ z_mask = -(arg_info(op->args[1])->z_mask
+ & -arg_info(op->args[1])->z_mask);
break;
CASE_OP_32_64(deposit):
- mask = deposit64(arg_info(op->args[1])->mask,
- op->args[3], op->args[4],
- arg_info(op->args[2])->mask);
+ z_mask = deposit64(arg_info(op->args[1])->z_mask,
+ op->args[3], op->args[4],
+ arg_info(op->args[2])->z_mask);
break;
CASE_OP_32_64(extract):
- mask = extract64(arg_info(op->args[1])->mask,
- op->args[2], op->args[3]);
+ z_mask = extract64(arg_info(op->args[1])->z_mask,
+ op->args[2], op->args[3]);
if (op->args[2] == 0) {
- affected = arg_info(op->args[1])->mask & ~mask;
+ affected = arg_info(op->args[1])->z_mask & ~z_mask;
}
break;
CASE_OP_32_64(sextract):
- mask = sextract64(arg_info(op->args[1])->mask,
- op->args[2], op->args[3]);
- if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
- affected = arg_info(op->args[1])->mask & ~mask;
+ z_mask = sextract64(arg_info(op->args[1])->z_mask,
+ op->args[2], op->args[3]);
+ if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) {
+ affected = arg_info(op->args[1])->z_mask & ~z_mask;
}
break;
CASE_OP_32_64(or):
CASE_OP_32_64(xor):
- mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask;
+ z_mask = arg_info(op->args[1])->z_mask
+ | arg_info(op->args[2])->z_mask;
break;
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
- mask = arg_info(op->args[2])->mask | 31;
+ z_mask = arg_info(op->args[2])->z_mask | 31;
break;
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- mask = arg_info(op->args[2])->mask | 63;
+ z_mask = arg_info(op->args[2])->z_mask | 63;
break;
case INDEX_op_ctpop_i32:
- mask = 32 | 31;
+ z_mask = 32 | 31;
break;
case INDEX_op_ctpop_i64:
- mask = 64 | 63;
+ z_mask = 64 | 63;
break;
CASE_OP_32_64(setcond):
case INDEX_op_setcond2_i32:
- mask = 1;
+ z_mask = 1;
break;
CASE_OP_32_64(movcond):
- mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask;
+ z_mask = arg_info(op->args[3])->z_mask
+ | arg_info(op->args[4])->z_mask;
break;
CASE_OP_32_64(ld8u):
- mask = 0xff;
+ z_mask = 0xff;
break;
CASE_OP_32_64(ld16u):
- mask = 0xffff;
+ z_mask = 0xffff;
break;
case INDEX_op_ld32u_i64:
- mask = 0xffffffffu;
+ z_mask = 0xffffffffu;
break;
CASE_OP_32_64(qemu_ld):
@@ -1026,43 +1028,43 @@ void tcg_optimize(TCGContext *s)
MemOpIdx oi = op->args[nb_oargs + nb_iargs];
MemOp mop = get_memop(oi);
if (!(mop & MO_SIGN)) {
- mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
+ z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
}
}
break;
CASE_OP_32_64(bswap16):
- mask = arg_info(op->args[1])->mask;
- if (mask <= 0xffff) {
+ z_mask = arg_info(op->args[1])->z_mask;
+ if (z_mask <= 0xffff) {
op->args[2] |= TCG_BSWAP_IZ;
}
- mask = bswap16(mask);
+ z_mask = bswap16(z_mask);
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
case TCG_BSWAP_OZ:
break;
case TCG_BSWAP_OS:
- mask = (int16_t)mask;
+ z_mask = (int16_t)z_mask;
break;
default: /* undefined high bits */
- mask |= MAKE_64BIT_MASK(16, 48);
+ z_mask |= MAKE_64BIT_MASK(16, 48);
break;
}
break;
case INDEX_op_bswap32_i64:
- mask = arg_info(op->args[1])->mask;
- if (mask <= 0xffffffffu) {
+ z_mask = arg_info(op->args[1])->z_mask;
+ if (z_mask <= 0xffffffffu) {
op->args[2] |= TCG_BSWAP_IZ;
}
- mask = bswap32(mask);
+ z_mask = bswap32(z_mask);
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
case TCG_BSWAP_OZ:
break;
case TCG_BSWAP_OS:
- mask = (int32_t)mask;
+ z_mask = (int32_t)z_mask;
break;
default: /* undefined high bits */
- mask |= MAKE_64BIT_MASK(32, 32);
+ z_mask |= MAKE_64BIT_MASK(32, 32);
break;
}
break;
@@ -1074,9 +1076,9 @@ void tcg_optimize(TCGContext *s)
/* 32-bit ops generate 32-bit results. For the result is zero test
below, we can ignore high bits, but for further optimizations we
need to record that the high bits contain garbage. */
- partmask = mask;
+ partmask = z_mask;
if (!(def->flags & TCG_OPF_64BIT)) {
- mask |= ~(tcg_target_ulong)0xffffffffu;
+ z_mask |= ~(tcg_target_ulong)0xffffffffu;
partmask &= 0xffffffffu;
affected &= 0xffffffffu;
}
@@ -1472,7 +1474,7 @@ void tcg_optimize(TCGContext *s)
vs the high word of the input. */
do_setcond_high:
reset_temp(op->args[0]);
- arg_info(op->args[0])->mask = 1;
+ arg_info(op->args[0])->z_mask = 1;
op->opc = INDEX_op_setcond_i32;
op->args[1] = op->args[2];
op->args[2] = op->args[4];
@@ -1498,7 +1500,7 @@ void tcg_optimize(TCGContext *s)
}
do_setcond_low:
reset_temp(op->args[0]);
- arg_info(op->args[0])->mask = 1;
+ arg_info(op->args[0])->z_mask = 1;
op->opc = INDEX_op_setcond_i32;
op->args[2] = op->args[3];
op->args[3] = op->args[5];
@@ -1543,7 +1545,7 @@ void tcg_optimize(TCGContext *s)
/* Default case: we know nothing about operation (or were unable
to compute the operation result) so no propagation is done.
We trash everything if the operation is the end of a basic
- block, otherwise we only trash the output args. "mask" is
+ block, otherwise we only trash the output args. "z_mask" is
the non-zero bits mask for the first output arg. */
if (def->flags & TCG_OPF_BB_END) {
memset(&temps_used, 0, sizeof(temps_used));
@@ -1554,7 +1556,7 @@ void tcg_optimize(TCGContext *s)
/* Save the corresponding known-zero bits mask for the
first output argument (only one supported so far). */
if (i == 0) {
- arg_info(op->args[i])->mask = mask;
+ arg_info(op->args[i])->z_mask = z_mask;
}
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 02/48] tcg/optimize: Split out OptContext
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
2021-10-07 19:54 ` [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask" Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-19 15:25 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 03/48] tcg/optimize: Remove do_default label Richard Henderson
` (47 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Provide what will become a larger context for splitting
the very large tcg_optimize function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 77 ++++++++++++++++++++++++++------------------------
1 file changed, 40 insertions(+), 37 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 148e360fc6..b76991215e 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -44,6 +44,10 @@ typedef struct TempOptInfo {
uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
} TempOptInfo;
+typedef struct OptContext {
+ TCGTempSet temps_used;
+} OptContext;
+
static inline TempOptInfo *ts_info(TCGTemp *ts)
{
return ts->state_ptr;
@@ -90,15 +94,15 @@ static void reset_temp(TCGArg arg)
}
/* Initialize and activate a temporary. */
-static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts)
+static void init_ts_info(OptContext *ctx, TCGTemp *ts)
{
size_t idx = temp_idx(ts);
TempOptInfo *ti;
- if (test_bit(idx, temps_used->l)) {
+ if (test_bit(idx, ctx->temps_used.l)) {
return;
}
- set_bit(idx, temps_used->l);
+ set_bit(idx, ctx->temps_used.l);
ti = ts->state_ptr;
if (ti == NULL) {
@@ -122,9 +126,9 @@ static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts)
}
}
-static void init_arg_info(TCGTempSet *temps_used, TCGArg arg)
+static void init_arg_info(OptContext *ctx, TCGArg arg)
{
- init_ts_info(temps_used, arg_temp(arg));
+ init_ts_info(ctx, arg_temp(arg));
}
static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
@@ -229,7 +233,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
}
}
-static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used,
+static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx,
TCGOp *op, TCGArg dst, uint64_t val)
{
const TCGOpDef *def = &tcg_op_defs[op->opc];
@@ -246,7 +250,7 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used,
/* Convert movi to mov with constant temp. */
tv = tcg_constant_internal(type, val);
- init_ts_info(temps_used, tv);
+ init_ts_info(ctx, tv);
tcg_opt_gen_mov(s, op, dst, temp_arg(tv));
}
@@ -605,7 +609,7 @@ void tcg_optimize(TCGContext *s)
{
int nb_temps, nb_globals, i;
TCGOp *op, *op_next, *prev_mb = NULL;
- TCGTempSet temps_used;
+ OptContext ctx = {};
/* Array VALS has an element for each temp.
If this temp holds a constant then its value is kept in VALS' element.
@@ -615,7 +619,6 @@ void tcg_optimize(TCGContext *s)
nb_temps = s->nb_temps;
nb_globals = s->nb_globals;
- memset(&temps_used, 0, sizeof(temps_used));
for (i = 0; i < nb_temps; ++i) {
s->temps[i].state_ptr = NULL;
}
@@ -634,14 +637,14 @@ void tcg_optimize(TCGContext *s)
for (i = 0; i < nb_oargs + nb_iargs; i++) {
TCGTemp *ts = arg_temp(op->args[i]);
if (ts) {
- init_ts_info(&temps_used, ts);
+ init_ts_info(&ctx, ts);
}
}
} else {
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
for (i = 0; i < nb_oargs + nb_iargs; i++) {
- init_arg_info(&temps_used, op->args[i]);
+ init_arg_info(&ctx, op->args[i]);
}
}
@@ -720,7 +723,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(rotr):
if (arg_is_const(op->args[1])
&& arg_info(op->args[1])->val == 0) {
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
continue;
}
break;
@@ -1085,7 +1088,7 @@ void tcg_optimize(TCGContext *s)
if (partmask == 0) {
tcg_debug_assert(nb_oargs == 1);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
continue;
}
if (affected == 0) {
@@ -1102,7 +1105,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(mulsh):
if (arg_is_const(op->args[2])
&& arg_info(op->args[2])->val == 0) {
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
continue;
}
break;
@@ -1129,7 +1132,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(sub):
CASE_OP_32_64_VEC(xor):
if (args_are_copies(op->args[1], op->args[2])) {
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
continue;
}
break;
@@ -1149,7 +1152,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = arg_info(op->args[1])->val;
tmp = dup_const(TCGOP_VECE(op), tmp);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1157,7 +1160,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_dup2_vec:
assert(TCG_TARGET_REG_BITS == 32);
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0],
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0],
deposit64(arg_info(op->args[1])->val, 32, 32,
arg_info(op->args[2])->val));
break;
@@ -1183,7 +1186,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extrh_i64_i32:
if (arg_is_const(op->args[1])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1194,7 +1197,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
op->args[2]);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1224,7 +1227,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
arg_info(op->args[2])->val);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1235,7 +1238,7 @@ void tcg_optimize(TCGContext *s)
TCGArg v = arg_info(op->args[1])->val;
if (v != 0) {
tmp = do_constant_folding(opc, v, 0);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
} else {
tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
}
@@ -1248,7 +1251,7 @@ void tcg_optimize(TCGContext *s)
tmp = deposit64(arg_info(op->args[1])->val,
op->args[3], op->args[4],
arg_info(op->args[2])->val);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1257,7 +1260,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = extract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1266,7 +1269,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = sextract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1283,7 +1286,7 @@ void tcg_optimize(TCGContext *s)
tmp = (int32_t)(((uint32_t)v1 >> shr) |
((uint32_t)v2 << (32 - shr)));
}
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1292,7 +1295,7 @@ void tcg_optimize(TCGContext *s)
tmp = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[3]);
if (tmp != 2) {
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1302,7 +1305,7 @@ void tcg_optimize(TCGContext *s)
op->args[1], op->args[2]);
if (tmp != 2) {
if (tmp) {
- memset(&temps_used, 0, sizeof(temps_used));
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
op->opc = INDEX_op_br;
op->args[0] = op->args[3];
} else {
@@ -1358,8 +1361,8 @@ void tcg_optimize(TCGContext *s)
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)a);
- tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(a >> 32));
+ tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a);
+ tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32));
break;
}
goto do_default;
@@ -1374,8 +1377,8 @@ void tcg_optimize(TCGContext *s)
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)r);
- tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(r >> 32));
+ tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r);
+ tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32));
break;
}
goto do_default;
@@ -1386,7 +1389,7 @@ void tcg_optimize(TCGContext *s)
if (tmp != 2) {
if (tmp) {
do_brcond_true:
- memset(&temps_used, 0, sizeof(temps_used));
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
op->opc = INDEX_op_br;
op->args[0] = op->args[5];
} else {
@@ -1402,7 +1405,7 @@ void tcg_optimize(TCGContext *s)
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_brcond_high:
- memset(&temps_used, 0, sizeof(temps_used));
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
op->opc = INDEX_op_brcond_i32;
op->args[0] = op->args[1];
op->args[1] = op->args[3];
@@ -1428,7 +1431,7 @@ void tcg_optimize(TCGContext *s)
goto do_default;
}
do_brcond_low:
- memset(&temps_used, 0, sizeof(temps_used));
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
op->opc = INDEX_op_brcond_i32;
op->args[1] = op->args[2];
op->args[2] = op->args[4];
@@ -1463,7 +1466,7 @@ void tcg_optimize(TCGContext *s)
op->args[5]);
if (tmp != 2) {
do_setcond_const:
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
} else if ((op->args[5] == TCG_COND_LT
|| op->args[5] == TCG_COND_GE)
&& arg_is_const(op->args[3])
@@ -1533,7 +1536,7 @@ void tcg_optimize(TCGContext *s)
if (!(tcg_call_flags(op)
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
for (i = 0; i < nb_globals; i++) {
- if (test_bit(i, temps_used.l)) {
+ if (test_bit(i, ctx.temps_used.l)) {
reset_ts(&s->temps[i]);
}
}
@@ -1548,7 +1551,7 @@ void tcg_optimize(TCGContext *s)
block, otherwise we only trash the output args. "z_mask" is
the non-zero bits mask for the first output arg. */
if (def->flags & TCG_OPF_BB_END) {
- memset(&temps_used, 0, sizeof(temps_used));
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
} else {
do_reset_output:
for (i = 0; i < nb_oargs; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 03/48] tcg/optimize: Remove do_default label
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
2021-10-07 19:54 ` [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask" Richard Henderson
2021-10-07 19:54 ` [PATCH v2 02/48] tcg/optimize: Split out OptContext Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-19 15:37 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface Richard Henderson
` (46 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Break the final cleanup clause out of the main switch
statement. When fully folding an opcode to mov/movi,
use "continue" to process the next opcode, else break
to fall into the final cleanup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 190 ++++++++++++++++++++++++-------------------------
1 file changed, 94 insertions(+), 96 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index b76991215e..a37efff4d0 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1146,16 +1146,16 @@ void tcg_optimize(TCGContext *s)
switch (opc) {
CASE_OP_32_64_VEC(mov):
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
- break;
+ continue;
case INDEX_op_dup_vec:
if (arg_is_const(op->args[1])) {
tmp = arg_info(op->args[1])->val;
tmp = dup_const(TCGOP_VECE(op), tmp);
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
case INDEX_op_dup2_vec:
assert(TCG_TARGET_REG_BITS == 32);
@@ -1163,13 +1163,13 @@ void tcg_optimize(TCGContext *s)
tcg_opt_gen_movi(s, &ctx, op, op->args[0],
deposit64(arg_info(op->args[1])->val, 32, 32,
arg_info(op->args[2])->val));
- break;
+ continue;
} else if (args_are_copies(op->args[1], op->args[2])) {
op->opc = INDEX_op_dup_vec;
TCGOP_VECE(op) = MO_32;
nb_iargs = 1;
}
- goto do_default;
+ break;
CASE_OP_32_64(not):
CASE_OP_32_64(neg):
@@ -1187,9 +1187,9 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(bswap16):
CASE_OP_32_64(bswap32):
@@ -1198,9 +1198,9 @@ void tcg_optimize(TCGContext *s)
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
op->args[2]);
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(add):
CASE_OP_32_64(sub):
@@ -1228,9 +1228,9 @@ void tcg_optimize(TCGContext *s)
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
arg_info(op->args[2])->val);
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(clz):
CASE_OP_32_64(ctz):
@@ -1242,9 +1242,9 @@ void tcg_optimize(TCGContext *s)
} else {
tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
}
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(deposit):
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
@@ -1252,27 +1252,27 @@ void tcg_optimize(TCGContext *s)
op->args[3], op->args[4],
arg_info(op->args[2])->val);
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(extract):
if (arg_is_const(op->args[1])) {
tmp = extract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(sextract):
if (arg_is_const(op->args[1])) {
tmp = sextract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(extract2):
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
@@ -1287,40 +1287,40 @@ void tcg_optimize(TCGContext *s)
((uint32_t)v2 << (32 - shr)));
}
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(setcond):
tmp = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[3]);
if (tmp != 2) {
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- break;
+ continue;
}
- goto do_default;
+ break;
CASE_OP_32_64(brcond):
tmp = do_constant_folding_cond(opc, op->args[0],
op->args[1], op->args[2]);
- if (tmp != 2) {
- if (tmp) {
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
- op->opc = INDEX_op_br;
- op->args[0] = op->args[3];
- } else {
- tcg_op_remove(s, op);
- }
+ switch (tmp) {
+ case 0:
+ tcg_op_remove(s, op);
+ continue;
+ case 1:
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
+ op->opc = opc = INDEX_op_br;
+ op->args[0] = op->args[3];
break;
}
- goto do_default;
+ break;
CASE_OP_32_64(movcond):
tmp = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[5]);
if (tmp != 2) {
tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
- break;
+ continue;
}
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
uint64_t tv = arg_info(op->args[3])->val;
@@ -1330,7 +1330,7 @@ void tcg_optimize(TCGContext *s)
if (fv == 1 && tv == 0) {
cond = tcg_invert_cond(cond);
} else if (!(tv == 1 && fv == 0)) {
- goto do_default;
+ break;
}
op->args[3] = cond;
op->opc = opc = (opc == INDEX_op_movcond_i32
@@ -1338,7 +1338,7 @@ void tcg_optimize(TCGContext *s)
: INDEX_op_setcond_i64);
nb_iargs = 2;
}
- goto do_default;
+ break;
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
@@ -1363,9 +1363,9 @@ void tcg_optimize(TCGContext *s)
rh = op->args[1];
tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a);
tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32));
- break;
+ continue;
}
- goto do_default;
+ break;
case INDEX_op_mulu2_i32:
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
@@ -1379,39 +1379,40 @@ void tcg_optimize(TCGContext *s)
rh = op->args[1];
tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r);
tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32));
- break;
+ continue;
}
- goto do_default;
+ break;
case INDEX_op_brcond2_i32:
tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
op->args[4]);
- if (tmp != 2) {
- if (tmp) {
- do_brcond_true:
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
- op->opc = INDEX_op_br;
- op->args[0] = op->args[5];
- } else {
+ if (tmp == 0) {
do_brcond_false:
- tcg_op_remove(s, op);
- }
- } else if ((op->args[4] == TCG_COND_LT
- || op->args[4] == TCG_COND_GE)
- && arg_is_const(op->args[2])
- && arg_info(op->args[2])->val == 0
- && arg_is_const(op->args[3])
- && arg_info(op->args[3])->val == 0) {
+ tcg_op_remove(s, op);
+ continue;
+ }
+ if (tmp == 1) {
+ do_brcond_true:
+ op->opc = opc = INDEX_op_br;
+ op->args[0] = op->args[5];
+ break;
+ }
+ if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE)
+ && arg_is_const(op->args[2])
+ && arg_info(op->args[2])->val == 0
+ && arg_is_const(op->args[3])
+ && arg_info(op->args[3])->val == 0) {
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_brcond_high:
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
- op->opc = INDEX_op_brcond_i32;
+ op->opc = opc = INDEX_op_brcond_i32;
op->args[0] = op->args[1];
op->args[1] = op->args[3];
op->args[2] = op->args[4];
op->args[3] = op->args[5];
- } else if (op->args[4] == TCG_COND_EQ) {
+ break;
+ }
+ if (op->args[4] == TCG_COND_EQ) {
/* Simplify EQ comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
@@ -1428,7 +1429,7 @@ void tcg_optimize(TCGContext *s)
if (tmp == 0) {
goto do_brcond_false;
} else if (tmp != 1) {
- goto do_default;
+ break;
}
do_brcond_low:
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
@@ -1436,7 +1437,9 @@ void tcg_optimize(TCGContext *s)
op->args[1] = op->args[2];
op->args[2] = op->args[4];
op->args[3] = op->args[5];
- } else if (op->args[4] == TCG_COND_NE) {
+ break;
+ }
+ if (op->args[4] == TCG_COND_NE) {
/* Simplify NE comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
@@ -1455,9 +1458,6 @@ void tcg_optimize(TCGContext *s)
} else if (tmp == 1) {
goto do_brcond_true;
}
- goto do_default;
- } else {
- goto do_default;
}
break;
@@ -1467,12 +1467,13 @@ void tcg_optimize(TCGContext *s)
if (tmp != 2) {
do_setcond_const:
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
- } else if ((op->args[5] == TCG_COND_LT
- || op->args[5] == TCG_COND_GE)
- && arg_is_const(op->args[3])
- && arg_info(op->args[3])->val == 0
- && arg_is_const(op->args[4])
- && arg_info(op->args[4])->val == 0) {
+ continue;
+ }
+ if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
+ && arg_is_const(op->args[3])
+ && arg_info(op->args[3])->val == 0
+ && arg_is_const(op->args[4])
+ && arg_info(op->args[4])->val == 0) {
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_setcond_high:
@@ -1482,7 +1483,9 @@ void tcg_optimize(TCGContext *s)
op->args[1] = op->args[2];
op->args[2] = op->args[4];
op->args[3] = op->args[5];
- } else if (op->args[5] == TCG_COND_EQ) {
+ break;
+ }
+ if (op->args[5] == TCG_COND_EQ) {
/* Simplify EQ comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
@@ -1499,7 +1502,7 @@ void tcg_optimize(TCGContext *s)
if (tmp == 0) {
goto do_setcond_high;
} else if (tmp != 1) {
- goto do_default;
+ break;
}
do_setcond_low:
reset_temp(op->args[0]);
@@ -1507,7 +1510,9 @@ void tcg_optimize(TCGContext *s)
op->opc = INDEX_op_setcond_i32;
op->args[2] = op->args[3];
op->args[3] = op->args[5];
- } else if (op->args[5] == TCG_COND_NE) {
+ break;
+ }
+ if (op->args[5] == TCG_COND_NE) {
/* Simplify NE comparisons where one of the pairs
can be simplified. */
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
@@ -1526,14 +1531,21 @@ void tcg_optimize(TCGContext *s)
} else if (tmp == 1) {
goto do_setcond_const;
}
- goto do_default;
- } else {
- goto do_default;
}
break;
- case INDEX_op_call:
- if (!(tcg_call_flags(op)
+ default:
+ break;
+ }
+
+ /* Some of the folding above can change opc. */
+ opc = op->opc;
+ def = &tcg_op_defs[opc];
+ if (def->flags & TCG_OPF_BB_END) {
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
+ } else {
+ if (opc == INDEX_op_call &&
+ !(tcg_call_flags(op)
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
for (i = 0; i < nb_globals; i++) {
if (test_bit(i, ctx.temps_used.l)) {
@@ -1541,29 +1553,15 @@ void tcg_optimize(TCGContext *s)
}
}
}
- goto do_reset_output;
- default:
- do_default:
- /* Default case: we know nothing about operation (or were unable
- to compute the operation result) so no propagation is done.
- We trash everything if the operation is the end of a basic
- block, otherwise we only trash the output args. "z_mask" is
- the non-zero bits mask for the first output arg. */
- if (def->flags & TCG_OPF_BB_END) {
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
- } else {
- do_reset_output:
- for (i = 0; i < nb_oargs; i++) {
- reset_temp(op->args[i]);
- /* Save the corresponding known-zero bits mask for the
- first output argument (only one supported so far). */
- if (i == 0) {
- arg_info(op->args[i])->z_mask = z_mask;
- }
+ for (i = 0; i < nb_oargs; i++) {
+ reset_temp(op->args[i]);
+ /* Save the corresponding known-zero bits mask for the
+ first output argument (only one supported so far). */
+ if (i == 0) {
+ arg_info(op->args[i])->z_mask = z_mask;
}
}
- break;
}
/* Eliminate duplicate and redundant fence instructions. */
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (2 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 03/48] tcg/optimize: Remove do_default label Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-19 15:38 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext Richard Henderson
` (45 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Adjust the interface to take the OptContext parameter instead
of TCGContext or both.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 67 +++++++++++++++++++++++++-------------------------
1 file changed, 34 insertions(+), 33 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index a37efff4d0..627a5b39f6 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -45,6 +45,7 @@ typedef struct TempOptInfo {
} TempOptInfo;
typedef struct OptContext {
+ TCGContext *tcg;
TCGTempSet temps_used;
} OptContext;
@@ -183,7 +184,7 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2)
return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
}
-static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
+static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
{
TCGTemp *dst_ts = arg_temp(dst);
TCGTemp *src_ts = arg_temp(src);
@@ -194,7 +195,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
TCGOpcode new_op;
if (ts_are_copies(dst_ts, src_ts)) {
- tcg_op_remove(s, op);
+ tcg_op_remove(ctx->tcg, op);
return;
}
@@ -233,8 +234,8 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
}
}
-static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx,
- TCGOp *op, TCGArg dst, uint64_t val)
+static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
+ TCGArg dst, uint64_t val)
{
const TCGOpDef *def = &tcg_op_defs[op->opc];
TCGType type;
@@ -251,7 +252,7 @@ static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx,
/* Convert movi to mov with constant temp. */
tv = tcg_constant_internal(type, val);
init_ts_info(ctx, tv);
- tcg_opt_gen_mov(s, op, dst, temp_arg(tv));
+ tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
}
static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
@@ -609,7 +610,7 @@ void tcg_optimize(TCGContext *s)
{
int nb_temps, nb_globals, i;
TCGOp *op, *op_next, *prev_mb = NULL;
- OptContext ctx = {};
+ OptContext ctx = { .tcg = s };
/* Array VALS has an element for each temp.
If this temp holds a constant then its value is kept in VALS' element.
@@ -723,7 +724,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(rotr):
if (arg_is_const(op->args[1])
&& arg_info(op->args[1])->val == 0) {
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
continue;
}
break;
@@ -838,7 +839,7 @@ void tcg_optimize(TCGContext *s)
if (!arg_is_const(op->args[1])
&& arg_is_const(op->args[2])
&& arg_info(op->args[2])->val == 0) {
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
continue;
}
break;
@@ -848,7 +849,7 @@ void tcg_optimize(TCGContext *s)
if (!arg_is_const(op->args[1])
&& arg_is_const(op->args[2])
&& arg_info(op->args[2])->val == -1) {
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
continue;
}
break;
@@ -1088,12 +1089,12 @@ void tcg_optimize(TCGContext *s)
if (partmask == 0) {
tcg_debug_assert(nb_oargs == 1);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
continue;
}
if (affected == 0) {
tcg_debug_assert(nb_oargs == 1);
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
continue;
}
@@ -1105,7 +1106,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(mulsh):
if (arg_is_const(op->args[2])
&& arg_info(op->args[2])->val == 0) {
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
continue;
}
break;
@@ -1118,7 +1119,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(or):
CASE_OP_32_64_VEC(and):
if (args_are_copies(op->args[1], op->args[2])) {
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
continue;
}
break;
@@ -1132,7 +1133,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(sub):
CASE_OP_32_64_VEC(xor):
if (args_are_copies(op->args[1], op->args[2])) {
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
continue;
}
break;
@@ -1145,14 +1146,14 @@ void tcg_optimize(TCGContext *s)
allocator where needed and possible. Also detect copies. */
switch (opc) {
CASE_OP_32_64_VEC(mov):
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
continue;
case INDEX_op_dup_vec:
if (arg_is_const(op->args[1])) {
tmp = arg_info(op->args[1])->val;
tmp = dup_const(TCGOP_VECE(op), tmp);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1160,7 +1161,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_dup2_vec:
assert(TCG_TARGET_REG_BITS == 32);
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- tcg_opt_gen_movi(s, &ctx, op, op->args[0],
+ tcg_opt_gen_movi(&ctx, op, op->args[0],
deposit64(arg_info(op->args[1])->val, 32, 32,
arg_info(op->args[2])->val));
continue;
@@ -1186,7 +1187,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extrh_i64_i32:
if (arg_is_const(op->args[1])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1197,7 +1198,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
op->args[2]);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1227,7 +1228,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
arg_info(op->args[2])->val);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1238,9 +1239,9 @@ void tcg_optimize(TCGContext *s)
TCGArg v = arg_info(op->args[1])->val;
if (v != 0) {
tmp = do_constant_folding(opc, v, 0);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
} else {
- tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]);
}
continue;
}
@@ -1251,7 +1252,7 @@ void tcg_optimize(TCGContext *s)
tmp = deposit64(arg_info(op->args[1])->val,
op->args[3], op->args[4],
arg_info(op->args[2])->val);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1260,7 +1261,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = extract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1269,7 +1270,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = sextract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1286,7 +1287,7 @@ void tcg_optimize(TCGContext *s)
tmp = (int32_t)(((uint32_t)v1 >> shr) |
((uint32_t)v2 << (32 - shr)));
}
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1295,7 +1296,7 @@ void tcg_optimize(TCGContext *s)
tmp = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[3]);
if (tmp != 2) {
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
break;
@@ -1319,7 +1320,7 @@ void tcg_optimize(TCGContext *s)
tmp = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[5]);
if (tmp != 2) {
- tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4-tmp]);
continue;
}
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
@@ -1361,8 +1362,8 @@ void tcg_optimize(TCGContext *s)
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a);
- tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32));
+ tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a);
+ tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32));
continue;
}
break;
@@ -1377,8 +1378,8 @@ void tcg_optimize(TCGContext *s)
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r);
- tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32));
+ tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r);
+ tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32));
continue;
}
break;
@@ -1466,7 +1467,7 @@ void tcg_optimize(TCGContext *s)
op->args[5]);
if (tmp != 2) {
do_setcond_const:
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
continue;
}
if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (3 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-19 15:44 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 06/48] tcg/optimize: Split out init_arguments Richard Henderson
` (44 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
This will expose the variable to subroutines that
will be broken out of tcg_optimize.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 627a5b39f6..b875d76354 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -46,6 +46,7 @@ typedef struct TempOptInfo {
typedef struct OptContext {
TCGContext *tcg;
+ TCGOp *prev_mb;
TCGTempSet temps_used;
} OptContext;
@@ -609,7 +610,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
void tcg_optimize(TCGContext *s)
{
int nb_temps, nb_globals, i;
- TCGOp *op, *op_next, *prev_mb = NULL;
+ TCGOp *op, *op_next;
OptContext ctx = { .tcg = s };
/* Array VALS has an element for each temp.
@@ -1566,7 +1567,7 @@ void tcg_optimize(TCGContext *s)
}
/* Eliminate duplicate and redundant fence instructions. */
- if (prev_mb) {
+ if (ctx.prev_mb) {
switch (opc) {
case INDEX_op_mb:
/* Merge two barriers of the same type into one,
@@ -1580,7 +1581,7 @@ void tcg_optimize(TCGContext *s)
* barrier. This is stricter than specified but for
* the purposes of TCG is better than not optimizing.
*/
- prev_mb->args[0] |= op->args[0];
+ ctx.prev_mb->args[0] |= op->args[0];
tcg_op_remove(s, op);
break;
@@ -1597,11 +1598,11 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_qemu_st_i64:
case INDEX_op_call:
/* Opcodes that touch guest memory stop the optimization. */
- prev_mb = NULL;
+ ctx.prev_mb = NULL;
break;
}
} else if (opc == INDEX_op_mb) {
- prev_mb = op;
+ ctx.prev_mb = op;
}
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 06/48] tcg/optimize: Split out init_arguments
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (4 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-19 16:13 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 07/48] tcg/optimize: Split out copy_propagate Richard Henderson
` (43 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
There was no real reason for calls to have separate code here.
Unify init for calls vs non-calls using the call path, which
handles TCG_CALL_DUMMY_ARG.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 25 +++++++++++--------------
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index b875d76354..019c5aaf81 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -128,11 +128,6 @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts)
}
}
-static void init_arg_info(OptContext *ctx, TCGArg arg)
-{
- init_ts_info(ctx, arg_temp(arg));
-}
-
static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
{
TCGTemp *i, *g, *l;
@@ -606,6 +601,16 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
return false;
}
+static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args)
+{
+ for (int i = 0; i < nb_args; i++) {
+ TCGTemp *ts = arg_temp(op->args[i]);
+ if (ts) {
+ init_ts_info(ctx, ts);
+ }
+ }
+}
+
/* Propagate constants and copies, fold constant expressions. */
void tcg_optimize(TCGContext *s)
{
@@ -636,19 +641,11 @@ void tcg_optimize(TCGContext *s)
if (opc == INDEX_op_call) {
nb_oargs = TCGOP_CALLO(op);
nb_iargs = TCGOP_CALLI(op);
- for (i = 0; i < nb_oargs + nb_iargs; i++) {
- TCGTemp *ts = arg_temp(op->args[i]);
- if (ts) {
- init_ts_info(&ctx, ts);
- }
- }
} else {
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
- for (i = 0; i < nb_oargs + nb_iargs; i++) {
- init_arg_info(&ctx, op->args[i]);
- }
}
+ init_arguments(&ctx, op, nb_oargs + nb_iargs);
/* Do copy propagation */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 07/48] tcg/optimize: Split out copy_propagate
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (5 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 06/48] tcg/optimize: Split out init_arguments Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 16:01 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 08/48] tcg/optimize: Split out fold_call Richard Henderson
` (42 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Continue splitting tcg_optimize.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 019c5aaf81..fad6f5de1f 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -611,6 +611,19 @@ static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args)
}
}
+static void copy_propagate(OptContext *ctx, TCGOp *op,
+ int nb_oargs, int nb_iargs)
+{
+ TCGContext *s = ctx->tcg;
+
+ for (int i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
+ TCGTemp *ts = arg_temp(op->args[i]);
+ if (ts && ts_is_copy(ts)) {
+ op->args[i] = temp_arg(find_better_copy(s, ts));
+ }
+ }
+}
+
/* Propagate constants and copies, fold constant expressions. */
void tcg_optimize(TCGContext *s)
{
@@ -646,14 +659,7 @@ void tcg_optimize(TCGContext *s)
nb_iargs = def->nb_iargs;
}
init_arguments(&ctx, op, nb_oargs + nb_iargs);
-
- /* Do copy propagation */
- for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
- TCGTemp *ts = arg_temp(op->args[i]);
- if (ts && ts_is_copy(ts)) {
- op->args[i] = temp_arg(find_better_copy(s, ts));
- }
- }
+ copy_propagate(&ctx, op, nb_oargs, nb_iargs);
/* For commutative operations make constant second argument */
switch (opc) {
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 08/48] tcg/optimize: Split out fold_call
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (6 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 07/48] tcg/optimize: Split out copy_propagate Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 16:05 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals Richard Henderson
` (41 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Calls are special in that they have a variable number
of arguments, and need to be able to clobber globals.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 63 ++++++++++++++++++++++++++++++++------------------
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index fad6f5de1f..74b9aa025a 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -624,10 +624,42 @@ static void copy_propagate(OptContext *ctx, TCGOp *op,
}
}
+static bool fold_call(OptContext *ctx, TCGOp *op)
+{
+ TCGContext *s = ctx->tcg;
+ int nb_oargs = TCGOP_CALLO(op);
+ int nb_iargs = TCGOP_CALLI(op);
+ int flags, i;
+
+ init_arguments(ctx, op, nb_oargs + nb_iargs);
+ copy_propagate(ctx, op, nb_oargs, nb_iargs);
+
+ /* If the function reads or writes globals, reset temp data. */
+ flags = tcg_call_flags(op);
+ if (!(flags & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
+ int nb_globals = s->nb_globals;
+
+ for (i = 0; i < nb_globals; i++) {
+ if (test_bit(i, ctx->temps_used.l)) {
+ reset_ts(&ctx->tcg->temps[i]);
+ }
+ }
+ }
+
+ /* Reset temp data for outputs. */
+ for (i = 0; i < nb_oargs; i++) {
+ reset_temp(op->args[i]);
+ }
+
+ /* Stop optimizing MB across calls. */
+ ctx->prev_mb = NULL;
+ return true;
+}
+
/* Propagate constants and copies, fold constant expressions. */
void tcg_optimize(TCGContext *s)
{
- int nb_temps, nb_globals, i;
+ int nb_temps, i;
TCGOp *op, *op_next;
OptContext ctx = { .tcg = s };
@@ -637,8 +669,6 @@ void tcg_optimize(TCGContext *s)
available through the doubly linked circular list. */
nb_temps = s->nb_temps;
- nb_globals = s->nb_globals;
-
for (i = 0; i < nb_temps; ++i) {
s->temps[i].state_ptr = NULL;
}
@@ -647,17 +677,17 @@ void tcg_optimize(TCGContext *s)
uint64_t z_mask, partmask, affected, tmp;
int nb_oargs, nb_iargs;
TCGOpcode opc = op->opc;
- const TCGOpDef *def = &tcg_op_defs[opc];
+ const TCGOpDef *def;
- /* Count the arguments, and initialize the temps that are
- going to be used */
+ /* Calls are special. */
if (opc == INDEX_op_call) {
- nb_oargs = TCGOP_CALLO(op);
- nb_iargs = TCGOP_CALLI(op);
- } else {
- nb_oargs = def->nb_oargs;
- nb_iargs = def->nb_iargs;
+ fold_call(&ctx, op);
+ continue;
}
+
+ def = &tcg_op_defs[opc];
+ nb_oargs = def->nb_oargs;
+ nb_iargs = def->nb_iargs;
init_arguments(&ctx, op, nb_oargs + nb_iargs);
copy_propagate(&ctx, op, nb_oargs, nb_iargs);
@@ -1549,16 +1579,6 @@ void tcg_optimize(TCGContext *s)
if (def->flags & TCG_OPF_BB_END) {
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
} else {
- if (opc == INDEX_op_call &&
- !(tcg_call_flags(op)
- & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
- for (i = 0; i < nb_globals; i++) {
- if (test_bit(i, ctx.temps_used.l)) {
- reset_ts(&s->temps[i]);
- }
- }
- }
-
for (i = 0; i < nb_oargs; i++) {
reset_temp(op->args[i]);
/* Save the corresponding known-zero bits mask for the
@@ -1599,7 +1619,6 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st8_i32:
case INDEX_op_qemu_st_i64:
- case INDEX_op_call:
/* Opcodes that touch guest memory stop the optimization. */
ctx.prev_mb = NULL;
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (7 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 08/48] tcg/optimize: Split out fold_call Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 16:17 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 10/48] tcg/optimize: Change fail return for do_constant_folding_cond* Richard Henderson
` (40 subsequent siblings)
49 siblings, 2 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Rather than try to keep these up-to-date across folding,
re-read nb_oargs at the end, after re-reading the opcode.
A couple of asserts need dropping, but that will take care
of itself as we split the function further.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 74b9aa025a..77cdffaaef 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -675,7 +675,6 @@ void tcg_optimize(TCGContext *s)
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
uint64_t z_mask, partmask, affected, tmp;
- int nb_oargs, nb_iargs;
TCGOpcode opc = op->opc;
const TCGOpDef *def;
@@ -686,10 +685,8 @@ void tcg_optimize(TCGContext *s)
}
def = &tcg_op_defs[opc];
- nb_oargs = def->nb_oargs;
- nb_iargs = def->nb_iargs;
- init_arguments(&ctx, op, nb_oargs + nb_iargs);
- copy_propagate(&ctx, op, nb_oargs, nb_iargs);
+ init_arguments(&ctx, op, def->nb_oargs + def->nb_iargs);
+ copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs);
/* For commutative operations make constant second argument */
switch (opc) {
@@ -1063,7 +1060,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(qemu_ld):
{
- MemOpIdx oi = op->args[nb_oargs + nb_iargs];
+ MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs];
MemOp mop = get_memop(oi);
if (!(mop & MO_SIGN)) {
z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
@@ -1122,12 +1119,10 @@ void tcg_optimize(TCGContext *s)
}
if (partmask == 0) {
- tcg_debug_assert(nb_oargs == 1);
tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
continue;
}
if (affected == 0) {
- tcg_debug_assert(nb_oargs == 1);
tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
continue;
}
@@ -1202,7 +1197,6 @@ void tcg_optimize(TCGContext *s)
} else if (args_are_copies(op->args[1], op->args[2])) {
op->opc = INDEX_op_dup_vec;
TCGOP_VECE(op) = MO_32;
- nb_iargs = 1;
}
break;
@@ -1371,7 +1365,6 @@ void tcg_optimize(TCGContext *s)
op->opc = opc = (opc == INDEX_op_movcond_i32
? INDEX_op_setcond_i32
: INDEX_op_setcond_i64);
- nb_iargs = 2;
}
break;
@@ -1579,6 +1572,7 @@ void tcg_optimize(TCGContext *s)
if (def->flags & TCG_OPF_BB_END) {
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
} else {
+ int nb_oargs = def->nb_oargs;
for (i = 0; i < nb_oargs; i++) {
reset_temp(op->args[i]);
/* Save the corresponding known-zero bits mask for the
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 10/48] tcg/optimize: Change fail return for do_constant_folding_cond*
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (8 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi} Richard Henderson
` (39 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Return -1 instead of 2 for failure.
This us to use comparisons against 0 for all cases.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 145 +++++++++++++++++++++++++------------------------
1 file changed, 74 insertions(+), 71 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 77cdffaaef..19c01687b4 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -502,10 +502,12 @@ static bool do_constant_folding_cond_eq(TCGCond c)
}
}
-/* Return 2 if the condition can't be simplified, and the result
- of the condition (0 or 1) if it can */
-static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
- TCGArg y, TCGCond c)
+/*
+ * Return -1 if the condition can't be simplified,
+ * and the result of the condition (0 or 1) if it can.
+ */
+static int do_constant_folding_cond(TCGOpcode op, TCGArg x,
+ TCGArg y, TCGCond c)
{
uint64_t xv = arg_info(x)->val;
uint64_t yv = arg_info(y)->val;
@@ -527,15 +529,17 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
case TCG_COND_GEU:
return 1;
default:
- return 2;
+ return -1;
}
}
- return 2;
+ return -1;
}
-/* Return 2 if the condition can't be simplified, and the result
- of the condition (0 or 1) if it can */
-static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
+/*
+ * Return -1 if the condition can't be simplified,
+ * and the result of the condition (0 or 1) if it can.
+ */
+static int do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
{
TCGArg al = p1[0], ah = p1[1];
TCGArg bl = p2[0], bh = p2[1];
@@ -565,7 +569,7 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
if (args_are_copies(al, bl) && args_are_copies(ah, bh)) {
return do_constant_folding_cond_eq(c);
}
- return 2;
+ return -1;
}
static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
@@ -1321,22 +1325,21 @@ void tcg_optimize(TCGContext *s)
break;
CASE_OP_32_64(setcond):
- tmp = do_constant_folding_cond(opc, op->args[1],
- op->args[2], op->args[3]);
- if (tmp != 2) {
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
+ i = do_constant_folding_cond(opc, op->args[1],
+ op->args[2], op->args[3]);
+ if (i >= 0) {
+ tcg_opt_gen_movi(&ctx, op, op->args[0], i);
continue;
}
break;
CASE_OP_32_64(brcond):
- tmp = do_constant_folding_cond(opc, op->args[0],
- op->args[1], op->args[2]);
- switch (tmp) {
- case 0:
+ i = do_constant_folding_cond(opc, op->args[0],
+ op->args[1], op->args[2]);
+ if (i == 0) {
tcg_op_remove(s, op);
continue;
- case 1:
+ } else if (i > 0) {
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
op->opc = opc = INDEX_op_br;
op->args[0] = op->args[3];
@@ -1345,10 +1348,10 @@ void tcg_optimize(TCGContext *s)
break;
CASE_OP_32_64(movcond):
- tmp = do_constant_folding_cond(opc, op->args[1],
- op->args[2], op->args[5]);
- if (tmp != 2) {
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4-tmp]);
+ i = do_constant_folding_cond(opc, op->args[1],
+ op->args[2], op->args[5]);
+ if (i >= 0) {
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4 - i]);
continue;
}
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
@@ -1412,14 +1415,14 @@ void tcg_optimize(TCGContext *s)
break;
case INDEX_op_brcond2_i32:
- tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
- op->args[4]);
- if (tmp == 0) {
+ i = do_constant_folding_cond2(&op->args[0], &op->args[2],
+ op->args[4]);
+ if (i == 0) {
do_brcond_false:
tcg_op_remove(s, op);
continue;
}
- if (tmp == 1) {
+ if (i > 0) {
do_brcond_true:
op->opc = opc = INDEX_op_br;
op->args[0] = op->args[5];
@@ -1443,20 +1446,20 @@ void tcg_optimize(TCGContext *s)
if (op->args[4] == TCG_COND_EQ) {
/* Simplify EQ comparisons where one of the pairs
can be simplified. */
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[0], op->args[2],
- TCG_COND_EQ);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
+ op->args[0], op->args[2],
+ TCG_COND_EQ);
+ if (i == 0) {
goto do_brcond_false;
- } else if (tmp == 1) {
+ } else if (i > 0) {
goto do_brcond_high;
}
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[1], op->args[3],
- TCG_COND_EQ);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
+ op->args[1], op->args[3],
+ TCG_COND_EQ);
+ if (i == 0) {
goto do_brcond_false;
- } else if (tmp != 1) {
+ } else if (i < 0) {
break;
}
do_brcond_low:
@@ -1470,31 +1473,31 @@ void tcg_optimize(TCGContext *s)
if (op->args[4] == TCG_COND_NE) {
/* Simplify NE comparisons where one of the pairs
can be simplified. */
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[0], op->args[2],
- TCG_COND_NE);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
+ op->args[0], op->args[2],
+ TCG_COND_NE);
+ if (i == 0) {
goto do_brcond_high;
- } else if (tmp == 1) {
+ } else if (i > 0) {
goto do_brcond_true;
}
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[1], op->args[3],
- TCG_COND_NE);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
+ op->args[1], op->args[3],
+ TCG_COND_NE);
+ if (i == 0) {
goto do_brcond_low;
- } else if (tmp == 1) {
+ } else if (i > 0) {
goto do_brcond_true;
}
}
break;
case INDEX_op_setcond2_i32:
- tmp = do_constant_folding_cond2(&op->args[1], &op->args[3],
- op->args[5]);
- if (tmp != 2) {
+ i = do_constant_folding_cond2(&op->args[1], &op->args[3],
+ op->args[5]);
+ if (i >= 0) {
do_setcond_const:
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
+ tcg_opt_gen_movi(&ctx, op, op->args[0], i);
continue;
}
if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
@@ -1516,20 +1519,20 @@ void tcg_optimize(TCGContext *s)
if (op->args[5] == TCG_COND_EQ) {
/* Simplify EQ comparisons where one of the pairs
can be simplified. */
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[1], op->args[3],
- TCG_COND_EQ);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
+ op->args[1], op->args[3],
+ TCG_COND_EQ);
+ if (i == 0) {
goto do_setcond_const;
- } else if (tmp == 1) {
+ } else if (i > 0) {
goto do_setcond_high;
}
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[2], op->args[4],
- TCG_COND_EQ);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
+ op->args[2], op->args[4],
+ TCG_COND_EQ);
+ if (i == 0) {
goto do_setcond_high;
- } else if (tmp != 1) {
+ } else if (i < 0) {
break;
}
do_setcond_low:
@@ -1543,20 +1546,20 @@ void tcg_optimize(TCGContext *s)
if (op->args[5] == TCG_COND_NE) {
/* Simplify NE comparisons where one of the pairs
can be simplified. */
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[1], op->args[3],
- TCG_COND_NE);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
+ op->args[1], op->args[3],
+ TCG_COND_NE);
+ if (i == 0) {
goto do_setcond_high;
- } else if (tmp == 1) {
+ } else if (i > 0) {
goto do_setcond_const;
}
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[2], op->args[4],
- TCG_COND_NE);
- if (tmp == 0) {
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
+ op->args[2], op->args[4],
+ TCG_COND_NE);
+ if (i == 0) {
goto do_setcond_low;
- } else if (tmp == 1) {
+ } else if (i > 0) {
goto do_setcond_const;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi}
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (9 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 10/48] tcg/optimize: Change fail return for do_constant_folding_cond* Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 12/48] tcg/optimize: Split out finish_folding Richard Henderson
` (38 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This will allow callers to tail call to these functions
and return true indicating processing complete.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 19c01687b4..066e635f73 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -180,7 +180,7 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2)
return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
}
-static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
+static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
{
TCGTemp *dst_ts = arg_temp(dst);
TCGTemp *src_ts = arg_temp(src);
@@ -192,7 +192,7 @@ static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
if (ts_are_copies(dst_ts, src_ts)) {
tcg_op_remove(ctx->tcg, op);
- return;
+ return true;
}
reset_ts(dst_ts);
@@ -228,9 +228,10 @@ static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
di->is_const = si->is_const;
di->val = si->val;
}
+ return true;
}
-static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
+static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
TCGArg dst, uint64_t val)
{
const TCGOpDef *def = &tcg_op_defs[op->opc];
@@ -248,7 +249,7 @@ static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
/* Convert movi to mov with constant temp. */
tv = tcg_constant_internal(type, val);
init_ts_info(ctx, tv);
- tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
+ return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
}
static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 12/48] tcg/optimize: Split out finish_folding
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (10 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi} Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 13/48] tcg/optimize: Use a boolean to avoid a mass of continues Richard Henderson
` (37 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Copy z_mask into OptContext, for writeback to the
first output within the new function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 49 +++++++++++++++++++++++++++++++++----------------
1 file changed, 33 insertions(+), 16 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 066e635f73..368457f4a2 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -48,6 +48,9 @@ typedef struct OptContext {
TCGContext *tcg;
TCGOp *prev_mb;
TCGTempSet temps_used;
+
+ /* In flight values from optimization. */
+ uint64_t z_mask;
} OptContext;
static inline TempOptInfo *ts_info(TCGTemp *ts)
@@ -629,6 +632,34 @@ static void copy_propagate(OptContext *ctx, TCGOp *op,
}
}
+static void finish_folding(OptContext *ctx, TCGOp *op)
+{
+ const TCGOpDef *def = &tcg_op_defs[op->opc];
+ int i, nb_oargs;
+
+ /*
+ * For an opcode that ends a BB, reset all temp data.
+ * We do no cross-BB optimization.
+ */
+ if (def->flags & TCG_OPF_BB_END) {
+ memset(&ctx->temps_used, 0, sizeof(ctx->temps_used));
+ ctx->prev_mb = NULL;
+ return;
+ }
+
+ nb_oargs = def->nb_oargs;
+ for (i = 0; i < nb_oargs; i++) {
+ reset_temp(op->args[i]);
+ /*
+ * Save the corresponding known-zero bits mask for the
+ * first output argument (only one supported so far).
+ */
+ if (i == 0) {
+ arg_info(op->args[i])->z_mask = ctx->z_mask;
+ }
+ }
+}
+
static bool fold_call(OptContext *ctx, TCGOp *op)
{
TCGContext *s = ctx->tcg;
@@ -1122,6 +1153,7 @@ void tcg_optimize(TCGContext *s)
partmask &= 0xffffffffu;
affected &= 0xffffffffu;
}
+ ctx.z_mask = z_mask;
if (partmask == 0) {
tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
@@ -1570,22 +1602,7 @@ void tcg_optimize(TCGContext *s)
break;
}
- /* Some of the folding above can change opc. */
- opc = op->opc;
- def = &tcg_op_defs[opc];
- if (def->flags & TCG_OPF_BB_END) {
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
- } else {
- int nb_oargs = def->nb_oargs;
- for (i = 0; i < nb_oargs; i++) {
- reset_temp(op->args[i]);
- /* Save the corresponding known-zero bits mask for the
- first output argument (only one supported so far). */
- if (i == 0) {
- arg_info(op->args[i])->z_mask = z_mask;
- }
- }
- }
+ finish_folding(&ctx, op);
/* Eliminate duplicate and redundant fence instructions. */
if (ctx.prev_mb) {
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 13/48] tcg/optimize: Use a boolean to avoid a mass of continues
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (11 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 12/48] tcg/optimize: Split out finish_folding Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st} Richard Henderson
` (36 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 368457f4a2..699476e2f1 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -713,6 +713,7 @@ void tcg_optimize(TCGContext *s)
uint64_t z_mask, partmask, affected, tmp;
TCGOpcode opc = op->opc;
const TCGOpDef *def;
+ bool done = false;
/* Calls are special. */
if (opc == INDEX_op_call) {
@@ -1212,8 +1213,8 @@ void tcg_optimize(TCGContext *s)
allocator where needed and possible. Also detect copies. */
switch (opc) {
CASE_OP_32_64_VEC(mov):
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
- continue;
+ done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
+ break;
case INDEX_op_dup_vec:
if (arg_is_const(op->args[1])) {
@@ -1602,7 +1603,9 @@ void tcg_optimize(TCGContext *s)
break;
}
- finish_folding(&ctx, op);
+ if (!done) {
+ finish_folding(&ctx, op);
+ }
/* Eliminate duplicate and redundant fence instructions. */
if (ctx.prev_mb) {
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (12 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 13/48] tcg/optimize: Use a boolean to avoid a mass of continues Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 15/48] tcg/optimize: Split out fold_const{1,2} Richard Henderson
` (35 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
This puts the separate mb optimization into the same framework
as the others. While fold_qemu_{ld,st} are currently identical,
that won't last as more code gets moved.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 89 +++++++++++++++++++++++++++++---------------------
1 file changed, 51 insertions(+), 38 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 699476e2f1..159a5a9ee5 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -692,6 +692,44 @@ static bool fold_call(OptContext *ctx, TCGOp *op)
return true;
}
+static bool fold_mb(OptContext *ctx, TCGOp *op)
+{
+ /* Eliminate duplicate and redundant fence instructions. */
+ if (ctx->prev_mb) {
+ /*
+ * Merge two barriers of the same type into one,
+ * or a weaker barrier into a stronger one,
+ * or two weaker barriers into a stronger one.
+ * mb X; mb Y => mb X|Y
+ * mb; strl => mb; st
+ * ldaq; mb => ld; mb
+ * ldaq; strl => ld; mb; st
+ * Other combinations are also merged into a strong
+ * barrier. This is stricter than specified but for
+ * the purposes of TCG is better than not optimizing.
+ */
+ ctx->prev_mb->args[0] |= op->args[0];
+ tcg_op_remove(ctx->tcg, op);
+ } else {
+ ctx->prev_mb = op;
+ }
+ return true;
+}
+
+static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
+{
+ /* Opcodes that touch guest memory stop the mb optimization. */
+ ctx->prev_mb = NULL;
+ return false;
+}
+
+static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
+{
+ /* Opcodes that touch guest memory stop the mb optimization. */
+ ctx->prev_mb = NULL;
+ return false;
+}
+
/* Propagate constants and copies, fold constant expressions. */
void tcg_optimize(TCGContext *s)
{
@@ -1599,6 +1637,19 @@ void tcg_optimize(TCGContext *s)
}
break;
+ case INDEX_op_mb:
+ done = fold_mb(&ctx, op);
+ break;
+ case INDEX_op_qemu_ld_i32:
+ case INDEX_op_qemu_ld_i64:
+ done = fold_qemu_ld(&ctx, op);
+ break;
+ case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st8_i32:
+ case INDEX_op_qemu_st_i64:
+ done = fold_qemu_st(&ctx, op);
+ break;
+
default:
break;
}
@@ -1606,43 +1657,5 @@ void tcg_optimize(TCGContext *s)
if (!done) {
finish_folding(&ctx, op);
}
-
- /* Eliminate duplicate and redundant fence instructions. */
- if (ctx.prev_mb) {
- switch (opc) {
- case INDEX_op_mb:
- /* Merge two barriers of the same type into one,
- * or a weaker barrier into a stronger one,
- * or two weaker barriers into a stronger one.
- * mb X; mb Y => mb X|Y
- * mb; strl => mb; st
- * ldaq; mb => ld; mb
- * ldaq; strl => ld; mb; st
- * Other combinations are also merged into a strong
- * barrier. This is stricter than specified but for
- * the purposes of TCG is better than not optimizing.
- */
- ctx.prev_mb->args[0] |= op->args[0];
- tcg_op_remove(s, op);
- break;
-
- default:
- /* Opcodes that end the block stop the optimization. */
- if ((def->flags & TCG_OPF_BB_END) == 0) {
- break;
- }
- /* fallthru */
- case INDEX_op_qemu_ld_i32:
- case INDEX_op_qemu_ld_i64:
- case INDEX_op_qemu_st_i32:
- case INDEX_op_qemu_st8_i32:
- case INDEX_op_qemu_st_i64:
- /* Opcodes that touch guest memory stop the optimization. */
- ctx.prev_mb = NULL;
- break;
- }
- } else if (opc == INDEX_op_mb) {
- ctx.prev_mb = op;
- }
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 15/48] tcg/optimize: Split out fold_const{1,2}
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (13 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st} Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 16/48] tcg/optimize: Split out fold_setcond2 Richard Henderson
` (34 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Split out a whole bunch of placeholder functions, which are
currently identical. That won't last as more code gets moved.
Use CASE_32_64_VEC for some logical operators that previously
missed the addition of vectors.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 254 +++++++++++++++++++++++++++++++++++++++----------
1 file changed, 202 insertions(+), 52 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 159a5a9ee5..e66d935808 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -660,6 +660,60 @@ static void finish_folding(OptContext *ctx, TCGOp *op)
}
}
+/*
+ * The fold_* functions return true when processing is complete,
+ * usually by folding the operation to a constant or to a copy,
+ * and calling tcg_opt_gen_{mov,movi}. They may do other things,
+ * like collect information about the value produced, for use in
+ * optimizing a subsequent operation.
+ *
+ * These first fold_* functions are all helpers, used by other
+ * folders for more specific operations.
+ */
+
+static bool fold_const1(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1])) {
+ uint64_t t;
+
+ t = arg_info(op->args[1])->val;
+ t = do_constant_folding(op->opc, t, 0);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
+ }
+ return false;
+}
+
+static bool fold_const2(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ uint64_t t1 = arg_info(op->args[1])->val;
+ uint64_t t2 = arg_info(op->args[2])->val;
+
+ t1 = do_constant_folding(op->opc, t1, t2);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
+ }
+ return false;
+}
+
+/*
+ * These outermost fold_<op> functions are sorted alphabetically.
+ */
+
+static bool fold_add(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_and(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_andc(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
static bool fold_call(OptContext *ctx, TCGOp *op)
{
TCGContext *s = ctx->tcg;
@@ -692,6 +746,26 @@ static bool fold_call(OptContext *ctx, TCGOp *op)
return true;
}
+static bool fold_ctpop(OptContext *ctx, TCGOp *op)
+{
+ return fold_const1(ctx, op);
+}
+
+static bool fold_eqv(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_exts(OptContext *ctx, TCGOp *op)
+{
+ return fold_const1(ctx, op);
+}
+
+static bool fold_extu(OptContext *ctx, TCGOp *op)
+{
+ return fold_const1(ctx, op);
+}
+
static bool fold_mb(OptContext *ctx, TCGOp *op)
{
/* Eliminate duplicate and redundant fence instructions. */
@@ -716,6 +790,41 @@ static bool fold_mb(OptContext *ctx, TCGOp *op)
return true;
}
+static bool fold_multiply(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_nand(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_neg(OptContext *ctx, TCGOp *op)
+{
+ return fold_const1(ctx, op);
+}
+
+static bool fold_nor(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_not(OptContext *ctx, TCGOp *op)
+{
+ return fold_const1(ctx, op);
+}
+
+static bool fold_or(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_orc(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
{
/* Opcodes that touch guest memory stop the mb optimization. */
@@ -730,6 +839,21 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
return false;
}
+static bool fold_shift(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_sub(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
+static bool fold_xor(OptContext *ctx, TCGOp *op)
+{
+ return fold_const2(ctx, op);
+}
+
/* Propagate constants and copies, fold constant expressions. */
void tcg_optimize(TCGContext *s)
{
@@ -1276,26 +1400,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(not):
- CASE_OP_32_64(neg):
- CASE_OP_32_64(ext8s):
- CASE_OP_32_64(ext8u):
- CASE_OP_32_64(ext16s):
- CASE_OP_32_64(ext16u):
- CASE_OP_32_64(ctpop):
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_extrl_i64_i32:
- case INDEX_op_extrh_i64_i32:
- if (arg_is_const(op->args[1])) {
- tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
CASE_OP_32_64(bswap16):
CASE_OP_32_64(bswap32):
case INDEX_op_bswap64_i64:
@@ -1307,36 +1411,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(add):
- CASE_OP_32_64(sub):
- CASE_OP_32_64(mul):
- CASE_OP_32_64(or):
- CASE_OP_32_64(and):
- CASE_OP_32_64(xor):
- CASE_OP_32_64(shl):
- CASE_OP_32_64(shr):
- CASE_OP_32_64(sar):
- CASE_OP_32_64(rotl):
- CASE_OP_32_64(rotr):
- CASE_OP_32_64(andc):
- CASE_OP_32_64(orc):
- CASE_OP_32_64(eqv):
- CASE_OP_32_64(nand):
- CASE_OP_32_64(nor):
- CASE_OP_32_64(muluh):
- CASE_OP_32_64(mulsh):
- CASE_OP_32_64(div):
- CASE_OP_32_64(divu):
- CASE_OP_32_64(rem):
- CASE_OP_32_64(remu):
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
- arg_info(op->args[2])->val);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
CASE_OP_32_64(clz):
CASE_OP_32_64(ctz):
if (arg_is_const(op->args[1])) {
@@ -1637,9 +1711,71 @@ void tcg_optimize(TCGContext *s)
}
break;
+ default:
+ break;
+
+ /* ---------------------------------------------------------- */
+ /* Sorted alphabetically by opcode as much as possible. */
+
+ CASE_OP_32_64_VEC(add):
+ done = fold_add(&ctx, op);
+ break;
+ CASE_OP_32_64_VEC(and):
+ done = fold_and(&ctx, op);
+ break;
+ CASE_OP_32_64_VEC(andc):
+ done = fold_andc(&ctx, op);
+ break;
+ CASE_OP_32_64(ctpop):
+ done = fold_ctpop(&ctx, op);
+ break;
+ CASE_OP_32_64(div):
+ CASE_OP_32_64(divu):
+ done = fold_const2(&ctx, op);
+ break;
+ CASE_OP_32_64(eqv):
+ done = fold_eqv(&ctx, op);
+ break;
+ CASE_OP_32_64(ext8s):
+ CASE_OP_32_64(ext16s):
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext_i32_i64:
+ done = fold_exts(&ctx, op);
+ break;
+ CASE_OP_32_64(ext8u):
+ CASE_OP_32_64(ext16u):
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extrh_i64_i32:
+ done = fold_extu(&ctx, op);
+ break;
case INDEX_op_mb:
done = fold_mb(&ctx, op);
break;
+ CASE_OP_32_64(mul):
+ CASE_OP_32_64(mulsh):
+ CASE_OP_32_64(muluh):
+ done = fold_multiply(&ctx, op);
+ break;
+ CASE_OP_32_64(nand):
+ done = fold_nand(&ctx, op);
+ break;
+ CASE_OP_32_64(neg):
+ done = fold_neg(&ctx, op);
+ break;
+ CASE_OP_32_64(nor):
+ done = fold_nor(&ctx, op);
+ break;
+ CASE_OP_32_64_VEC(not):
+ done = fold_not(&ctx, op);
+ break;
+ CASE_OP_32_64_VEC(or):
+ done = fold_or(&ctx, op);
+ break;
+ CASE_OP_32_64_VEC(orc):
+ done = fold_orc(&ctx, op);
+ break;
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
done = fold_qemu_ld(&ctx, op);
@@ -1649,8 +1785,22 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_qemu_st_i64:
done = fold_qemu_st(&ctx, op);
break;
-
- default:
+ CASE_OP_32_64(rem):
+ CASE_OP_32_64(remu):
+ done = fold_const2(&ctx, op);
+ break;
+ CASE_OP_32_64(rotl):
+ CASE_OP_32_64(rotr):
+ CASE_OP_32_64(sar):
+ CASE_OP_32_64(shl):
+ CASE_OP_32_64(shr):
+ done = fold_shift(&ctx, op);
+ break;
+ CASE_OP_32_64_VEC(sub):
+ done = fold_sub(&ctx, op);
+ break;
+ CASE_OP_32_64_VEC(xor):
+ done = fold_xor(&ctx, op);
break;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 16/48] tcg/optimize: Split out fold_setcond2
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (14 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 15/48] tcg/optimize: Split out fold_const{1,2} Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2 Richard Henderson
` (33 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Reduce some code duplication by folding the NE and EQ cases.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 145 ++++++++++++++++++++++++-------------------------
1 file changed, 72 insertions(+), 73 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index e66d935808..0eaa0127f3 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -839,6 +839,75 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
return false;
}
+static bool fold_setcond2(OptContext *ctx, TCGOp *op)
+{
+ TCGCond cond = op->args[5];
+ int i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond);
+ int inv = 0;
+
+ if (i >= 0) {
+ goto do_setcond_const;
+ }
+
+ switch (cond) {
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ /*
+ * Simplify LT/GE comparisons vs zero to a single compare
+ * vs the high word of the input.
+ */
+ if (arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0 &&
+ arg_is_const(op->args[4]) && arg_info(op->args[4])->val == 0) {
+ goto do_setcond_high;
+ }
+ break;
+
+ case TCG_COND_NE:
+ inv = 1;
+ QEMU_FALLTHROUGH;
+ case TCG_COND_EQ:
+ /*
+ * Simplify EQ/NE comparisons where one of the pairs
+ * can be simplified.
+ */
+ i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1],
+ op->args[3], cond);
+ switch (i ^ inv) {
+ case 0:
+ goto do_setcond_const;
+ case 1:
+ goto do_setcond_high;
+ }
+
+ i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2],
+ op->args[4], cond);
+ switch (i ^ inv) {
+ case 0:
+ goto do_setcond_const;
+ case 1:
+ op->args[2] = op->args[3];
+ op->args[3] = cond;
+ op->opc = INDEX_op_setcond_i32;
+ break;
+ }
+ break;
+
+ default:
+ break;
+
+ do_setcond_high:
+ op->args[1] = op->args[2];
+ op->args[2] = op->args[4];
+ op->args[3] = cond;
+ op->opc = INDEX_op_setcond_i32;
+ break;
+ }
+ return false;
+
+ do_setcond_const:
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
+}
+
static bool fold_shift(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1638,79 +1707,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- case INDEX_op_setcond2_i32:
- i = do_constant_folding_cond2(&op->args[1], &op->args[3],
- op->args[5]);
- if (i >= 0) {
- do_setcond_const:
- tcg_opt_gen_movi(&ctx, op, op->args[0], i);
- continue;
- }
- if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
- && arg_is_const(op->args[3])
- && arg_info(op->args[3])->val == 0
- && arg_is_const(op->args[4])
- && arg_info(op->args[4])->val == 0) {
- /* Simplify LT/GE comparisons vs zero to a single compare
- vs the high word of the input. */
- do_setcond_high:
- reset_temp(op->args[0]);
- arg_info(op->args[0])->z_mask = 1;
- op->opc = INDEX_op_setcond_i32;
- op->args[1] = op->args[2];
- op->args[2] = op->args[4];
- op->args[3] = op->args[5];
- break;
- }
- if (op->args[5] == TCG_COND_EQ) {
- /* Simplify EQ comparisons where one of the pairs
- can be simplified. */
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[1], op->args[3],
- TCG_COND_EQ);
- if (i == 0) {
- goto do_setcond_const;
- } else if (i > 0) {
- goto do_setcond_high;
- }
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[2], op->args[4],
- TCG_COND_EQ);
- if (i == 0) {
- goto do_setcond_high;
- } else if (i < 0) {
- break;
- }
- do_setcond_low:
- reset_temp(op->args[0]);
- arg_info(op->args[0])->z_mask = 1;
- op->opc = INDEX_op_setcond_i32;
- op->args[2] = op->args[3];
- op->args[3] = op->args[5];
- break;
- }
- if (op->args[5] == TCG_COND_NE) {
- /* Simplify NE comparisons where one of the pairs
- can be simplified. */
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[1], op->args[3],
- TCG_COND_NE);
- if (i == 0) {
- goto do_setcond_high;
- } else if (i > 0) {
- goto do_setcond_const;
- }
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
- op->args[2], op->args[4],
- TCG_COND_NE);
- if (i == 0) {
- goto do_setcond_low;
- } else if (i > 0) {
- goto do_setcond_const;
- }
- }
- break;
-
default:
break;
@@ -1796,6 +1792,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(shr):
done = fold_shift(&ctx, op);
break;
+ case INDEX_op_setcond2_i32:
+ done = fold_setcond2(&ctx, op);
+ break;
CASE_OP_32_64_VEC(sub):
done = fold_sub(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (15 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 16/48] tcg/optimize: Split out fold_setcond2 Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 18/48] tcg/optimize: Split out fold_brcond Richard Henderson
` (32 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Reduce some code duplication by folding the NE and EQ cases.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 161 +++++++++++++++++++++++++------------------------
1 file changed, 83 insertions(+), 78 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 0eaa0127f3..266787957f 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -714,6 +714,86 @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_brcond2(OptContext *ctx, TCGOp *op)
+{
+ TCGCond cond = op->args[4];
+ int i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond);
+ TCGArg label = op->args[5];
+ int inv = 0;
+
+ if (i == 0) {
+ goto do_brcond_false;
+ } else if (i > 0) {
+ goto do_brcond_true;
+ }
+
+ switch (cond) {
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ /*
+ * Simplify LT/GE comparisons vs zero to a single compare
+ * vs the high word of the input.
+ */
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0 &&
+ arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0) {
+ goto do_brcond_high;
+ }
+ break;
+
+ case TCG_COND_NE:
+ inv = 1;
+ QEMU_FALLTHROUGH;
+ case TCG_COND_EQ:
+ /*
+ * Simplify EQ/NE comparisons where one of the pairs
+ * can be simplified.
+ */
+ i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0],
+ op->args[2], cond);
+ switch (i ^ inv) {
+ case 0:
+ goto do_brcond_false;
+ case 1:
+ goto do_brcond_high;
+ }
+
+ i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1],
+ op->args[3], cond);
+ switch (i ^ inv) {
+ case 0:
+ goto do_brcond_false;
+ case 1:
+ op->opc = INDEX_op_brcond_i32;
+ op->args[1] = op->args[2];
+ op->args[2] = cond;
+ op->args[3] = label;
+ break;
+ }
+ break;
+
+ default:
+ break;
+
+ do_brcond_true:
+ op->opc = INDEX_op_br;
+ op->args[0] = label;
+ break;
+
+ do_brcond_high:
+ op->opc = INDEX_op_brcond_i32;
+ op->args[0] = op->args[1];
+ op->args[1] = op->args[3];
+ op->args[2] = cond;
+ op->args[3] = label;
+ break;
+ }
+ return false;
+
+ do_brcond_false:
+ tcg_op_remove(ctx->tcg, op);
+ return true;
+}
+
static bool fold_call(OptContext *ctx, TCGOp *op)
{
TCGContext *s = ctx->tcg;
@@ -1629,84 +1709,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- case INDEX_op_brcond2_i32:
- i = do_constant_folding_cond2(&op->args[0], &op->args[2],
- op->args[4]);
- if (i == 0) {
- do_brcond_false:
- tcg_op_remove(s, op);
- continue;
- }
- if (i > 0) {
- do_brcond_true:
- op->opc = opc = INDEX_op_br;
- op->args[0] = op->args[5];
- break;
- }
- if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE)
- && arg_is_const(op->args[2])
- && arg_info(op->args[2])->val == 0
- && arg_is_const(op->args[3])
- && arg_info(op->args[3])->val == 0) {
- /* Simplify LT/GE comparisons vs zero to a single compare
- vs the high word of the input. */
- do_brcond_high:
- op->opc = opc = INDEX_op_brcond_i32;
- op->args[0] = op->args[1];
- op->args[1] = op->args[3];
- op->args[2] = op->args[4];
- op->args[3] = op->args[5];
- break;
- }
- if (op->args[4] == TCG_COND_EQ) {
- /* Simplify EQ comparisons where one of the pairs
- can be simplified. */
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[0], op->args[2],
- TCG_COND_EQ);
- if (i == 0) {
- goto do_brcond_false;
- } else if (i > 0) {
- goto do_brcond_high;
- }
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[1], op->args[3],
- TCG_COND_EQ);
- if (i == 0) {
- goto do_brcond_false;
- } else if (i < 0) {
- break;
- }
- do_brcond_low:
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
- op->opc = INDEX_op_brcond_i32;
- op->args[1] = op->args[2];
- op->args[2] = op->args[4];
- op->args[3] = op->args[5];
- break;
- }
- if (op->args[4] == TCG_COND_NE) {
- /* Simplify NE comparisons where one of the pairs
- can be simplified. */
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[0], op->args[2],
- TCG_COND_NE);
- if (i == 0) {
- goto do_brcond_high;
- } else if (i > 0) {
- goto do_brcond_true;
- }
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
- op->args[1], op->args[3],
- TCG_COND_NE);
- if (i == 0) {
- goto do_brcond_low;
- } else if (i > 0) {
- goto do_brcond_true;
- }
- }
- break;
-
default:
break;
@@ -1722,6 +1724,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(andc):
done = fold_andc(&ctx, op);
break;
+ case INDEX_op_brcond2_i32:
+ done = fold_brcond2(&ctx, op);
+ break;
CASE_OP_32_64(ctpop):
done = fold_ctpop(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 18/48] tcg/optimize: Split out fold_brcond
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (16 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2 Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 19/48] tcg/optimize: Split out fold_setcond Richard Henderson
` (31 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 266787957f..786d46ed66 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -714,6 +714,22 @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_brcond(OptContext *ctx, TCGOp *op)
+{
+ TCGCond cond = op->args[2];
+ int i = do_constant_folding_cond(op->opc, op->args[0], op->args[1], cond);
+
+ if (i == 0) {
+ tcg_op_remove(ctx->tcg, op);
+ return true;
+ }
+ if (i > 0) {
+ op->opc = INDEX_op_br;
+ op->args[0] = op->args[3];
+ }
+ return false;
+}
+
static bool fold_brcond2(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[4];
@@ -1628,20 +1644,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(brcond):
- i = do_constant_folding_cond(opc, op->args[0],
- op->args[1], op->args[2]);
- if (i == 0) {
- tcg_op_remove(s, op);
- continue;
- } else if (i > 0) {
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
- op->opc = opc = INDEX_op_br;
- op->args[0] = op->args[3];
- break;
- }
- break;
-
CASE_OP_32_64(movcond):
i = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[5]);
@@ -1724,6 +1726,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(andc):
done = fold_andc(&ctx, op);
break;
+ CASE_OP_32_64(brcond):
+ done = fold_brcond(&ctx, op);
+ break;
case INDEX_op_brcond2_i32:
done = fold_brcond2(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 19/48] tcg/optimize: Split out fold_setcond
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (17 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 18/48] tcg/optimize: Split out fold_brcond Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 20/48] tcg/optimize: Split out fold_mulu2_i32 Richard Henderson
` (30 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 786d46ed66..6bb5e19e55 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -935,6 +935,17 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
return false;
}
+static bool fold_setcond(OptContext *ctx, TCGOp *op)
+{
+ TCGCond cond = op->args[3];
+ int i = do_constant_folding_cond(op->opc, op->args[1], op->args[2], cond);
+
+ if (i >= 0) {
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
+ }
+ return false;
+}
+
static bool fold_setcond2(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[5];
@@ -1635,15 +1646,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(setcond):
- i = do_constant_folding_cond(opc, op->args[1],
- op->args[2], op->args[3]);
- if (i >= 0) {
- tcg_opt_gen_movi(&ctx, op, op->args[0], i);
- continue;
- }
- break;
-
CASE_OP_32_64(movcond):
i = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[5]);
@@ -1802,6 +1804,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(shr):
done = fold_shift(&ctx, op);
break;
+ CASE_OP_32_64(setcond):
+ done = fold_setcond(&ctx, op);
+ break;
case INDEX_op_setcond2_i32:
done = fold_setcond2(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 20/48] tcg/optimize: Split out fold_mulu2_i32
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (18 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 19/48] tcg/optimize: Split out fold_setcond Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 21/48] tcg/optimize: Split out fold_addsub2_i32 Richard Henderson
` (29 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 37 +++++++++++++++++++++----------------
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 6bb5e19e55..01a0925c89 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -891,6 +891,24 @@ static bool fold_multiply(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
+ uint32_t a = arg_info(op->args[2])->val;
+ uint32_t b = arg_info(op->args[3])->val;
+ uint64_t r = (uint64_t)a * b;
+ TCGArg rl, rh;
+ TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
+
+ rl = op->args[0];
+ rh = op->args[1];
+ tcg_opt_gen_movi(ctx, op, rl, (int32_t)r);
+ tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(r >> 32));
+ return true;
+ }
+ return false;
+}
+
static bool fold_nand(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1697,22 +1715,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- case INDEX_op_mulu2_i32:
- if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
- uint32_t a = arg_info(op->args[2])->val;
- uint32_t b = arg_info(op->args[3])->val;
- uint64_t r = (uint64_t)a * b;
- TCGArg rl, rh;
- TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32);
-
- rl = op->args[0];
- rh = op->args[1];
- tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r);
- tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32));
- continue;
- }
- break;
-
default:
break;
@@ -1766,6 +1768,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(muluh):
done = fold_multiply(&ctx, op);
break;
+ case INDEX_op_mulu2_i32:
+ done = fold_mulu2_i32(&ctx, op);
+ break;
CASE_OP_32_64(nand):
done = fold_nand(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 21/48] tcg/optimize: Split out fold_addsub2_i32
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (19 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 20/48] tcg/optimize: Split out fold_mulu2_i32 Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 22/48] tcg/optimize: Split out fold_movcond Richard Henderson
` (28 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Add two additional helpers, fold_add2_i32 and fold_sub2_i32
which will not be simple wrappers forever.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 70 +++++++++++++++++++++++++++++++-------------------
1 file changed, 44 insertions(+), 26 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 01a0925c89..1cec06aa81 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -704,6 +704,39 @@ static bool fold_add(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add)
+{
+ if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
+ arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
+ uint32_t al = arg_info(op->args[2])->val;
+ uint32_t ah = arg_info(op->args[3])->val;
+ uint32_t bl = arg_info(op->args[4])->val;
+ uint32_t bh = arg_info(op->args[5])->val;
+ uint64_t a = ((uint64_t)ah << 32) | al;
+ uint64_t b = ((uint64_t)bh << 32) | bl;
+ TCGArg rl, rh;
+ TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
+
+ if (add) {
+ a += b;
+ } else {
+ a -= b;
+ }
+
+ rl = op->args[0];
+ rh = op->args[1];
+ tcg_opt_gen_movi(ctx, op, rl, (int32_t)a);
+ tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(a >> 32));
+ return true;
+ }
+ return false;
+}
+
+static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
+{
+ return fold_addsub2_i32(ctx, op, true);
+}
+
static bool fold_and(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1043,6 +1076,11 @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
+{
+ return fold_addsub2_i32(ctx, op, false);
+}
+
static bool fold_xor(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1688,32 +1726,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
- if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])
- && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
- uint32_t al = arg_info(op->args[2])->val;
- uint32_t ah = arg_info(op->args[3])->val;
- uint32_t bl = arg_info(op->args[4])->val;
- uint32_t bh = arg_info(op->args[5])->val;
- uint64_t a = ((uint64_t)ah << 32) | al;
- uint64_t b = ((uint64_t)bh << 32) | bl;
- TCGArg rl, rh;
- TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32);
-
- if (opc == INDEX_op_add2_i32) {
- a += b;
- } else {
- a -= b;
- }
-
- rl = op->args[0];
- rh = op->args[1];
- tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a);
- tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32));
- continue;
- }
- break;
default:
break;
@@ -1724,6 +1736,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(add):
done = fold_add(&ctx, op);
break;
+ case INDEX_op_add2_i32:
+ done = fold_add2_i32(&ctx, op);
+ break;
CASE_OP_32_64_VEC(and):
done = fold_and(&ctx, op);
break;
@@ -1818,6 +1833,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(sub):
done = fold_sub(&ctx, op);
break;
+ case INDEX_op_sub2_i32:
+ done = fold_sub2_i32(&ctx, op);
+ break;
CASE_OP_32_64_VEC(xor):
done = fold_xor(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 22/48] tcg/optimize: Split out fold_movcond
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (20 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 21/48] tcg/optimize: Split out fold_addsub2_i32 Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 23/48] tcg/optimize: Split out fold_extract2 Richard Henderson
` (27 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 56 ++++++++++++++++++++++++++++----------------------
1 file changed, 31 insertions(+), 25 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 1cec06aa81..c8aa027a5a 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -919,6 +919,34 @@ static bool fold_mb(OptContext *ctx, TCGOp *op)
return true;
}
+static bool fold_movcond(OptContext *ctx, TCGOp *op)
+{
+ TCGOpcode opc = op->opc;
+ TCGCond cond = op->args[5];
+ int i = do_constant_folding_cond(opc, op->args[1], op->args[2], cond);
+
+ if (i >= 0) {
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
+ }
+
+ if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
+ uint64_t tv = arg_info(op->args[3])->val;
+ uint64_t fv = arg_info(op->args[4])->val;
+
+ opc = (opc == INDEX_op_movcond_i32
+ ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64);
+
+ if (tv == 1 && fv == 0) {
+ op->opc = opc;
+ op->args[3] = cond;
+ } else if (fv == 1 && tv == 0) {
+ op->opc = opc;
+ op->args[3] = tcg_invert_cond(cond);
+ }
+ }
+ return false;
+}
+
static bool fold_multiply(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1702,31 +1730,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(movcond):
- i = do_constant_folding_cond(opc, op->args[1],
- op->args[2], op->args[5]);
- if (i >= 0) {
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4 - i]);
- continue;
- }
- if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
- uint64_t tv = arg_info(op->args[3])->val;
- uint64_t fv = arg_info(op->args[4])->val;
- TCGCond cond = op->args[5];
-
- if (fv == 1 && tv == 0) {
- cond = tcg_invert_cond(cond);
- } else if (!(tv == 1 && fv == 0)) {
- break;
- }
- op->args[3] = cond;
- op->opc = opc = (opc == INDEX_op_movcond_i32
- ? INDEX_op_setcond_i32
- : INDEX_op_setcond_i64);
- }
- break;
-
-
default:
break;
@@ -1778,6 +1781,9 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_mb:
done = fold_mb(&ctx, op);
break;
+ CASE_OP_32_64(movcond):
+ done = fold_movcond(&ctx, op);
+ break;
CASE_OP_32_64(mul):
CASE_OP_32_64(mulsh):
CASE_OP_32_64(muluh):
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 23/48] tcg/optimize: Split out fold_extract2
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (21 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 22/48] tcg/optimize: Split out fold_movcond Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 24/48] tcg/optimize: Split out fold_extract, fold_sextract Richard Henderson
` (26 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c8aa027a5a..8229a67192 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -885,6 +885,25 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_extract2(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ uint64_t v1 = arg_info(op->args[1])->val;
+ uint64_t v2 = arg_info(op->args[2])->val;
+ int shr = op->args[3];
+
+ if (op->opc == INDEX_op_extract2_i64) {
+ v1 >>= shr;
+ v2 <<= 64 - shr;
+ } else {
+ v1 = (uint32_t)v1 >> shr;
+ v2 = (int32_t)v2 << (32 - shr);
+ }
+ return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2);
+ }
+ return false;
+}
+
static bool fold_exts(OptContext *ctx, TCGOp *op)
{
return fold_const1(ctx, op);
@@ -1713,23 +1732,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(extract2):
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- uint64_t v1 = arg_info(op->args[1])->val;
- uint64_t v2 = arg_info(op->args[2])->val;
- int shr = op->args[3];
-
- if (opc == INDEX_op_extract2_i64) {
- tmp = (v1 >> shr) | (v2 << (64 - shr));
- } else {
- tmp = (int32_t)(((uint32_t)v1 >> shr) |
- ((uint32_t)v2 << (32 - shr)));
- }
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
default:
break;
@@ -1764,6 +1766,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(eqv):
done = fold_eqv(&ctx, op);
break;
+ CASE_OP_32_64(extract2):
+ done = fold_extract2(&ctx, op);
+ break;
CASE_OP_32_64(ext8s):
CASE_OP_32_64(ext16s):
case INDEX_op_ext32s_i64:
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 24/48] tcg/optimize: Split out fold_extract, fold_sextract
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (22 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 23/48] tcg/optimize: Split out fold_extract2 Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 25/48] tcg/optimize: Split out fold_deposit Richard Henderson
` (25 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 48 ++++++++++++++++++++++++++++++------------------
1 file changed, 30 insertions(+), 18 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 8229a67192..6020a678ab 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -885,6 +885,18 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_extract(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1])) {
+ uint64_t t;
+
+ t = arg_info(op->args[1])->val;
+ t = extract64(t, op->args[2], op->args[3]);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
+ }
+ return false;
+}
+
static bool fold_extract2(OptContext *ctx, TCGOp *op)
{
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
@@ -1113,6 +1125,18 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
}
+static bool fold_sextract(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1])) {
+ uint64_t t;
+
+ t = arg_info(op->args[1])->val;
+ t = sextract64(t, op->args[2], op->args[3]);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
+ }
+ return false;
+}
+
static bool fold_shift(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1714,24 +1738,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(extract):
- if (arg_is_const(op->args[1])) {
- tmp = extract64(arg_info(op->args[1])->val,
- op->args[2], op->args[3]);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
- CASE_OP_32_64(sextract):
- if (arg_is_const(op->args[1])) {
- tmp = sextract64(arg_info(op->args[1])->val,
- op->args[2], op->args[3]);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
default:
break;
@@ -1766,6 +1772,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(eqv):
done = fold_eqv(&ctx, op);
break;
+ CASE_OP_32_64(extract):
+ done = fold_extract(&ctx, op);
+ break;
CASE_OP_32_64(extract2):
done = fold_extract2(&ctx, op);
break;
@@ -1841,6 +1850,9 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_setcond2_i32:
done = fold_setcond2(&ctx, op);
break;
+ CASE_OP_32_64(sextract):
+ done = fold_sextract(&ctx, op);
+ break;
CASE_OP_32_64_VEC(sub):
done = fold_sub(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 25/48] tcg/optimize: Split out fold_deposit
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (23 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 24/48] tcg/optimize: Split out fold_extract, fold_sextract Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 26/48] tcg/optimize: Split out fold_count_zeros Richard Henderson
` (24 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 6020a678ab..dd78982330 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -880,6 +880,18 @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op)
return fold_const1(ctx, op);
}
+static bool fold_deposit(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ uint64_t t1 = arg_info(op->args[1])->val;
+ uint64_t t2 = arg_info(op->args[2])->val;
+
+ t1 = deposit64(t1, op->args[3], op->args[4], t2);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
+ }
+ return false;
+}
+
static bool fold_eqv(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1728,16 +1740,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(deposit):
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- tmp = deposit64(arg_info(op->args[1])->val,
- op->args[3], op->args[4],
- arg_info(op->args[2])->val);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
default:
break;
@@ -1765,6 +1767,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(ctpop):
done = fold_ctpop(&ctx, op);
break;
+ CASE_OP_32_64(deposit):
+ done = fold_deposit(&ctx, op);
+ break;
CASE_OP_32_64(div):
CASE_OP_32_64(divu):
done = fold_const2(&ctx, op);
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 26/48] tcg/optimize: Split out fold_count_zeros
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (24 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 25/48] tcg/optimize: Split out fold_deposit Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 27/48] tcg/optimize: Split out fold_bswap Richard Henderson
` (23 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index dd78982330..d2e5727662 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -875,6 +875,20 @@ static bool fold_call(OptContext *ctx, TCGOp *op)
return true;
}
+static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1])) {
+ uint64_t t = arg_info(op->args[1])->val;
+
+ if (t != 0) {
+ t = do_constant_folding(op->opc, t, 0);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
+ }
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
+ }
+ return false;
+}
+
static bool fold_ctpop(OptContext *ctx, TCGOp *op)
{
return fold_const1(ctx, op);
@@ -1726,20 +1740,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(clz):
- CASE_OP_32_64(ctz):
- if (arg_is_const(op->args[1])) {
- TCGArg v = arg_info(op->args[1])->val;
- if (v != 0) {
- tmp = do_constant_folding(opc, v, 0);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- } else {
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]);
- }
- continue;
- }
- break;
-
default:
break;
@@ -1764,6 +1764,10 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_brcond2_i32:
done = fold_brcond2(&ctx, op);
break;
+ CASE_OP_32_64(clz):
+ CASE_OP_32_64(ctz):
+ done = fold_count_zeros(&ctx, op);
+ break;
CASE_OP_32_64(ctpop):
done = fold_ctpop(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 27/48] tcg/optimize: Split out fold_bswap
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (25 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 26/48] tcg/optimize: Split out fold_count_zeros Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 28/48] tcg/optimize: Split out fold_dup, fold_dup2 Richard Henderson
` (22 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 27 ++++++++++++++++-----------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index d2e5727662..7a7c3e25c5 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -843,6 +843,17 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
return true;
}
+static bool fold_bswap(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1])) {
+ uint64_t t = arg_info(op->args[1])->val;
+
+ t = do_constant_folding(op->opc, t, op->args[2]);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
+ }
+ return false;
+}
+
static bool fold_call(OptContext *ctx, TCGOp *op)
{
TCGContext *s = ctx->tcg;
@@ -1729,17 +1740,6 @@ void tcg_optimize(TCGContext *s)
}
break;
- CASE_OP_32_64(bswap16):
- CASE_OP_32_64(bswap32):
- case INDEX_op_bswap64_i64:
- if (arg_is_const(op->args[1])) {
- tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
- op->args[2]);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
default:
break;
@@ -1764,6 +1764,11 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_brcond2_i32:
done = fold_brcond2(&ctx, op);
break;
+ CASE_OP_32_64(bswap16):
+ CASE_OP_32_64(bswap32):
+ case INDEX_op_bswap64_i64:
+ done = fold_bswap(&ctx, op);
+ break;
CASE_OP_32_64(clz):
CASE_OP_32_64(ctz):
done = fold_count_zeros(&ctx, op);
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 28/48] tcg/optimize: Split out fold_dup, fold_dup2
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (26 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 27/48] tcg/optimize: Split out fold_bswap Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 29/48] tcg/optimize: Split out fold_mov Richard Henderson
` (21 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 53 +++++++++++++++++++++++++++++---------------------
1 file changed, 31 insertions(+), 22 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 7a7c3e25c5..db50cf6499 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -917,6 +917,31 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
return false;
}
+static bool fold_dup(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1])) {
+ uint64_t t = arg_info(op->args[1])->val;
+ t = dup_const(TCGOP_VECE(op), t);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
+ }
+ return false;
+}
+
+static bool fold_dup2(OptContext *ctx, TCGOp *op)
+{
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ uint64_t t = deposit64(arg_info(op->args[1])->val, 32, 32,
+ arg_info(op->args[2])->val);
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
+ }
+
+ if (args_are_copies(op->args[1], op->args[2])) {
+ op->opc = INDEX_op_dup_vec;
+ TCGOP_VECE(op) = MO_32;
+ }
+ return false;
+}
+
static bool fold_eqv(OptContext *ctx, TCGOp *op)
{
return fold_const2(ctx, op);
@@ -1718,28 +1743,6 @@ void tcg_optimize(TCGContext *s)
done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
break;
- case INDEX_op_dup_vec:
- if (arg_is_const(op->args[1])) {
- tmp = arg_info(op->args[1])->val;
- tmp = dup_const(TCGOP_VECE(op), tmp);
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
- continue;
- }
- break;
-
- case INDEX_op_dup2_vec:
- assert(TCG_TARGET_REG_BITS == 32);
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- tcg_opt_gen_movi(&ctx, op, op->args[0],
- deposit64(arg_info(op->args[1])->val, 32, 32,
- arg_info(op->args[2])->val));
- continue;
- } else if (args_are_copies(op->args[1], op->args[2])) {
- op->opc = INDEX_op_dup_vec;
- TCGOP_VECE(op) = MO_32;
- }
- break;
-
default:
break;
@@ -1783,6 +1786,12 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(divu):
done = fold_const2(&ctx, op);
break;
+ case INDEX_op_dup_vec:
+ done = fold_dup(&ctx, op);
+ break;
+ case INDEX_op_dup2_vec:
+ done = fold_dup2(&ctx, op);
+ break;
CASE_OP_32_64(eqv):
done = fold_eqv(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 29/48] tcg/optimize: Split out fold_mov
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (27 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 28/48] tcg/optimize: Split out fold_dup, fold_dup2 Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 30/48] tcg/optimize: Split out fold_xx_to_i Richard Henderson
` (20 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This is the final entry in the main switch that was in a
different form. After this, we have the option to convert
the switch into a function dispatch table.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index db50cf6499..3a923fda10 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1012,6 +1012,11 @@ static bool fold_mb(OptContext *ctx, TCGOp *op)
return true;
}
+static bool fold_mov(OptContext *ctx, TCGOp *op)
+{
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
+}
+
static bool fold_movcond(OptContext *ctx, TCGOp *op)
{
TCGOpcode opc = op->opc;
@@ -1735,20 +1740,11 @@ void tcg_optimize(TCGContext *s)
break;
}
- /* Propagate constants through copy operations and do constant
- folding. Constants will be substituted to arguments by register
- allocator where needed and possible. Also detect copies. */
+ /*
+ * Process each opcode.
+ * Sorted alphabetically by opcode as much as possible.
+ */
switch (opc) {
- CASE_OP_32_64_VEC(mov):
- done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
- break;
-
- default:
- break;
-
- /* ---------------------------------------------------------- */
- /* Sorted alphabetically by opcode as much as possible. */
-
CASE_OP_32_64_VEC(add):
done = fold_add(&ctx, op);
break;
@@ -1818,6 +1814,9 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_mb:
done = fold_mb(&ctx, op);
break;
+ CASE_OP_32_64_VEC(mov):
+ done = fold_mov(&ctx, op);
+ break;
CASE_OP_32_64(movcond):
done = fold_movcond(&ctx, op);
break;
@@ -1885,6 +1884,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(xor):
done = fold_xor(&ctx, op);
break;
+ default:
+ break;
}
if (!done) {
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 30/48] tcg/optimize: Split out fold_xx_to_i
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (28 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 29/48] tcg/optimize: Split out fold_mov Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 31/48] tcg/optimize: Split out fold_xx_to_x Richard Henderson
` (19 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Pull the "op r, a, a => movi r, 0" optimization into a function,
and use it in the outer opcode fold functions.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 41 ++++++++++++++++++++++++-----------------
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3a923fda10..708fb850b0 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -695,6 +695,15 @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
return false;
}
+/* If the binary operation has both arguments equal, fold to @i. */
+static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
+{
+ if (args_are_copies(op->args[1], op->args[2])) {
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
+ }
+ return false;
+}
+
/*
* These outermost fold_<op> functions are sorted alphabetically.
*/
@@ -744,7 +753,11 @@ static bool fold_and(OptContext *ctx, TCGOp *op)
static bool fold_andc(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xx_to_i(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_brcond(OptContext *ctx, TCGOp *op)
@@ -1211,7 +1224,11 @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
static bool fold_sub(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xx_to_i(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
@@ -1221,7 +1238,11 @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
static bool fold_xor(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xx_to_i(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
/* Propagate constants and copies, fold constant expressions. */
@@ -1726,20 +1747,6 @@ void tcg_optimize(TCGContext *s)
break;
}
- /* Simplify expression for "op r, a, a => movi r, 0" cases */
- switch (opc) {
- CASE_OP_32_64_VEC(andc):
- CASE_OP_32_64_VEC(sub):
- CASE_OP_32_64_VEC(xor):
- if (args_are_copies(op->args[1], op->args[2])) {
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
- continue;
- }
- break;
- default:
- break;
- }
-
/*
* Process each opcode.
* Sorted alphabetically by opcode as much as possible.
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 31/48] tcg/optimize: Split out fold_xx_to_x
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (29 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 30/48] tcg/optimize: Split out fold_xx_to_i Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 32/48] tcg/optimize: Split out fold_xi_to_i Richard Henderson
` (18 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Pull the "op r, a, a => mov r, a" optimization into a function,
and use it in the outer opcode fold functions.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 39 ++++++++++++++++++++++++---------------
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 708fb850b0..1ba3a78585 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -704,8 +704,22 @@ static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
return false;
}
+/* If the binary operation has both arguments equal, fold to identity. */
+static bool fold_xx_to_x(OptContext *ctx, TCGOp *op)
+{
+ if (args_are_copies(op->args[1], op->args[2])) {
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
+ }
+ return false;
+}
+
/*
* These outermost fold_<op> functions are sorted alphabetically.
+ *
+ * The ordering of the transformations should be:
+ * 1) those that produce a constant
+ * 2) those that produce a copy
+ * 3) those that produce information about the result value.
*/
static bool fold_add(OptContext *ctx, TCGOp *op)
@@ -748,7 +762,11 @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
static bool fold_and(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xx_to_x(ctx, op)) {
+ return true;
+ }
+ return false;
}
static bool fold_andc(OptContext *ctx, TCGOp *op)
@@ -1103,7 +1121,11 @@ static bool fold_not(OptContext *ctx, TCGOp *op)
static bool fold_or(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xx_to_x(ctx, op)) {
+ return true;
+ }
+ return false;
}
static bool fold_orc(OptContext *ctx, TCGOp *op)
@@ -1734,19 +1756,6 @@ void tcg_optimize(TCGContext *s)
break;
}
- /* Simplify expression for "op r, a, a => mov r, a" cases */
- switch (opc) {
- CASE_OP_32_64_VEC(or):
- CASE_OP_32_64_VEC(and):
- if (args_are_copies(op->args[1], op->args[2])) {
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
- continue;
- }
- break;
- default:
- break;
- }
-
/*
* Process each opcode.
* Sorted alphabetically by opcode as much as possible.
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 32/48] tcg/optimize: Split out fold_xi_to_i
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (30 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 31/48] tcg/optimize: Split out fold_xx_to_x Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 33/48] tcg/optimize: Add type to OptContext Richard Henderson
` (17 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Pull the "op r, a, 0 => movi r, 0" optimization into a function,
and use it in the outer opcode fold functions.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 32 +++++++++++++++-----------------
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 1ba3a78585..0734bcb42e 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -695,6 +695,15 @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
return false;
}
+/* If the binary operation has second argument @i, fold to @i. */
+static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
+{
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) {
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
+ }
+ return false;
+}
+
/* If the binary operation has both arguments equal, fold to @i. */
static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
{
@@ -763,6 +772,7 @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
static bool fold_and(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
+ fold_xi_to_i(ctx, op, 0) ||
fold_xx_to_x(ctx, op)) {
return true;
}
@@ -1078,7 +1088,11 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
static bool fold_multiply(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xi_to_i(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
@@ -1740,22 +1754,6 @@ void tcg_optimize(TCGContext *s)
continue;
}
- /* Simplify expression for "op r, a, 0 => movi r, 0" cases */
- switch (opc) {
- CASE_OP_32_64_VEC(and):
- CASE_OP_32_64_VEC(mul):
- CASE_OP_32_64(muluh):
- CASE_OP_32_64(mulsh):
- if (arg_is_const(op->args[2])
- && arg_info(op->args[2])->val == 0) {
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
- continue;
- }
- break;
- default:
- break;
- }
-
/*
* Process each opcode.
* Sorted alphabetically by opcode as much as possible.
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 33/48] tcg/optimize: Add type to OptContext
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (31 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 32/48] tcg/optimize: Split out fold_xi_to_i Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 34/48] tcg/optimize: Split out fold_to_not Richard Henderson
` (16 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Compute the type of the operation early.
There are at least 4 places that used a def->flags ladder
to determine the type of the operation being optimized.
There were two places that assumed !TCG_OPF_64BIT means
TCG_TYPE_I32, and so could potentially compute incorrect
results for vector operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 130 ++++++++++++++++++++++++++++---------------------
1 file changed, 75 insertions(+), 55 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 0734bcb42e..324866cbf1 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -51,6 +51,7 @@ typedef struct OptContext {
/* In flight values from optimization. */
uint64_t z_mask;
+ TCGType type;
} OptContext;
static inline TempOptInfo *ts_info(TCGTemp *ts)
@@ -187,7 +188,6 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
{
TCGTemp *dst_ts = arg_temp(dst);
TCGTemp *src_ts = arg_temp(src);
- const TCGOpDef *def;
TempOptInfo *di;
TempOptInfo *si;
uint64_t z_mask;
@@ -201,16 +201,24 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
reset_ts(dst_ts);
di = ts_info(dst_ts);
si = ts_info(src_ts);
- def = &tcg_op_defs[op->opc];
- if (def->flags & TCG_OPF_VECTOR) {
- new_op = INDEX_op_mov_vec;
- } else if (def->flags & TCG_OPF_64BIT) {
- new_op = INDEX_op_mov_i64;
- } else {
+
+ switch (ctx->type) {
+ case TCG_TYPE_I32:
new_op = INDEX_op_mov_i32;
+ break;
+ case TCG_TYPE_I64:
+ new_op = INDEX_op_mov_i64;
+ break;
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
+ new_op = INDEX_op_mov_vec;
+ break;
+ default:
+ g_assert_not_reached();
}
op->opc = new_op;
- /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
op->args[0] = dst;
op->args[1] = src;
@@ -237,20 +245,9 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
TCGArg dst, uint64_t val)
{
- const TCGOpDef *def = &tcg_op_defs[op->opc];
- TCGType type;
- TCGTemp *tv;
-
- if (def->flags & TCG_OPF_VECTOR) {
- type = TCGOP_VECL(op) + TCG_TYPE_V64;
- } else if (def->flags & TCG_OPF_64BIT) {
- type = TCG_TYPE_I64;
- } else {
- type = TCG_TYPE_I32;
- }
-
/* Convert movi to mov with constant temp. */
- tv = tcg_constant_internal(type, val);
+ TCGTemp *tv = tcg_constant_internal(ctx->type, val);
+
init_ts_info(ctx, tv);
return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
}
@@ -420,11 +417,11 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
}
}
-static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y)
+static uint64_t do_constant_folding(TCGOpcode op, TCGType type,
+ uint64_t x, uint64_t y)
{
- const TCGOpDef *def = &tcg_op_defs[op];
uint64_t res = do_constant_folding_2(op, x, y);
- if (!(def->flags & TCG_OPF_64BIT)) {
+ if (type == TCG_TYPE_I32) {
res = (int32_t)res;
}
return res;
@@ -510,19 +507,21 @@ static bool do_constant_folding_cond_eq(TCGCond c)
* Return -1 if the condition can't be simplified,
* and the result of the condition (0 or 1) if it can.
*/
-static int do_constant_folding_cond(TCGOpcode op, TCGArg x,
+static int do_constant_folding_cond(TCGType type, TCGArg x,
TCGArg y, TCGCond c)
{
uint64_t xv = arg_info(x)->val;
uint64_t yv = arg_info(y)->val;
if (arg_is_const(x) && arg_is_const(y)) {
- const TCGOpDef *def = &tcg_op_defs[op];
- tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
- if (def->flags & TCG_OPF_64BIT) {
- return do_constant_folding_cond_64(xv, yv, c);
- } else {
+ switch (type) {
+ case TCG_TYPE_I32:
return do_constant_folding_cond_32(xv, yv, c);
+ case TCG_TYPE_I64:
+ return do_constant_folding_cond_64(xv, yv, c);
+ default:
+ /* Only scalar comparisons are optimizable */
+ return -1;
}
} else if (args_are_copies(x, y)) {
return do_constant_folding_cond_eq(c);
@@ -677,7 +676,7 @@ static bool fold_const1(OptContext *ctx, TCGOp *op)
uint64_t t;
t = arg_info(op->args[1])->val;
- t = do_constant_folding(op->opc, t, 0);
+ t = do_constant_folding(op->opc, ctx->type, t, 0);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
return false;
@@ -689,7 +688,7 @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
uint64_t t1 = arg_info(op->args[1])->val;
uint64_t t2 = arg_info(op->args[2])->val;
- t1 = do_constant_folding(op->opc, t1, t2);
+ t1 = do_constant_folding(op->opc, ctx->type, t1, t2);
return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
}
return false;
@@ -791,7 +790,7 @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
static bool fold_brcond(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[2];
- int i = do_constant_folding_cond(op->opc, op->args[0], op->args[1], cond);
+ int i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond);
if (i == 0) {
tcg_op_remove(ctx->tcg, op);
@@ -838,7 +837,7 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
* Simplify EQ/NE comparisons where one of the pairs
* can be simplified.
*/
- i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0],
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[0],
op->args[2], cond);
switch (i ^ inv) {
case 0:
@@ -847,7 +846,7 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
goto do_brcond_high;
}
- i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1],
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1],
op->args[3], cond);
switch (i ^ inv) {
case 0:
@@ -889,7 +888,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
if (arg_is_const(op->args[1])) {
uint64_t t = arg_info(op->args[1])->val;
- t = do_constant_folding(op->opc, t, op->args[2]);
+ t = do_constant_folding(op->opc, ctx->type, t, op->args[2]);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
return false;
@@ -933,7 +932,7 @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
uint64_t t = arg_info(op->args[1])->val;
if (t != 0) {
- t = do_constant_folding(op->opc, t, 0);
+ t = do_constant_folding(op->opc, ctx->type, t, 0);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
@@ -1060,9 +1059,8 @@ static bool fold_mov(OptContext *ctx, TCGOp *op)
static bool fold_movcond(OptContext *ctx, TCGOp *op)
{
- TCGOpcode opc = op->opc;
TCGCond cond = op->args[5];
- int i = do_constant_folding_cond(opc, op->args[1], op->args[2], cond);
+ int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
if (i >= 0) {
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
@@ -1071,9 +1069,18 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
uint64_t tv = arg_info(op->args[3])->val;
uint64_t fv = arg_info(op->args[4])->val;
+ TCGOpcode opc;
- opc = (opc == INDEX_op_movcond_i32
- ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64);
+ switch (ctx->type) {
+ case TCG_TYPE_I32:
+ opc = INDEX_op_setcond_i32;
+ break;
+ case TCG_TYPE_I64:
+ opc = INDEX_op_setcond_i64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
if (tv == 1 && fv == 0) {
op->opc = opc;
@@ -1164,7 +1171,7 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
static bool fold_setcond(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[3];
- int i = do_constant_folding_cond(op->opc, op->args[1], op->args[2], cond);
+ int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
if (i >= 0) {
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
@@ -1203,7 +1210,7 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
* Simplify EQ/NE comparisons where one of the pairs
* can be simplified.
*/
- i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1],
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1],
op->args[3], cond);
switch (i ^ inv) {
case 0:
@@ -1212,7 +1219,7 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
goto do_setcond_high;
}
- i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2],
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[2],
op->args[4], cond);
switch (i ^ inv) {
case 0:
@@ -1314,6 +1321,15 @@ void tcg_optimize(TCGContext *s)
init_arguments(&ctx, op, def->nb_oargs + def->nb_iargs);
copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs);
+ /* Pre-compute the type of the operation. */
+ if (def->flags & TCG_OPF_VECTOR) {
+ ctx.type = TCG_TYPE_V64 + TCGOP_VECL(op);
+ } else if (def->flags & TCG_OPF_64BIT) {
+ ctx.type = TCG_TYPE_I64;
+ } else {
+ ctx.type = TCG_TYPE_I32;
+ }
+
/* For commutative operations make constant second argument */
switch (opc) {
CASE_OP_32_64_VEC(add):
@@ -1394,18 +1410,18 @@ void tcg_optimize(TCGContext *s)
/* Proceed with possible constant folding. */
break;
}
- if (opc == INDEX_op_sub_i32) {
+ switch (ctx.type) {
+ case TCG_TYPE_I32:
neg_op = INDEX_op_neg_i32;
have_neg = TCG_TARGET_HAS_neg_i32;
- } else if (opc == INDEX_op_sub_i64) {
+ break;
+ case TCG_TYPE_I64:
neg_op = INDEX_op_neg_i64;
have_neg = TCG_TARGET_HAS_neg_i64;
- } else if (TCG_TARGET_HAS_neg_vec) {
- TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64;
- unsigned vece = TCGOP_VECE(op);
+ break;
+ default:
neg_op = INDEX_op_neg_vec;
- have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0;
- } else {
+ have_neg = tcg_can_emit_vec_op(neg_op, ctx.type, TCGOP_VECE(op)) > 0;
break;
}
if (!have_neg) {
@@ -1459,15 +1475,19 @@ void tcg_optimize(TCGContext *s)
TCGOpcode not_op;
bool have_not;
- if (def->flags & TCG_OPF_VECTOR) {
+ switch (ctx.type) {
+ default:
not_op = INDEX_op_not_vec;
have_not = TCG_TARGET_HAS_not_vec;
- } else if (def->flags & TCG_OPF_64BIT) {
+ break;
+ case TCG_TYPE_I64:
not_op = INDEX_op_not_i64;
have_not = TCG_TARGET_HAS_not_i64;
- } else {
+ break;
+ case TCG_TYPE_I32:
not_op = INDEX_op_not_i32;
have_not = TCG_TARGET_HAS_not_i32;
+ break;
}
if (!have_not) {
break;
@@ -1738,7 +1758,7 @@ void tcg_optimize(TCGContext *s)
below, we can ignore high bits, but for further optimizations we
need to record that the high bits contain garbage. */
partmask = z_mask;
- if (!(def->flags & TCG_OPF_64BIT)) {
+ if (ctx.type == TCG_TYPE_I32) {
z_mask |= ~(tcg_target_ulong)0xffffffffu;
partmask &= 0xffffffffu;
affected &= 0xffffffffu;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 34/48] tcg/optimize: Split out fold_to_not
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (32 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 33/48] tcg/optimize: Add type to OptContext Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 35/48] tcg/optimize: Split out fold_sub_to_neg Richard Henderson
` (15 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Split out the conditional conversion from a more complex logical
operation to a simple NOT. Create a couple more helpers to make
this easy for the outer-most logical operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 154 +++++++++++++++++++++++++++----------------------
1 file changed, 86 insertions(+), 68 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 324866cbf1..1574954668 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -694,6 +694,52 @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
return false;
}
+/*
+ * Convert @op to NOT, if NOT is supported by the host.
+ * Return true f the conversion is successful, which will still
+ * indicate that the processing is complete.
+ */
+static bool fold_not(OptContext *ctx, TCGOp *op);
+static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx)
+{
+ TCGOpcode not_op;
+ bool have_not;
+
+ switch (ctx->type) {
+ case TCG_TYPE_I32:
+ not_op = INDEX_op_not_i32;
+ have_not = TCG_TARGET_HAS_not_i32;
+ break;
+ case TCG_TYPE_I64:
+ not_op = INDEX_op_not_i64;
+ have_not = TCG_TARGET_HAS_not_i64;
+ break;
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ not_op = INDEX_op_not_vec;
+ have_not = TCG_TARGET_HAS_not_vec;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (have_not) {
+ op->opc = not_op;
+ op->args[1] = op->args[idx];
+ return fold_not(ctx, op);
+ }
+ return false;
+}
+
+/* If the binary operation has first argument @i, fold to NOT. */
+static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
+{
+ if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == i) {
+ return fold_to_not(ctx, op, 2);
+ }
+ return false;
+}
+
/* If the binary operation has second argument @i, fold to @i. */
static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
{
@@ -703,6 +749,15 @@ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
return false;
}
+/* If the binary operation has second argument @i, fold to NOT. */
+static bool fold_xi_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
+{
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) {
+ return fold_to_not(ctx, op, 1);
+ }
+ return false;
+}
+
/* If the binary operation has both arguments equal, fold to @i. */
static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
{
@@ -781,7 +836,8 @@ static bool fold_and(OptContext *ctx, TCGOp *op)
static bool fold_andc(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
- fold_xx_to_i(ctx, op, 0)) {
+ fold_xx_to_i(ctx, op, 0) ||
+ fold_ix_to_not(ctx, op, -1)) {
return true;
}
return false;
@@ -984,7 +1040,11 @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
static bool fold_eqv(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xi_to_not(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_extract(OptContext *ctx, TCGOp *op)
@@ -1122,7 +1182,11 @@ static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
static bool fold_nand(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xi_to_not(ctx, op, -1)) {
+ return true;
+ }
+ return false;
}
static bool fold_neg(OptContext *ctx, TCGOp *op)
@@ -1132,12 +1196,22 @@ static bool fold_neg(OptContext *ctx, TCGOp *op)
static bool fold_nor(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xi_to_not(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_not(OptContext *ctx, TCGOp *op)
{
- return fold_const1(ctx, op);
+ if (fold_const1(ctx, op)) {
+ return true;
+ }
+
+ /* Because of fold_to_not, we want to always return true, via finish. */
+ finish_folding(ctx, op);
+ return true;
}
static bool fold_or(OptContext *ctx, TCGOp *op)
@@ -1151,7 +1225,11 @@ static bool fold_or(OptContext *ctx, TCGOp *op)
static bool fold_orc(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xi_to_not(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
@@ -1282,7 +1360,8 @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
static bool fold_xor(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
- fold_xx_to_i(ctx, op, 0)) {
+ fold_xx_to_i(ctx, op, 0) ||
+ fold_xi_to_not(ctx, op, -1)) {
return true;
}
return false;
@@ -1436,67 +1515,6 @@ void tcg_optimize(TCGContext *s)
}
}
break;
- CASE_OP_32_64_VEC(xor):
- CASE_OP_32_64(nand):
- if (!arg_is_const(op->args[1])
- && arg_is_const(op->args[2])
- && arg_info(op->args[2])->val == -1) {
- i = 1;
- goto try_not;
- }
- break;
- CASE_OP_32_64(nor):
- if (!arg_is_const(op->args[1])
- && arg_is_const(op->args[2])
- && arg_info(op->args[2])->val == 0) {
- i = 1;
- goto try_not;
- }
- break;
- CASE_OP_32_64_VEC(andc):
- if (!arg_is_const(op->args[2])
- && arg_is_const(op->args[1])
- && arg_info(op->args[1])->val == -1) {
- i = 2;
- goto try_not;
- }
- break;
- CASE_OP_32_64_VEC(orc):
- CASE_OP_32_64(eqv):
- if (!arg_is_const(op->args[2])
- && arg_is_const(op->args[1])
- && arg_info(op->args[1])->val == 0) {
- i = 2;
- goto try_not;
- }
- break;
- try_not:
- {
- TCGOpcode not_op;
- bool have_not;
-
- switch (ctx.type) {
- default:
- not_op = INDEX_op_not_vec;
- have_not = TCG_TARGET_HAS_not_vec;
- break;
- case TCG_TYPE_I64:
- not_op = INDEX_op_not_i64;
- have_not = TCG_TARGET_HAS_not_i64;
- break;
- case TCG_TYPE_I32:
- not_op = INDEX_op_not_i32;
- have_not = TCG_TARGET_HAS_not_i32;
- break;
- }
- if (!have_not) {
- break;
- }
- op->opc = not_op;
- reset_temp(op->args[0]);
- op->args[1] = op->args[i];
- continue;
- }
default:
break;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 35/48] tcg/optimize: Split out fold_sub_to_neg
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (33 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 34/48] tcg/optimize: Split out fold_to_not Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 36/48] tcg/optimize: Split out fold_xi_to_x Richard Henderson
` (14 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Even though there is only one user, place this more complex
conversion into its own helper.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 84 ++++++++++++++++++++++++++++----------------------
1 file changed, 47 insertions(+), 37 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 1574954668..9d7b174443 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1191,7 +1191,15 @@ static bool fold_nand(OptContext *ctx, TCGOp *op)
static bool fold_neg(OptContext *ctx, TCGOp *op)
{
- return fold_const1(ctx, op);
+ if (fold_const1(ctx, op)) {
+ return true;
+ }
+ /*
+ * Because of fold_sub_to_neg, we want to always return true,
+ * via finish_folding.
+ */
+ finish_folding(ctx, op);
+ return true;
}
static bool fold_nor(OptContext *ctx, TCGOp *op)
@@ -1343,10 +1351,47 @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
return fold_const2(ctx, op);
}
+static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
+{
+ TCGOpcode neg_op;
+ bool have_neg;
+
+ if (!arg_is_const(op->args[1]) || arg_info(op->args[1])->val != 0) {
+ return false;
+ }
+
+ switch (ctx->type) {
+ case TCG_TYPE_I32:
+ neg_op = INDEX_op_neg_i32;
+ have_neg = TCG_TARGET_HAS_neg_i32;
+ break;
+ case TCG_TYPE_I64:
+ neg_op = INDEX_op_neg_i64;
+ have_neg = TCG_TARGET_HAS_neg_i64;
+ break;
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ neg_op = INDEX_op_neg_vec;
+ have_neg = (TCG_TARGET_HAS_neg_vec &&
+ tcg_can_emit_vec_op(neg_op, ctx->type, TCGOP_VECE(op)) > 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (have_neg) {
+ op->opc = neg_op;
+ op->args[1] = op->args[2];
+ return fold_neg(ctx, op);
+ }
+ return false;
+}
+
static bool fold_sub(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
- fold_xx_to_i(ctx, op, 0)) {
+ fold_xx_to_i(ctx, op, 0) ||
+ fold_sub_to_neg(ctx, op)) {
return true;
}
return false;
@@ -1480,41 +1525,6 @@ void tcg_optimize(TCGContext *s)
continue;
}
break;
- CASE_OP_32_64_VEC(sub):
- {
- TCGOpcode neg_op;
- bool have_neg;
-
- if (arg_is_const(op->args[2])) {
- /* Proceed with possible constant folding. */
- break;
- }
- switch (ctx.type) {
- case TCG_TYPE_I32:
- neg_op = INDEX_op_neg_i32;
- have_neg = TCG_TARGET_HAS_neg_i32;
- break;
- case TCG_TYPE_I64:
- neg_op = INDEX_op_neg_i64;
- have_neg = TCG_TARGET_HAS_neg_i64;
- break;
- default:
- neg_op = INDEX_op_neg_vec;
- have_neg = tcg_can_emit_vec_op(neg_op, ctx.type, TCGOP_VECE(op)) > 0;
- break;
- }
- if (!have_neg) {
- break;
- }
- if (arg_is_const(op->args[1])
- && arg_info(op->args[1])->val == 0) {
- op->opc = neg_op;
- reset_temp(op->args[0]);
- op->args[1] = op->args[2];
- continue;
- }
- }
- break;
default:
break;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 36/48] tcg/optimize: Split out fold_xi_to_x
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (34 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 35/48] tcg/optimize: Split out fold_sub_to_neg Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 37/48] tcg/optimize: Split out fold_ix_to_i Richard Henderson
` (13 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Pull the "op r, a, i => mov r, a" optimization into a function,
and use them int the outer-most logical operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 60 +++++++++++++++++++++-----------------------------
1 file changed, 25 insertions(+), 35 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 9d7b174443..d1d0f3f60c 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -749,6 +749,15 @@ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
return false;
}
+/* If the binary operation has second argument @i, fold to identity. */
+static bool fold_xi_to_x(OptContext *ctx, TCGOp *op, uint64_t i)
+{
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) {
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
+ }
+ return false;
+}
+
/* If the binary operation has second argument @i, fold to NOT. */
static bool fold_xi_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
{
@@ -787,7 +796,11 @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op)
static bool fold_add(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xi_to_x(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add)
@@ -827,6 +840,7 @@ static bool fold_and(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
fold_xi_to_i(ctx, op, 0) ||
+ fold_xi_to_x(ctx, op, -1) ||
fold_xx_to_x(ctx, op)) {
return true;
}
@@ -837,6 +851,7 @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
fold_xx_to_i(ctx, op, 0) ||
+ fold_xi_to_x(ctx, op, 0) ||
fold_ix_to_not(ctx, op, -1)) {
return true;
}
@@ -1041,6 +1056,7 @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
static bool fold_eqv(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
+ fold_xi_to_x(ctx, op, -1) ||
fold_xi_to_not(ctx, op, 0)) {
return true;
}
@@ -1225,6 +1241,7 @@ static bool fold_not(OptContext *ctx, TCGOp *op)
static bool fold_or(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
+ fold_xi_to_x(ctx, op, 0) ||
fold_xx_to_x(ctx, op)) {
return true;
}
@@ -1348,7 +1365,11 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
static bool fold_shift(OptContext *ctx, TCGOp *op)
{
- return fold_const2(ctx, op);
+ if (fold_const2(ctx, op) ||
+ fold_xi_to_x(ctx, op, 0)) {
+ return true;
+ }
+ return false;
}
static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
@@ -1391,6 +1412,7 @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
fold_xx_to_i(ctx, op, 0) ||
+ fold_xi_to_x(ctx, op, 0) ||
fold_sub_to_neg(ctx, op)) {
return true;
}
@@ -1406,6 +1428,7 @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
fold_xx_to_i(ctx, op, 0) ||
+ fold_xi_to_x(ctx, op, 0) ||
fold_xi_to_not(ctx, op, -1)) {
return true;
}
@@ -1529,39 +1552,6 @@ void tcg_optimize(TCGContext *s)
break;
}
- /* Simplify expression for "op r, a, const => mov r, a" cases */
- switch (opc) {
- CASE_OP_32_64_VEC(add):
- CASE_OP_32_64_VEC(sub):
- CASE_OP_32_64_VEC(or):
- CASE_OP_32_64_VEC(xor):
- CASE_OP_32_64_VEC(andc):
- CASE_OP_32_64(shl):
- CASE_OP_32_64(shr):
- CASE_OP_32_64(sar):
- CASE_OP_32_64(rotl):
- CASE_OP_32_64(rotr):
- if (!arg_is_const(op->args[1])
- && arg_is_const(op->args[2])
- && arg_info(op->args[2])->val == 0) {
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
- continue;
- }
- break;
- CASE_OP_32_64_VEC(and):
- CASE_OP_32_64_VEC(orc):
- CASE_OP_32_64(eqv):
- if (!arg_is_const(op->args[1])
- && arg_is_const(op->args[2])
- && arg_info(op->args[2])->val == -1) {
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
- continue;
- }
- break;
- default:
- break;
- }
-
/* Simplify using known-zero bits. Currently only ops with a single
output argument is supported. */
z_mask = -1;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 37/48] tcg/optimize: Split out fold_ix_to_i
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (35 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 36/48] tcg/optimize: Split out fold_xi_to_x Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 38/48] tcg/optimize: Split out fold_masks Richard Henderson
` (12 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Pull the "op r, 0, b => movi r, 0" optimization into a function,
and use it in fold_shift.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 28 ++++++++++------------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index d1d0f3f60c..ba4ad38007 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -731,6 +731,15 @@ static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx)
return false;
}
+/* If the binary operation has first argument @i, fold to @i. */
+static bool fold_ix_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
+{
+ if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == i) {
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
+ }
+ return false;
+}
+
/* If the binary operation has first argument @i, fold to NOT. */
static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
{
@@ -1366,6 +1375,7 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
static bool fold_shift(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
+ fold_ix_to_i(ctx, op, 0) ||
fold_xi_to_x(ctx, op, 0)) {
return true;
}
@@ -1534,24 +1544,6 @@ void tcg_optimize(TCGContext *s)
break;
}
- /* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
- and "sub r, 0, a => neg r, a" case. */
- switch (opc) {
- CASE_OP_32_64(shl):
- CASE_OP_32_64(shr):
- CASE_OP_32_64(sar):
- CASE_OP_32_64(rotl):
- CASE_OP_32_64(rotr):
- if (arg_is_const(op->args[1])
- && arg_info(op->args[1])->val == 0) {
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
- continue;
- }
- break;
- default:
- break;
- }
-
/* Simplify using known-zero bits. Currently only ops with a single
output argument is supported. */
z_mask = -1;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 38/48] tcg/optimize: Split out fold_masks
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (36 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 37/48] tcg/optimize: Split out fold_ix_to_i Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies Richard Henderson
` (11 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Move all of the known-zero optimizations into the per-opcode
functions. Use fold_masks when there is a possibility of the
result being determined, and simply set ctx->z_mask otherwise.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 545 ++++++++++++++++++++++++++-----------------------
1 file changed, 294 insertions(+), 251 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index ba4ad38007..d82d0f15c7 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -50,7 +50,8 @@ typedef struct OptContext {
TCGTempSet temps_used;
/* In flight values from optimization. */
- uint64_t z_mask;
+ uint64_t a_mask; /* mask bit is 0 iff value identical to first input */
+ uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */
TCGType type;
} OptContext;
@@ -694,6 +695,31 @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
return false;
}
+static bool fold_masks(OptContext *ctx, TCGOp *op)
+{
+ uint64_t a_mask = ctx->a_mask;
+ uint64_t z_mask = ctx->z_mask;
+
+ /*
+ * 32-bit ops generate 32-bit results. For the result is zero test
+ * below, we can ignore high bits, but for further optimizations we
+ * need to record that the high bits contain garbage.
+ */
+ if (ctx->type == TCG_TYPE_I32) {
+ ctx->z_mask |= MAKE_64BIT_MASK(32, 32);
+ a_mask &= MAKE_64BIT_MASK(0, 32);
+ z_mask &= MAKE_64BIT_MASK(0, 32);
+ }
+
+ if (z_mask == 0) {
+ return tcg_opt_gen_movi(ctx, op, op->args[0], 0);
+ }
+ if (a_mask == 0) {
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
+ }
+ return false;
+}
+
/*
* Convert @op to NOT, if NOT is supported by the host.
* Return true f the conversion is successful, which will still
@@ -847,24 +873,55 @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
static bool fold_and(OptContext *ctx, TCGOp *op)
{
+ uint64_t z1, z2;
+
if (fold_const2(ctx, op) ||
fold_xi_to_i(ctx, op, 0) ||
fold_xi_to_x(ctx, op, -1) ||
fold_xx_to_x(ctx, op)) {
return true;
}
- return false;
+
+ z1 = arg_info(op->args[1])->z_mask;
+ z2 = arg_info(op->args[2])->z_mask;
+ ctx->z_mask = z1 & z2;
+
+ /*
+ * Known-zeros does not imply known-ones. Therefore unless
+ * arg2 is constant, we can't infer affected bits from it.
+ */
+ if (arg_is_const(op->args[2])) {
+ ctx->a_mask = z1 & ~z2;
+ }
+
+ return fold_masks(ctx, op);
}
static bool fold_andc(OptContext *ctx, TCGOp *op)
{
+ uint64_t z1;
+
if (fold_const2(ctx, op) ||
fold_xx_to_i(ctx, op, 0) ||
fold_xi_to_x(ctx, op, 0) ||
fold_ix_to_not(ctx, op, -1)) {
return true;
}
- return false;
+
+ z1 = arg_info(op->args[1])->z_mask;
+
+ /*
+ * Known-zeros does not imply known-ones. Therefore unless
+ * arg2 is constant, we can't infer anything from it.
+ */
+ if (arg_is_const(op->args[2])) {
+ uint64_t z2 = ~arg_info(op->args[2])->z_mask;
+ ctx->a_mask = z1 & ~z2;
+ z1 &= z2;
+ }
+ ctx->z_mask = z1;
+
+ return fold_masks(ctx, op);
}
static bool fold_brcond(OptContext *ctx, TCGOp *op)
@@ -965,13 +1022,52 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
static bool fold_bswap(OptContext *ctx, TCGOp *op)
{
+ uint64_t z_mask, sign;
+
if (arg_is_const(op->args[1])) {
uint64_t t = arg_info(op->args[1])->val;
t = do_constant_folding(op->opc, ctx->type, t, op->args[2]);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
- return false;
+
+ z_mask = arg_info(op->args[1])->z_mask;
+ switch (op->opc) {
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ z_mask = bswap16(z_mask);
+ sign = INT16_MIN;
+ break;
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ z_mask = bswap32(z_mask);
+ sign = INT32_MIN;
+ break;
+ case INDEX_op_bswap64_i64:
+ z_mask = bswap64(z_mask);
+ sign = INT64_MIN;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
+ case TCG_BSWAP_OZ:
+ break;
+ case TCG_BSWAP_OS:
+ /* If the sign bit may be 1, force all the bits above to 1. */
+ if (z_mask & sign) {
+ z_mask |= sign;
+ }
+ break;
+ default:
+ /* The high bits are undefined: force all bits above the sign to 1. */
+ z_mask |= sign << 1;
+ break;
+ }
+ ctx->z_mask = z_mask;
+
+ return fold_masks(ctx, op);
}
static bool fold_call(OptContext *ctx, TCGOp *op)
@@ -1008,6 +1104,8 @@ static bool fold_call(OptContext *ctx, TCGOp *op)
static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
{
+ uint64_t z_mask;
+
if (arg_is_const(op->args[1])) {
uint64_t t = arg_info(op->args[1])->val;
@@ -1017,12 +1115,39 @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
}
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
}
+
+ switch (ctx->type) {
+ case TCG_TYPE_I32:
+ z_mask = 31;
+ break;
+ case TCG_TYPE_I64:
+ z_mask = 63;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask;
+
return false;
}
static bool fold_ctpop(OptContext *ctx, TCGOp *op)
{
- return fold_const1(ctx, op);
+ if (fold_const1(ctx, op)) {
+ return true;
+ }
+
+ switch (ctx->type) {
+ case TCG_TYPE_I32:
+ ctx->z_mask = 32 | 31;
+ break;
+ case TCG_TYPE_I64:
+ ctx->z_mask = 64 | 63;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return false;
}
static bool fold_deposit(OptContext *ctx, TCGOp *op)
@@ -1034,6 +1159,10 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
t1 = deposit64(t1, op->args[3], op->args[4], t2);
return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
}
+
+ ctx->z_mask = deposit64(arg_info(op->args[1])->z_mask,
+ op->args[3], op->args[4],
+ arg_info(op->args[2])->z_mask);
return false;
}
@@ -1074,6 +1203,8 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
static bool fold_extract(OptContext *ctx, TCGOp *op)
{
+ uint64_t z_mask_old, z_mask;
+
if (arg_is_const(op->args[1])) {
uint64_t t;
@@ -1081,7 +1212,15 @@ static bool fold_extract(OptContext *ctx, TCGOp *op)
t = extract64(t, op->args[2], op->args[3]);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
- return false;
+
+ z_mask_old = arg_info(op->args[1])->z_mask;
+ z_mask = sextract64(z_mask_old, op->args[2], op->args[3]);
+ if (op->args[2] == 0) {
+ ctx->a_mask = z_mask_old ^ z_mask;
+ }
+ ctx->z_mask = z_mask;
+
+ return fold_masks(ctx, op);
}
static bool fold_extract2(OptContext *ctx, TCGOp *op)
@@ -1105,12 +1244,83 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
static bool fold_exts(OptContext *ctx, TCGOp *op)
{
- return fold_const1(ctx, op);
+ uint64_t z_mask_old, z_mask, sign;
+ bool type_change = false;
+
+ if (fold_const1(ctx, op)) {
+ return true;
+ }
+
+ z_mask_old = z_mask = arg_info(op->args[1])->z_mask;
+
+ switch (op->opc) {
+ CASE_OP_32_64(ext8s):
+ sign = INT8_MIN;
+ z_mask = (uint8_t)z_mask;
+ break;
+ CASE_OP_32_64(ext16s):
+ sign = INT16_MIN;
+ z_mask = (uint16_t)z_mask;
+ break;
+ case INDEX_op_ext_i32_i64:
+ type_change = true;
+ QEMU_FALLTHROUGH;
+ case INDEX_op_ext32s_i64:
+ sign = INT32_MIN;
+ z_mask = (uint32_t)z_mask;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (z_mask & sign) {
+ z_mask |= sign;
+ } else if (!type_change) {
+ ctx->a_mask = z_mask_old ^ z_mask;
+ }
+ ctx->z_mask = z_mask;
+
+ return fold_masks(ctx, op);
}
static bool fold_extu(OptContext *ctx, TCGOp *op)
{
- return fold_const1(ctx, op);
+ uint64_t z_mask_old, z_mask;
+ bool type_change = false;
+
+ if (fold_const1(ctx, op)) {
+ return true;
+ }
+
+ z_mask_old = z_mask = arg_info(op->args[1])->z_mask;
+
+ switch (op->opc) {
+ CASE_OP_32_64(ext8u):
+ z_mask = (uint8_t)z_mask;
+ break;
+ CASE_OP_32_64(ext16u):
+ z_mask = (uint16_t)z_mask;
+ break;
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extu_i32_i64:
+ type_change = true;
+ QEMU_FALLTHROUGH;
+ case INDEX_op_ext32u_i64:
+ z_mask = (uint32_t)z_mask;
+ break;
+ case INDEX_op_extrh_i64_i32:
+ type_change = true;
+ z_mask >>= 32;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ ctx->z_mask = z_mask;
+ if (!type_change) {
+ ctx->a_mask = z_mask_old ^ z_mask;
+ }
+ return fold_masks(ctx, op);
}
static bool fold_mb(OptContext *ctx, TCGOp *op)
@@ -1151,6 +1361,9 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
}
+ ctx->z_mask = arg_info(op->args[3])->z_mask
+ | arg_info(op->args[4])->z_mask;
+
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
uint64_t tv = arg_info(op->args[3])->val;
uint64_t fv = arg_info(op->args[4])->val;
@@ -1216,9 +1429,16 @@ static bool fold_nand(OptContext *ctx, TCGOp *op)
static bool fold_neg(OptContext *ctx, TCGOp *op)
{
+ uint64_t z_mask;
+
if (fold_const1(ctx, op)) {
return true;
}
+
+ /* Set to 1 all bits to the left of the rightmost. */
+ z_mask = arg_info(op->args[1])->z_mask;
+ ctx->z_mask = -(z_mask & -z_mask);
+
/*
* Because of fold_sub_to_neg, we want to always return true,
* via finish_folding.
@@ -1254,7 +1474,10 @@ static bool fold_or(OptContext *ctx, TCGOp *op)
fold_xx_to_x(ctx, op)) {
return true;
}
- return false;
+
+ ctx->z_mask = arg_info(op->args[1])->z_mask
+ | arg_info(op->args[2])->z_mask;
+ return fold_masks(ctx, op);
}
static bool fold_orc(OptContext *ctx, TCGOp *op)
@@ -1268,6 +1491,15 @@ static bool fold_orc(OptContext *ctx, TCGOp *op)
static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
{
+ const TCGOpDef *def = &tcg_op_defs[op->opc];
+ MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs];
+ MemOp mop = get_memop(oi);
+ int width = 8 << (mop & MO_SIZE);
+
+ if (!(mop & MO_SIGN) && width < 64) {
+ ctx->z_mask = MAKE_64BIT_MASK(0, width);
+ }
+
/* Opcodes that touch guest memory stop the mb optimization. */
ctx->prev_mb = NULL;
return false;
@@ -1288,6 +1520,8 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
if (i >= 0) {
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
}
+
+ ctx->z_mask = 1;
return false;
}
@@ -1354,6 +1588,8 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
op->opc = INDEX_op_setcond_i32;
break;
}
+
+ ctx->z_mask = 1;
return false;
do_setcond_const:
@@ -1362,6 +1598,8 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
static bool fold_sextract(OptContext *ctx, TCGOp *op)
{
+ int64_t z_mask_old, z_mask;
+
if (arg_is_const(op->args[1])) {
uint64_t t;
@@ -1369,7 +1607,15 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
t = sextract64(t, op->args[2], op->args[3]);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
- return false;
+
+ z_mask_old = arg_info(op->args[1])->z_mask;
+ z_mask = sextract64(z_mask_old, op->args[2], op->args[3]);
+ if (op->args[2] == 0 && z_mask >= 0) {
+ ctx->a_mask = z_mask_old ^ z_mask;
+ }
+ ctx->z_mask = z_mask;
+
+ return fold_masks(ctx, op);
}
static bool fold_shift(OptContext *ctx, TCGOp *op)
@@ -1379,6 +1625,13 @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
fold_xi_to_x(ctx, op, 0)) {
return true;
}
+
+ if (arg_is_const(op->args[2])) {
+ ctx->z_mask = do_constant_folding(op->opc, ctx->type,
+ arg_info(op->args[1])->z_mask,
+ arg_info(op->args[2])->val);
+ return fold_masks(ctx, op);
+ }
return false;
}
@@ -1434,6 +1687,25 @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
return fold_addsub2_i32(ctx, op, false);
}
+static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
+{
+ /* We can't do any folding with a load, but we can record bits. */
+ switch (op->opc) {
+ CASE_OP_32_64(ld8u):
+ ctx->z_mask = 0xff;
+ break;
+ CASE_OP_32_64(ld16u):
+ ctx->z_mask = 0xffff;
+ break;
+ case INDEX_op_ld32u_i64:
+ ctx->z_mask = 0xffffffffu;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return false;
+}
+
static bool fold_xor(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
@@ -1442,7 +1714,10 @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
fold_xi_to_not(ctx, op, -1)) {
return true;
}
- return false;
+
+ ctx->z_mask = arg_info(op->args[1])->z_mask
+ | arg_info(op->args[2])->z_mask;
+ return fold_masks(ctx, op);
}
/* Propagate constants and copies, fold constant expressions. */
@@ -1463,7 +1738,6 @@ void tcg_optimize(TCGContext *s)
}
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
- uint64_t z_mask, partmask, affected, tmp;
TCGOpcode opc = op->opc;
const TCGOpDef *def;
bool done = false;
@@ -1544,245 +1818,9 @@ void tcg_optimize(TCGContext *s)
break;
}
- /* Simplify using known-zero bits. Currently only ops with a single
- output argument is supported. */
- z_mask = -1;
- affected = -1;
- switch (opc) {
- CASE_OP_32_64(ext8s):
- if ((arg_info(op->args[1])->z_mask & 0x80) != 0) {
- break;
- }
- QEMU_FALLTHROUGH;
- CASE_OP_32_64(ext8u):
- z_mask = 0xff;
- goto and_const;
- CASE_OP_32_64(ext16s):
- if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) {
- break;
- }
- QEMU_FALLTHROUGH;
- CASE_OP_32_64(ext16u):
- z_mask = 0xffff;
- goto and_const;
- case INDEX_op_ext32s_i64:
- if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
- break;
- }
- QEMU_FALLTHROUGH;
- case INDEX_op_ext32u_i64:
- z_mask = 0xffffffffU;
- goto and_const;
-
- CASE_OP_32_64(and):
- z_mask = arg_info(op->args[2])->z_mask;
- if (arg_is_const(op->args[2])) {
- and_const:
- affected = arg_info(op->args[1])->z_mask & ~z_mask;
- }
- z_mask = arg_info(op->args[1])->z_mask & z_mask;
- break;
-
- case INDEX_op_ext_i32_i64:
- if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
- break;
- }
- QEMU_FALLTHROUGH;
- case INDEX_op_extu_i32_i64:
- /* We do not compute affected as it is a size changing op. */
- z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
- break;
-
- CASE_OP_32_64(andc):
- /* Known-zeros does not imply known-ones. Therefore unless
- op->args[2] is constant, we can't infer anything from it. */
- if (arg_is_const(op->args[2])) {
- z_mask = ~arg_info(op->args[2])->z_mask;
- goto and_const;
- }
- /* But we certainly know nothing outside args[1] may be set. */
- z_mask = arg_info(op->args[1])->z_mask;
- break;
-
- case INDEX_op_sar_i32:
- if (arg_is_const(op->args[2])) {
- tmp = arg_info(op->args[2])->val & 31;
- z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp;
- }
- break;
- case INDEX_op_sar_i64:
- if (arg_is_const(op->args[2])) {
- tmp = arg_info(op->args[2])->val & 63;
- z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp;
- }
- break;
-
- case INDEX_op_shr_i32:
- if (arg_is_const(op->args[2])) {
- tmp = arg_info(op->args[2])->val & 31;
- z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp;
- }
- break;
- case INDEX_op_shr_i64:
- if (arg_is_const(op->args[2])) {
- tmp = arg_info(op->args[2])->val & 63;
- z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp;
- }
- break;
-
- case INDEX_op_extrl_i64_i32:
- z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
- break;
- case INDEX_op_extrh_i64_i32:
- z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32;
- break;
-
- CASE_OP_32_64(shl):
- if (arg_is_const(op->args[2])) {
- tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
- z_mask = arg_info(op->args[1])->z_mask << tmp;
- }
- break;
-
- CASE_OP_32_64(neg):
- /* Set to 1 all bits to the left of the rightmost. */
- z_mask = -(arg_info(op->args[1])->z_mask
- & -arg_info(op->args[1])->z_mask);
- break;
-
- CASE_OP_32_64(deposit):
- z_mask = deposit64(arg_info(op->args[1])->z_mask,
- op->args[3], op->args[4],
- arg_info(op->args[2])->z_mask);
- break;
-
- CASE_OP_32_64(extract):
- z_mask = extract64(arg_info(op->args[1])->z_mask,
- op->args[2], op->args[3]);
- if (op->args[2] == 0) {
- affected = arg_info(op->args[1])->z_mask & ~z_mask;
- }
- break;
- CASE_OP_32_64(sextract):
- z_mask = sextract64(arg_info(op->args[1])->z_mask,
- op->args[2], op->args[3]);
- if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) {
- affected = arg_info(op->args[1])->z_mask & ~z_mask;
- }
- break;
-
- CASE_OP_32_64(or):
- CASE_OP_32_64(xor):
- z_mask = arg_info(op->args[1])->z_mask
- | arg_info(op->args[2])->z_mask;
- break;
-
- case INDEX_op_clz_i32:
- case INDEX_op_ctz_i32:
- z_mask = arg_info(op->args[2])->z_mask | 31;
- break;
-
- case INDEX_op_clz_i64:
- case INDEX_op_ctz_i64:
- z_mask = arg_info(op->args[2])->z_mask | 63;
- break;
-
- case INDEX_op_ctpop_i32:
- z_mask = 32 | 31;
- break;
- case INDEX_op_ctpop_i64:
- z_mask = 64 | 63;
- break;
-
- CASE_OP_32_64(setcond):
- case INDEX_op_setcond2_i32:
- z_mask = 1;
- break;
-
- CASE_OP_32_64(movcond):
- z_mask = arg_info(op->args[3])->z_mask
- | arg_info(op->args[4])->z_mask;
- break;
-
- CASE_OP_32_64(ld8u):
- z_mask = 0xff;
- break;
- CASE_OP_32_64(ld16u):
- z_mask = 0xffff;
- break;
- case INDEX_op_ld32u_i64:
- z_mask = 0xffffffffu;
- break;
-
- CASE_OP_32_64(qemu_ld):
- {
- MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs];
- MemOp mop = get_memop(oi);
- if (!(mop & MO_SIGN)) {
- z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
- }
- }
- break;
-
- CASE_OP_32_64(bswap16):
- z_mask = arg_info(op->args[1])->z_mask;
- if (z_mask <= 0xffff) {
- op->args[2] |= TCG_BSWAP_IZ;
- }
- z_mask = bswap16(z_mask);
- switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
- case TCG_BSWAP_OZ:
- break;
- case TCG_BSWAP_OS:
- z_mask = (int16_t)z_mask;
- break;
- default: /* undefined high bits */
- z_mask |= MAKE_64BIT_MASK(16, 48);
- break;
- }
- break;
-
- case INDEX_op_bswap32_i64:
- z_mask = arg_info(op->args[1])->z_mask;
- if (z_mask <= 0xffffffffu) {
- op->args[2] |= TCG_BSWAP_IZ;
- }
- z_mask = bswap32(z_mask);
- switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
- case TCG_BSWAP_OZ:
- break;
- case TCG_BSWAP_OS:
- z_mask = (int32_t)z_mask;
- break;
- default: /* undefined high bits */
- z_mask |= MAKE_64BIT_MASK(32, 32);
- break;
- }
- break;
-
- default:
- break;
- }
-
- /* 32-bit ops generate 32-bit results. For the result is zero test
- below, we can ignore high bits, but for further optimizations we
- need to record that the high bits contain garbage. */
- partmask = z_mask;
- if (ctx.type == TCG_TYPE_I32) {
- z_mask |= ~(tcg_target_ulong)0xffffffffu;
- partmask &= 0xffffffffu;
- affected &= 0xffffffffu;
- }
- ctx.z_mask = z_mask;
-
- if (partmask == 0) {
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
- continue;
- }
- if (affected == 0) {
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
- continue;
- }
+ /* Assume all bits affected, and no bits known zero. */
+ ctx.a_mask = -1;
+ ctx.z_mask = -1;
/*
* Process each opcode.
@@ -1855,6 +1893,11 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extrh_i64_i32:
done = fold_extu(&ctx, op);
break;
+ CASE_OP_32_64(ld8u):
+ CASE_OP_32_64(ld16u):
+ case INDEX_op_ld32u_i64:
+ done = fold_tcg_ld(&ctx, op);
+ break;
case INDEX_op_mb:
done = fold_mb(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (37 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 38/48] tcg/optimize: Split out fold_masks Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops Richard Henderson
` (10 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Rename to fold_multiply2, and handle muls2_i32, mulu2_i64,
and muls2_i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 44 +++++++++++++++++++++++++++++++++++---------
1 file changed, 35 insertions(+), 9 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index d82d0f15c7..0011ac31ec 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1400,19 +1400,44 @@ static bool fold_multiply(OptContext *ctx, TCGOp *op)
return false;
}
-static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
+static bool fold_multiply2(OptContext *ctx, TCGOp *op)
{
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
- uint32_t a = arg_info(op->args[2])->val;
- uint32_t b = arg_info(op->args[3])->val;
- uint64_t r = (uint64_t)a * b;
+ uint64_t a = arg_info(op->args[2])->val;
+ uint64_t b = arg_info(op->args[3])->val;
+ uint64_t h, l;
TCGArg rl, rh;
- TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
+ TCGOp *op2;
+
+ switch (op->opc) {
+ case INDEX_op_mulu2_i32:
+ l = (uint64_t)(uint32_t)a * (uint32_t)b;
+ h = (int32_t)(l >> 32);
+ l = (int32_t)l;
+ break;
+ case INDEX_op_muls2_i32:
+ l = (int64_t)(int32_t)a * (int32_t)b;
+ h = l >> 32;
+ l = (int32_t)l;
+ break;
+ case INDEX_op_mulu2_i64:
+ mulu64(&l, &h, a, b);
+ break;
+ case INDEX_op_muls2_i64:
+ muls64(&l, &h, a, b);
+ break;
+ default:
+ g_assert_not_reached();
+ }
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(ctx, op, rl, (int32_t)r);
- tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(r >> 32));
+
+ /* The proper opcode is supplied by tcg_opt_gen_mov. */
+ op2 = tcg_op_insert_before(ctx->tcg, op, 0);
+
+ tcg_opt_gen_movi(ctx, op, rl, l);
+ tcg_opt_gen_movi(ctx, op2, rh, h);
return true;
}
return false;
@@ -1912,8 +1937,9 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(muluh):
done = fold_multiply(&ctx, op);
break;
- case INDEX_op_mulu2_i32:
- done = fold_mulu2_i32(&ctx, op);
+ CASE_OP_32_64(muls2):
+ CASE_OP_32_64(mulu2):
+ done = fold_multiply2(&ctx, op);
break;
CASE_OP_32_64(nand):
done = fold_nand(&ctx, op);
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (38 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-19 15:34 ` Alex Bennée
2021-10-07 19:54 ` [PATCH v2 41/48] tcg/optimize: Sink commutative operand swapping into fold functions Richard Henderson
` (9 subsequent siblings)
49 siblings, 1 reply; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Rename to fold_addsub2.
Use Int128 to implement the wider operation.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 64 +++++++++++++++++++++++++++++++++-----------------
1 file changed, 43 insertions(+), 21 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 0011ac31ec..5e662ad8f7 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -838,37 +838,59 @@ static bool fold_add(OptContext *ctx, TCGOp *op)
return false;
}
-static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add)
+static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
{
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
- uint32_t al = arg_info(op->args[2])->val;
- uint32_t ah = arg_info(op->args[3])->val;
- uint32_t bl = arg_info(op->args[4])->val;
- uint32_t bh = arg_info(op->args[5])->val;
- uint64_t a = ((uint64_t)ah << 32) | al;
- uint64_t b = ((uint64_t)bh << 32) | bl;
+ uint64_t al = arg_info(op->args[2])->val;
+ uint64_t ah = arg_info(op->args[3])->val;
+ uint64_t bl = arg_info(op->args[4])->val;
+ uint64_t bh = arg_info(op->args[5])->val;
TCGArg rl, rh;
- TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
+ TCGOp *op2;
- if (add) {
- a += b;
+ if (ctx->type == TCG_TYPE_I32) {
+ uint64_t a = deposit64(al, 32, 32, ah);
+ uint64_t b = deposit64(bl, 32, 32, bh);
+
+ if (add) {
+ a += b;
+ } else {
+ a -= b;
+ }
+
+ al = sextract64(a, 0, 32);
+ ah = sextract64(a, 32, 32);
} else {
- a -= b;
+ Int128 a = int128_make128(al, ah);
+ Int128 b = int128_make128(bl, bh);
+
+ if (add) {
+ a = int128_add(a, b);
+ } else {
+ a = int128_sub(a, b);
+ }
+
+ al = int128_getlo(a);
+ ah = int128_gethi(a);
}
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(ctx, op, rl, (int32_t)a);
- tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(a >> 32));
+
+ /* The proper opcode is supplied by tcg_opt_gen_mov. */
+ op2 = tcg_op_insert_before(ctx->tcg, op, 0);
+
+ tcg_opt_gen_movi(ctx, op, rl, al);
+ tcg_opt_gen_movi(ctx, op2, rh, ah);
return true;
}
return false;
}
-static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
+static bool fold_add2(OptContext *ctx, TCGOp *op)
{
- return fold_addsub2_i32(ctx, op, true);
+ return fold_addsub2(ctx, op, true);
}
static bool fold_and(OptContext *ctx, TCGOp *op)
@@ -1707,9 +1729,9 @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
return false;
}
-static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
+static bool fold_sub2(OptContext *ctx, TCGOp *op)
{
- return fold_addsub2_i32(ctx, op, false);
+ return fold_addsub2(ctx, op, false);
}
static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
@@ -1855,8 +1877,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(add):
done = fold_add(&ctx, op);
break;
- case INDEX_op_add2_i32:
- done = fold_add2_i32(&ctx, op);
+ CASE_OP_32_64(add2):
+ done = fold_add2(&ctx, op);
break;
CASE_OP_32_64_VEC(and):
done = fold_and(&ctx, op);
@@ -1991,8 +2013,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(sub):
done = fold_sub(&ctx, op);
break;
- case INDEX_op_sub2_i32:
- done = fold_sub2_i32(&ctx, op);
+ CASE_OP_32_64(sub2):
+ done = fold_sub2(&ctx, op);
break;
CASE_OP_32_64_VEC(xor):
done = fold_xor(&ctx, op);
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 41/48] tcg/optimize: Sink commutative operand swapping into fold functions
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (39 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 42/48] tcg/optimize: Add more simplifications for orc Richard Henderson
` (8 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Most of these are handled by creating a fold_const2_commutative
to handle all of the binary operators. The rest were already
handled on a case-by-case basis in the switch, and have their
own fold function in which to place the call.
We now have only one major switch on TCGOpcode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 128 ++++++++++++++++++++++---------------------------
1 file changed, 56 insertions(+), 72 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 5e662ad8f7..ad94f246ff 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -695,6 +695,12 @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
return false;
}
+static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
+{
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
+ return fold_const2(ctx, op);
+}
+
static bool fold_masks(OptContext *ctx, TCGOp *op)
{
uint64_t a_mask = ctx->a_mask;
@@ -831,7 +837,7 @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op)
static bool fold_add(OptContext *ctx, TCGOp *op)
{
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xi_to_x(ctx, op, 0)) {
return true;
}
@@ -890,6 +896,9 @@ static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
static bool fold_add2(OptContext *ctx, TCGOp *op)
{
+ swap_commutative(op->args[0], &op->args[2], &op->args[4]);
+ swap_commutative(op->args[1], &op->args[3], &op->args[5]);
+
return fold_addsub2(ctx, op, true);
}
@@ -897,7 +906,7 @@ static bool fold_and(OptContext *ctx, TCGOp *op)
{
uint64_t z1, z2;
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xi_to_i(ctx, op, 0) ||
fold_xi_to_x(ctx, op, -1) ||
fold_xx_to_x(ctx, op)) {
@@ -949,8 +958,13 @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
static bool fold_brcond(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[2];
- int i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond);
+ int i;
+ if (swap_commutative(-1, &op->args[0], &op->args[1])) {
+ op->args[2] = cond = tcg_swap_cond(cond);
+ }
+
+ i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond);
if (i == 0) {
tcg_op_remove(ctx->tcg, op);
return true;
@@ -965,10 +979,14 @@ static bool fold_brcond(OptContext *ctx, TCGOp *op)
static bool fold_brcond2(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[4];
- int i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond);
TCGArg label = op->args[5];
- int inv = 0;
+ int i, inv = 0;
+ if (swap_commutative2(&op->args[0], &op->args[2])) {
+ op->args[4] = cond = tcg_swap_cond(cond);
+ }
+
+ i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond);
if (i == 0) {
goto do_brcond_false;
} else if (i > 0) {
@@ -1215,7 +1233,7 @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
static bool fold_eqv(OptContext *ctx, TCGOp *op)
{
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xi_to_x(ctx, op, -1) ||
fold_xi_to_not(ctx, op, 0)) {
return true;
@@ -1377,8 +1395,20 @@ static bool fold_mov(OptContext *ctx, TCGOp *op)
static bool fold_movcond(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[5];
- int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
+ int i;
+ if (swap_commutative(-1, &op->args[1], &op->args[2])) {
+ op->args[5] = cond = tcg_swap_cond(cond);
+ }
+ /*
+ * Canonicalize the "false" input reg to match the destination reg so
+ * that the tcg backend can implement a "move if true" operation.
+ */
+ if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
+ op->args[5] = cond = tcg_invert_cond(cond);
+ }
+
+ i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
if (i >= 0) {
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
}
@@ -1415,7 +1445,7 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
static bool fold_multiply(OptContext *ctx, TCGOp *op)
{
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xi_to_i(ctx, op, 0)) {
return true;
}
@@ -1424,6 +1454,8 @@ static bool fold_multiply(OptContext *ctx, TCGOp *op)
static bool fold_multiply2(OptContext *ctx, TCGOp *op)
{
+ swap_commutative(op->args[0], &op->args[2], &op->args[3]);
+
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
uint64_t a = arg_info(op->args[2])->val;
uint64_t b = arg_info(op->args[3])->val;
@@ -1467,7 +1499,7 @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op)
static bool fold_nand(OptContext *ctx, TCGOp *op)
{
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xi_to_not(ctx, op, -1)) {
return true;
}
@@ -1496,7 +1528,7 @@ static bool fold_neg(OptContext *ctx, TCGOp *op)
static bool fold_nor(OptContext *ctx, TCGOp *op)
{
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xi_to_not(ctx, op, 0)) {
return true;
}
@@ -1516,7 +1548,7 @@ static bool fold_not(OptContext *ctx, TCGOp *op)
static bool fold_or(OptContext *ctx, TCGOp *op)
{
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xi_to_x(ctx, op, 0) ||
fold_xx_to_x(ctx, op)) {
return true;
@@ -1562,8 +1594,13 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
static bool fold_setcond(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[3];
- int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
+ int i;
+ if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
+ op->args[3] = cond = tcg_swap_cond(cond);
+ }
+
+ i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
if (i >= 0) {
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
}
@@ -1575,9 +1612,13 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
static bool fold_setcond2(OptContext *ctx, TCGOp *op)
{
TCGCond cond = op->args[5];
- int i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond);
- int inv = 0;
+ int i, inv = 0;
+ if (swap_commutative2(&op->args[1], &op->args[3])) {
+ op->args[5] = cond = tcg_swap_cond(cond);
+ }
+
+ i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond);
if (i >= 0) {
goto do_setcond_const;
}
@@ -1755,7 +1796,7 @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
static bool fold_xor(OptContext *ctx, TCGOp *op)
{
- if (fold_const2(ctx, op) ||
+ if (fold_const2_commutative(ctx, op) ||
fold_xx_to_i(ctx, op, 0) ||
fold_xi_to_x(ctx, op, 0) ||
fold_xi_to_not(ctx, op, -1)) {
@@ -1808,63 +1849,6 @@ void tcg_optimize(TCGContext *s)
ctx.type = TCG_TYPE_I32;
}
- /* For commutative operations make constant second argument */
- switch (opc) {
- CASE_OP_32_64_VEC(add):
- CASE_OP_32_64_VEC(mul):
- CASE_OP_32_64_VEC(and):
- CASE_OP_32_64_VEC(or):
- CASE_OP_32_64_VEC(xor):
- CASE_OP_32_64(eqv):
- CASE_OP_32_64(nand):
- CASE_OP_32_64(nor):
- CASE_OP_32_64(muluh):
- CASE_OP_32_64(mulsh):
- swap_commutative(op->args[0], &op->args[1], &op->args[2]);
- break;
- CASE_OP_32_64(brcond):
- if (swap_commutative(-1, &op->args[0], &op->args[1])) {
- op->args[2] = tcg_swap_cond(op->args[2]);
- }
- break;
- CASE_OP_32_64(setcond):
- if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
- op->args[3] = tcg_swap_cond(op->args[3]);
- }
- break;
- CASE_OP_32_64(movcond):
- if (swap_commutative(-1, &op->args[1], &op->args[2])) {
- op->args[5] = tcg_swap_cond(op->args[5]);
- }
- /* For movcond, we canonicalize the "false" input reg to match
- the destination reg so that the tcg backend can implement
- a "move if true" operation. */
- if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
- op->args[5] = tcg_invert_cond(op->args[5]);
- }
- break;
- CASE_OP_32_64(add2):
- swap_commutative(op->args[0], &op->args[2], &op->args[4]);
- swap_commutative(op->args[1], &op->args[3], &op->args[5]);
- break;
- CASE_OP_32_64(mulu2):
- CASE_OP_32_64(muls2):
- swap_commutative(op->args[0], &op->args[2], &op->args[3]);
- break;
- case INDEX_op_brcond2_i32:
- if (swap_commutative2(&op->args[0], &op->args[2])) {
- op->args[4] = tcg_swap_cond(op->args[4]);
- }
- break;
- case INDEX_op_setcond2_i32:
- if (swap_commutative2(&op->args[1], &op->args[3])) {
- op->args[5] = tcg_swap_cond(op->args[5]);
- }
- break;
- default:
- break;
- }
-
/* Assume all bits affected, and no bits known zero. */
ctx.a_mask = -1;
ctx.z_mask = -1;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 42/48] tcg/optimize: Add more simplifications for orc
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (40 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 41/48] tcg/optimize: Sink commutative operand swapping into fold functions Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values Richard Henderson
` (7 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Two simplifications that were missing from before the split
to fold functions, and are now easy to provide.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index ad94f246ff..9c11f83a4a 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1562,6 +1562,8 @@ static bool fold_or(OptContext *ctx, TCGOp *op)
static bool fold_orc(OptContext *ctx, TCGOp *op)
{
if (fold_const2(ctx, op) ||
+ fold_xx_to_i(ctx, op, -1) ||
+ fold_xi_to_x(ctx, op, -1) ||
fold_xi_to_not(ctx, op, 0)) {
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (41 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 42/48] tcg/optimize: Add more simplifications for orc Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 44/48] tcg/optimize: Optimize sign extensions Richard Henderson
` (6 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
This "garbage" setting pre-dates the addition of the type
changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64,
and INDEX_op_extr{l,h}_i64_i32.
So now we have a definitive points at which to adjust z_mask
to eliminate such bits from the 32-bit operands.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 35 ++++++++++++++++-------------------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 9c11f83a4a..5ef41e2769 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -123,10 +123,6 @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts)
ti->is_const = true;
ti->val = ts->val;
ti->z_mask = ts->val;
- if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
- /* High bits of a 32-bit quantity are garbage. */
- ti->z_mask |= ~0xffffffffull;
- }
} else {
ti->is_const = false;
ti->z_mask = -1;
@@ -191,7 +187,6 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
TCGTemp *src_ts = arg_temp(src);
TempOptInfo *di;
TempOptInfo *si;
- uint64_t z_mask;
TCGOpcode new_op;
if (ts_are_copies(dst_ts, src_ts)) {
@@ -223,12 +218,7 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
op->args[0] = dst;
op->args[1] = src;
- z_mask = si->z_mask;
- if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
- /* High bits of the destination are now garbage. */
- z_mask |= ~0xffffffffull;
- }
- di->z_mask = z_mask;
+ di->z_mask = si->z_mask;
if (src_ts->type == dst_ts->type) {
TempOptInfo *ni = ts_info(si->next_copy);
@@ -246,9 +236,14 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
TCGArg dst, uint64_t val)
{
- /* Convert movi to mov with constant temp. */
- TCGTemp *tv = tcg_constant_internal(ctx->type, val);
+ TCGTemp *tv;
+ if (ctx->type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ /* Convert movi to mov with constant temp. */
+ tv = tcg_constant_internal(ctx->type, val);
init_ts_info(ctx, tv);
return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
}
@@ -707,14 +702,16 @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
uint64_t z_mask = ctx->z_mask;
/*
- * 32-bit ops generate 32-bit results. For the result is zero test
- * below, we can ignore high bits, but for further optimizations we
- * need to record that the high bits contain garbage.
+ * 32-bit ops generate 32-bit results, which for the purpose of
+ * simplifying tcg are sign-extended. Certainly that's how we
+ * represent our constants elsewhere. Note that the bits will
+ * be reset properly for a 64-bit value when encountering the
+ * type changing opcodes.
*/
if (ctx->type == TCG_TYPE_I32) {
- ctx->z_mask |= MAKE_64BIT_MASK(32, 32);
- a_mask &= MAKE_64BIT_MASK(0, 32);
- z_mask &= MAKE_64BIT_MASK(0, 32);
+ a_mask = (int32_t)a_mask;
+ z_mask = (int32_t)z_mask;
+ ctx->z_mask = z_mask;
}
if (z_mask == 0) {
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 44/48] tcg/optimize: Optimize sign extensions
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (42 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 45/48] tcg/optimize: Propagate sign info for logical operations Richard Henderson
` (5 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
Certain targets, like riscv, produce signed 32-bit results.
This can lead to lots of redundant extensions as values are
manipulated.
Begin by tracking only the obvious sign-extensions, and
converting them to simple copies when possible.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 129 ++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 105 insertions(+), 24 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 5ef41e2769..06b178aa4a 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -42,6 +42,7 @@ typedef struct TempOptInfo {
TCGTemp *next_copy;
uint64_t val;
uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
+ uint64_t s_mask; /* a left-aligned mask of clrsb(value) bits. */
} TempOptInfo;
typedef struct OptContext {
@@ -52,9 +53,37 @@ typedef struct OptContext {
/* In flight values from optimization. */
uint64_t a_mask; /* mask bit is 0 iff value identical to first input */
uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */
+ uint64_t s_mask; /* mask of clrsb(value) bits */
TCGType type;
} OptContext;
+/* Calculate the smask for a specific value. */
+static uint64_t smask_from_value(uint64_t value)
+{
+ int rep = clrsb64(value);
+ return ~(~0ull >> rep);
+}
+
+/*
+ * Calculate the smask for a given set of known-zeros.
+ * If there are lots of zeros on the left, we can consider the remainder
+ * an unsigned field, and thus the corresponding signed field is one bit
+ * larger.
+ */
+static uint64_t smask_from_zmask(uint64_t zmask)
+{
+ /*
+ * Only the 0 bits are significant for zmask, thus the msb itself
+ * must be zero, else we have no sign information.
+ */
+ int rep = clz64(zmask);
+ if (rep == 0) {
+ return 0;
+ }
+ rep -= 1;
+ return ~(~0ull >> rep);
+}
+
static inline TempOptInfo *ts_info(TCGTemp *ts)
{
return ts->state_ptr;
@@ -93,6 +122,7 @@ static void reset_ts(TCGTemp *ts)
ti->prev_copy = ts;
ti->is_const = false;
ti->z_mask = -1;
+ ti->s_mask = 0;
}
static void reset_temp(TCGArg arg)
@@ -123,9 +153,11 @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts)
ti->is_const = true;
ti->val = ts->val;
ti->z_mask = ts->val;
+ ti->s_mask = smask_from_value(ts->val);
} else {
ti->is_const = false;
ti->z_mask = -1;
+ ti->s_mask = 0;
}
}
@@ -219,6 +251,7 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
op->args[1] = src;
di->z_mask = si->z_mask;
+ di->s_mask = si->s_mask;
if (src_ts->type == dst_ts->type) {
TempOptInfo *ni = ts_info(si->next_copy);
@@ -644,13 +677,15 @@ static void finish_folding(OptContext *ctx, TCGOp *op)
nb_oargs = def->nb_oargs;
for (i = 0; i < nb_oargs; i++) {
- reset_temp(op->args[i]);
+ TCGTemp *ts = arg_temp(op->args[i]);
+ reset_ts(ts);
/*
- * Save the corresponding known-zero bits mask for the
+ * Save the corresponding known-zero/sign bits mask for the
* first output argument (only one supported so far).
*/
if (i == 0) {
- arg_info(op->args[i])->z_mask = ctx->z_mask;
+ ts_info(ts)->z_mask = ctx->z_mask;
+ ts_info(ts)->s_mask = ctx->s_mask;
}
}
}
@@ -700,6 +735,7 @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
{
uint64_t a_mask = ctx->a_mask;
uint64_t z_mask = ctx->z_mask;
+ uint64_t s_mask = ctx->s_mask;
/*
* 32-bit ops generate 32-bit results, which for the purpose of
@@ -711,7 +747,9 @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
if (ctx->type == TCG_TYPE_I32) {
a_mask = (int32_t)a_mask;
z_mask = (int32_t)z_mask;
+ s_mask |= MAKE_64BIT_MASK(32, 32);
ctx->z_mask = z_mask;
+ ctx->s_mask = s_mask;
}
if (z_mask == 0) {
@@ -1059,7 +1097,7 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
static bool fold_bswap(OptContext *ctx, TCGOp *op)
{
- uint64_t z_mask, sign;
+ uint64_t z_mask, s_mask, sign;
if (arg_is_const(op->args[1])) {
uint64_t t = arg_info(op->args[1])->val;
@@ -1069,6 +1107,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
}
z_mask = arg_info(op->args[1])->z_mask;
+
switch (op->opc) {
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
@@ -1087,6 +1126,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
default:
g_assert_not_reached();
}
+ s_mask = smask_from_zmask(z_mask);
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
case TCG_BSWAP_OZ:
@@ -1095,14 +1135,17 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
/* If the sign bit may be 1, force all the bits above to 1. */
if (z_mask & sign) {
z_mask |= sign;
+ s_mask = sign << 1;
}
break;
default:
/* The high bits are undefined: force all bits above the sign to 1. */
z_mask |= sign << 1;
+ s_mask = 0;
break;
}
ctx->z_mask = z_mask;
+ ctx->s_mask = s_mask;
return fold_masks(ctx, op);
}
@@ -1241,21 +1284,24 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
static bool fold_extract(OptContext *ctx, TCGOp *op)
{
uint64_t z_mask_old, z_mask;
+ int pos = op->args[2];
+ int len = op->args[3];
if (arg_is_const(op->args[1])) {
uint64_t t;
t = arg_info(op->args[1])->val;
- t = extract64(t, op->args[2], op->args[3]);
+ t = extract64(t, pos, len);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
z_mask_old = arg_info(op->args[1])->z_mask;
- z_mask = sextract64(z_mask_old, op->args[2], op->args[3]);
- if (op->args[2] == 0) {
+ z_mask = extract64(z_mask_old, pos, len);
+ if (pos == 0) {
ctx->a_mask = z_mask_old ^ z_mask;
}
ctx->z_mask = z_mask;
+ ctx->s_mask = smask_from_zmask(z_mask);
return fold_masks(ctx, op);
}
@@ -1281,14 +1327,16 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
static bool fold_exts(OptContext *ctx, TCGOp *op)
{
- uint64_t z_mask_old, z_mask, sign;
+ uint64_t s_mask_old, s_mask, z_mask, sign;
bool type_change = false;
if (fold_const1(ctx, op)) {
return true;
}
- z_mask_old = z_mask = arg_info(op->args[1])->z_mask;
+ z_mask = arg_info(op->args[1])->z_mask;
+ s_mask = arg_info(op->args[1])->s_mask;
+ s_mask_old = s_mask;
switch (op->opc) {
CASE_OP_32_64(ext8s):
@@ -1312,10 +1360,14 @@ static bool fold_exts(OptContext *ctx, TCGOp *op)
if (z_mask & sign) {
z_mask |= sign;
- } else if (!type_change) {
- ctx->a_mask = z_mask_old ^ z_mask;
}
+ s_mask |= sign << 1;
+
ctx->z_mask = z_mask;
+ ctx->s_mask = s_mask;
+ if (!type_change) {
+ ctx->a_mask = s_mask & ~s_mask_old;
+ }
return fold_masks(ctx, op);
}
@@ -1354,6 +1406,7 @@ static bool fold_extu(OptContext *ctx, TCGOp *op)
}
ctx->z_mask = z_mask;
+ ctx->s_mask = smask_from_zmask(z_mask);
if (!type_change) {
ctx->a_mask = z_mask_old ^ z_mask;
}
@@ -1574,8 +1627,12 @@ static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
MemOp mop = get_memop(oi);
int width = 8 << (mop & MO_SIZE);
- if (!(mop & MO_SIGN) && width < 64) {
- ctx->z_mask = MAKE_64BIT_MASK(0, width);
+ if (width < 64) {
+ ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width);
+ if (!(mop & MO_SIGN)) {
+ ctx->z_mask = MAKE_64BIT_MASK(0, width);
+ ctx->s_mask <<= 1;
+ }
}
/* Opcodes that touch guest memory stop the mb optimization. */
@@ -1685,23 +1742,31 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
static bool fold_sextract(OptContext *ctx, TCGOp *op)
{
- int64_t z_mask_old, z_mask;
+ uint64_t z_mask, s_mask, s_mask_old;
+ int pos = op->args[2];
+ int len = op->args[3];
if (arg_is_const(op->args[1])) {
uint64_t t;
t = arg_info(op->args[1])->val;
- t = sextract64(t, op->args[2], op->args[3]);
+ t = sextract64(t, pos, len);
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
}
- z_mask_old = arg_info(op->args[1])->z_mask;
- z_mask = sextract64(z_mask_old, op->args[2], op->args[3]);
- if (op->args[2] == 0 && z_mask >= 0) {
- ctx->a_mask = z_mask_old ^ z_mask;
- }
+ z_mask = arg_info(op->args[1])->z_mask;
+ z_mask = sextract64(z_mask, pos, len);
ctx->z_mask = z_mask;
+ s_mask_old = arg_info(op->args[1])->s_mask;
+ s_mask = sextract64(s_mask_old, pos, len);
+ s_mask |= MAKE_64BIT_MASK(len, 64 - len);
+ ctx->s_mask = s_mask;
+
+ if (pos == 0) {
+ ctx->a_mask = s_mask & ~s_mask_old;
+ }
+
return fold_masks(ctx, op);
}
@@ -1778,14 +1843,26 @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
{
/* We can't do any folding with a load, but we can record bits. */
switch (op->opc) {
+ CASE_OP_32_64(ld8s):
+ ctx->s_mask = MAKE_64BIT_MASK(8, 56);
+ break;
CASE_OP_32_64(ld8u):
- ctx->z_mask = 0xff;
+ ctx->z_mask = MAKE_64BIT_MASK(0, 8);
+ ctx->s_mask = MAKE_64BIT_MASK(9, 55);
+ break;
+ CASE_OP_32_64(ld16s):
+ ctx->s_mask = MAKE_64BIT_MASK(16, 48);
break;
CASE_OP_32_64(ld16u):
- ctx->z_mask = 0xffff;
+ ctx->z_mask = MAKE_64BIT_MASK(0, 16);
+ ctx->s_mask = MAKE_64BIT_MASK(17, 47);
+ break;
+ case INDEX_op_ld32s_i64:
+ ctx->s_mask = MAKE_64BIT_MASK(32, 32);
break;
case INDEX_op_ld32u_i64:
- ctx->z_mask = 0xffffffffu;
+ ctx->z_mask = MAKE_64BIT_MASK(0, 32);
+ ctx->s_mask = MAKE_64BIT_MASK(33, 31);
break;
default:
g_assert_not_reached();
@@ -1848,9 +1925,10 @@ void tcg_optimize(TCGContext *s)
ctx.type = TCG_TYPE_I32;
}
- /* Assume all bits affected, and no bits known zero. */
+ /* Assume all bits affected, no bits known zero, no sign reps. */
ctx.a_mask = -1;
ctx.z_mask = -1;
+ ctx.s_mask = 0;
/*
* Process each opcode.
@@ -1923,8 +2001,11 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extrh_i64_i32:
done = fold_extu(&ctx, op);
break;
+ CASE_OP_32_64(ld8s):
CASE_OP_32_64(ld8u):
+ CASE_OP_32_64(ld16s):
CASE_OP_32_64(ld16u):
+ case INDEX_op_ld32s_i64:
case INDEX_op_ld32u_i64:
done = fold_tcg_ld(&ctx, op);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 45/48] tcg/optimize: Propagate sign info for logical operations
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (43 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 44/48] tcg/optimize: Optimize sign extensions Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 46/48] tcg/optimize: Propagate sign info for setcond Richard Henderson
` (4 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Sign repetitions are perforce all identical, whether they are 1 or 0.
Bitwise operations preserve the relative quantity of the repetitions.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 06b178aa4a..71e97ccd99 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -952,6 +952,13 @@ static bool fold_and(OptContext *ctx, TCGOp *op)
z2 = arg_info(op->args[2])->z_mask;
ctx->z_mask = z1 & z2;
+ /*
+ * Sign repetitions are perforce all identical, whether they are 1 or 0.
+ * Bitwise operations preserve the relative quantity of the repetitions.
+ */
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
+
/*
* Known-zeros does not imply known-ones. Therefore unless
* arg2 is constant, we can't infer affected bits from it.
@@ -987,6 +994,8 @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
}
ctx->z_mask = z1;
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
return fold_masks(ctx, op);
}
@@ -1278,6 +1287,9 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
fold_xi_to_not(ctx, op, 0)) {
return true;
}
+
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
return false;
}
@@ -1465,6 +1477,8 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
ctx->z_mask = arg_info(op->args[3])->z_mask
| arg_info(op->args[4])->z_mask;
+ ctx->s_mask = arg_info(op->args[3])->s_mask
+ & arg_info(op->args[4])->s_mask;
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
uint64_t tv = arg_info(op->args[3])->val;
@@ -1553,6 +1567,9 @@ static bool fold_nand(OptContext *ctx, TCGOp *op)
fold_xi_to_not(ctx, op, -1)) {
return true;
}
+
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
return false;
}
@@ -1582,6 +1599,9 @@ static bool fold_nor(OptContext *ctx, TCGOp *op)
fold_xi_to_not(ctx, op, 0)) {
return true;
}
+
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
return false;
}
@@ -1591,6 +1611,8 @@ static bool fold_not(OptContext *ctx, TCGOp *op)
return true;
}
+ ctx->s_mask = arg_info(op->args[1])->s_mask;
+
/* Because of fold_to_not, we want to always return true, via finish. */
finish_folding(ctx, op);
return true;
@@ -1606,6 +1628,8 @@ static bool fold_or(OptContext *ctx, TCGOp *op)
ctx->z_mask = arg_info(op->args[1])->z_mask
| arg_info(op->args[2])->z_mask;
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
return fold_masks(ctx, op);
}
@@ -1617,6 +1641,9 @@ static bool fold_orc(OptContext *ctx, TCGOp *op)
fold_xi_to_not(ctx, op, 0)) {
return true;
}
+
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
return false;
}
@@ -1881,6 +1908,8 @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
ctx->z_mask = arg_info(op->args[1])->z_mask
| arg_info(op->args[2])->z_mask;
+ ctx->s_mask = arg_info(op->args[1])->s_mask
+ & arg_info(op->args[2])->s_mask;
return fold_masks(ctx, op);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 46/48] tcg/optimize: Propagate sign info for setcond
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (44 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 45/48] tcg/optimize: Propagate sign info for logical operations Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 47/48] tcg/optimize: Propagate sign info for bit counting Richard Henderson
` (3 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
The result is either 0 or 1, which means that we have
a 2 bit signed result, and thus 62 bits of sign.
For clarity, use the smask_from_zmask function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 71e97ccd99..1c106bfbc3 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1689,6 +1689,7 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
}
ctx->z_mask = 1;
+ ctx->s_mask = smask_from_zmask(1);
return false;
}
@@ -1761,6 +1762,7 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
}
ctx->z_mask = 1;
+ ctx->s_mask = smask_from_zmask(1);
return false;
do_setcond_const:
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 47/48] tcg/optimize: Propagate sign info for bit counting
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (45 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 46/48] tcg/optimize: Propagate sign info for setcond Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 48/48] tcg/optimize: Propagate sign info for shifting Richard Henderson
` (2 subsequent siblings)
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
The results are generally 6 bit unsigned values, though
the count leading and trailing bits may produce any value
for a zero input.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 1c106bfbc3..678e7c1983 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1216,6 +1216,7 @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
g_assert_not_reached();
}
ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask;
+ ctx->s_mask = smask_from_zmask(z_mask);
return false;
}
@@ -1236,6 +1237,7 @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op)
default:
g_assert_not_reached();
}
+ ctx->s_mask = smask_from_zmask(ctx->z_mask);
return false;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH v2 48/48] tcg/optimize: Propagate sign info for shifting
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (46 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 47/48] tcg/optimize: Propagate sign info for bit counting Richard Henderson
@ 2021-10-07 19:54 ` Richard Henderson
2021-10-15 23:41 ` [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
2021-10-20 16:13 ` Alex Bennée
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-07 19:54 UTC (permalink / raw)
To: qemu-devel
For constant shifts, we can simply shift the s_mask.
For variable shifts, we know that sar does not reduce
the s_mask, which helps for sequences like
ext32s_i64 t, in
sar_i64 t, t, v
ext32s_i64 out, t
allowing the final extend to be eliminated.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 47 insertions(+), 3 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 678e7c1983..92cfb644bf 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -84,6 +84,18 @@ static uint64_t smask_from_zmask(uint64_t zmask)
return ~(~0ull >> rep);
}
+/*
+ * Recreate a properly left-aligned smask after manipulation.
+ * Some bit-shuffling, particularly shifts and rotates, may
+ * retain sign bits on the left, but may scatter disconnected
+ * sign bits on the right. Retain only what remains to the left.
+ */
+static uint64_t smask_from_smask(int64_t smask)
+{
+ /* Only the 1 bits are significant for smask */
+ return smask_from_zmask(~smask);
+}
+
static inline TempOptInfo *ts_info(TCGTemp *ts)
{
return ts->state_ptr;
@@ -1803,18 +1815,50 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
static bool fold_shift(OptContext *ctx, TCGOp *op)
{
+ uint64_t s_mask, z_mask, sign;
+
if (fold_const2(ctx, op) ||
fold_ix_to_i(ctx, op, 0) ||
fold_xi_to_x(ctx, op, 0)) {
return true;
}
+ s_mask = arg_info(op->args[1])->s_mask;
+ z_mask = arg_info(op->args[1])->z_mask;
+
if (arg_is_const(op->args[2])) {
- ctx->z_mask = do_constant_folding(op->opc, ctx->type,
- arg_info(op->args[1])->z_mask,
- arg_info(op->args[2])->val);
+ int sh = arg_info(op->args[2])->val;
+
+ ctx->z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh);
+
+ s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh);
+ ctx->s_mask = smask_from_smask(s_mask);
+
return fold_masks(ctx, op);
}
+
+ switch (op->opc) {
+ CASE_OP_32_64(sar):
+ /*
+ * Arithmetic right shift will not reduce the number of
+ * input sign repetitions.
+ */
+ ctx->s_mask = s_mask;
+ break;
+ CASE_OP_32_64(shr):
+ /*
+ * If the sign bit is known zero, then logical right shift
+ * will not reduced the number of input sign repetitions.
+ */
+ sign = (s_mask & -s_mask) >> 1;
+ if (!(z_mask & sign)) {
+ ctx->s_mask = s_mask;
+ }
+ break;
+ default:
+ break;
+ }
+
return false;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* Re: [PATCH v2 00/48] tcg: optimize redundant sign extensions
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (47 preceding siblings ...)
2021-10-07 19:54 ` [PATCH v2 48/48] tcg/optimize: Propagate sign info for shifting Richard Henderson
@ 2021-10-15 23:41 ` Richard Henderson
2021-10-20 16:13 ` Alex Bennée
49 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-15 23:41 UTC (permalink / raw)
To: qemu-devel
Ping.
On 10/7/21 12:54 PM, Richard Henderson wrote:
> Currently, we have support for optimizing redundant zero extensions,
> which I think was done with x86 and aarch64 in mind, which zero-extend
> all 32-bit operations into the 64-bit register.
>
> But targets like Alpha, MIPS, and RISC-V do sign-extensions instead.
> The last 5 patches address this.
>
> But before that, split the quite massive tcg_optimize function.
>
> Changes for v2:
> * Rebase, adjusting MemOpIdx renaming.
> * Apply r-b and some feedback (f4bug).
>
>
> r~
>
>
> Richard Henderson (48):
> tcg/optimize: Rename "mask" to "z_mask"
> tcg/optimize: Split out OptContext
> tcg/optimize: Remove do_default label
> tcg/optimize: Change tcg_opt_gen_{mov,movi} interface
> tcg/optimize: Move prev_mb into OptContext
> tcg/optimize: Split out init_arguments
> tcg/optimize: Split out copy_propagate
> tcg/optimize: Split out fold_call
> tcg/optimize: Drop nb_oargs, nb_iargs locals
> tcg/optimize: Change fail return for do_constant_folding_cond*
> tcg/optimize: Return true from tcg_opt_gen_{mov,movi}
> tcg/optimize: Split out finish_folding
> tcg/optimize: Use a boolean to avoid a mass of continues
> tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}
> tcg/optimize: Split out fold_const{1,2}
> tcg/optimize: Split out fold_setcond2
> tcg/optimize: Split out fold_brcond2
> tcg/optimize: Split out fold_brcond
> tcg/optimize: Split out fold_setcond
> tcg/optimize: Split out fold_mulu2_i32
> tcg/optimize: Split out fold_addsub2_i32
> tcg/optimize: Split out fold_movcond
> tcg/optimize: Split out fold_extract2
> tcg/optimize: Split out fold_extract, fold_sextract
> tcg/optimize: Split out fold_deposit
> tcg/optimize: Split out fold_count_zeros
> tcg/optimize: Split out fold_bswap
> tcg/optimize: Split out fold_dup, fold_dup2
> tcg/optimize: Split out fold_mov
> tcg/optimize: Split out fold_xx_to_i
> tcg/optimize: Split out fold_xx_to_x
> tcg/optimize: Split out fold_xi_to_i
> tcg/optimize: Add type to OptContext
> tcg/optimize: Split out fold_to_not
> tcg/optimize: Split out fold_sub_to_neg
> tcg/optimize: Split out fold_xi_to_x
> tcg/optimize: Split out fold_ix_to_i
> tcg/optimize: Split out fold_masks
> tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies
> tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
> tcg/optimize: Sink commutative operand swapping into fold functions
> tcg/optimize: Add more simplifications for orc
> tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values
> tcg/optimize: Optimize sign extensions
> tcg/optimize: Propagate sign info for logical operations
> tcg/optimize: Propagate sign info for setcond
> tcg/optimize: Propagate sign info for bit counting
> tcg/optimize: Propagate sign info for shifting
>
> tcg/optimize.c | 2602 +++++++++++++++++++++++++++++-------------------
> 1 file changed, 1585 insertions(+), 1017 deletions(-)
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask"
2021-10-07 19:54 ` [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask" Richard Henderson
@ 2021-10-19 15:23 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Alex Bennée @ 2021-10-19 15:23 UTC (permalink / raw)
To: Richard Henderson; +Cc: Philippe Mathieu-Daudé, qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Prepare for tracking different masks by renaming this one.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 02/48] tcg/optimize: Split out OptContext
2021-10-07 19:54 ` [PATCH v2 02/48] tcg/optimize: Split out OptContext Richard Henderson
@ 2021-10-19 15:25 ` Alex Bennée
2021-10-19 15:37 ` Richard Henderson
2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 1 reply; 87+ messages in thread
From: Alex Bennée @ 2021-10-19 15:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Provide what will become a larger context for splitting
> the very large tcg_optimize function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 77 ++++++++++++++++++++++++++------------------------
> 1 file changed, 40 insertions(+), 37 deletions(-)
>
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 148e360fc6..b76991215e 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -44,6 +44,10 @@ typedef struct TempOptInfo {
> uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
> } TempOptInfo;
>
> +typedef struct OptContext {
> + TCGTempSet temps_used;
> +} OptContext;
> +
> static inline TempOptInfo *ts_info(TCGTemp *ts)
> {
> return ts->state_ptr;
> @@ -90,15 +94,15 @@ static void reset_temp(TCGArg arg)
> }
>
<snip>
> @@ -605,7 +609,7 @@ void tcg_optimize(TCGContext *s)
> {
> int nb_temps, nb_globals, i;
> TCGOp *op, *op_next, *prev_mb = NULL;
> - TCGTempSet temps_used;
> + OptContext ctx = {};
>
> /* Array VALS has an element for each temp.
> If this temp holds a constant then its value is kept in VALS' element.
> @@ -615,7 +619,6 @@ void tcg_optimize(TCGContext *s)
> nb_temps = s->nb_temps;
> nb_globals = s->nb_globals;
>
> - memset(&temps_used, 0, sizeof(temps_used));
Did you mean to drop this memset entirely given I see it being done
later on?
<snip>
> @@ -1302,7 +1305,7 @@ void tcg_optimize(TCGContext *s)
> op->args[1], op->args[2]);
> if (tmp != 2) {
> if (tmp) {
> - memset(&temps_used, 0, sizeof(temps_used));
> + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
> op->opc = INDEX_op_br;
> op->args[0] = op->args[3];
> } else {
Otherwise:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
2021-10-07 19:54 ` [PATCH v2 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops Richard Henderson
@ 2021-10-19 15:34 ` Alex Bennée
2021-10-19 16:01 ` Richard Henderson
0 siblings, 1 reply; 87+ messages in thread
From: Alex Bennée @ 2021-10-19 15:34 UTC (permalink / raw)
To: Richard Henderson; +Cc: Philippe Mathieu-Daudé, qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Rename to fold_addsub2.
> Use Int128 to implement the wider operation.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 64 +++++++++++++++++++++++++++++++++-----------------
> 1 file changed, 43 insertions(+), 21 deletions(-)
>
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 0011ac31ec..5e662ad8f7 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -838,37 +838,59 @@ static bool fold_add(OptContext *ctx, TCGOp *op)
> return false;
> }
>
> -static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add)
> +static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
> {
> if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
> arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
> - uint32_t al = arg_info(op->args[2])->val;
> - uint32_t ah = arg_info(op->args[3])->val;
> - uint32_t bl = arg_info(op->args[4])->val;
> - uint32_t bh = arg_info(op->args[5])->val;
> - uint64_t a = ((uint64_t)ah << 32) | al;
> - uint64_t b = ((uint64_t)bh << 32) | bl;
> + uint64_t al = arg_info(op->args[2])->val;
> + uint64_t ah = arg_info(op->args[3])->val;
> + uint64_t bl = arg_info(op->args[4])->val;
> + uint64_t bh = arg_info(op->args[5])->val;
> TCGArg rl, rh;
> - TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
> + TCGOp *op2;
>
> - if (add) {
> - a += b;
> + if (ctx->type == TCG_TYPE_I32) {
> + uint64_t a = deposit64(al, 32, 32, ah);
> + uint64_t b = deposit64(bl, 32, 32, bh);
> +
> + if (add) {
> + a += b;
> + } else {
> + a -= b;
> + }
> +
> + al = sextract64(a, 0, 32);
> + ah = sextract64(a, 32, 32);
> } else {
> - a -= b;
> + Int128 a = int128_make128(al, ah);
> + Int128 b = int128_make128(bl, bh);
This didn't find the Int128 support:
FAILED: libqemu-arm-linux-user.fa.p/tcg_optimize.c.o
cc -m64 -mcx16 -Ilibqemu-arm-linux-user.fa.p -I. -I../.. -Itarget/arm -I../../target/arm -I../../linux-user/host/x86_64 -Ilinux-user -I../../linux-user -Ilinux-user/arm -I../../linux-user/arm -Itrace -Iqapi -Iui -Iui/shader -I/usr/include/capstone -I/usr/include/glib-2.0 -I/usr/lib/x86_64-linux-gnu/glib-2.0/include -fdiagnostics-color=auto -Wall -Winvalid-pch -Werror -std=gnu11 -O2 -g -isystem /home/alex/lsrc/qemu.git/linux-headers -isystem linux-headers -iquote . -iquote /home/alex/lsrc/qemu.git -iquote /home/alex/lsrc/qemu.git/include -iquote /home/alex/lsrc/qemu.git/disas/libvixl -iquote /home/alex/lsrc/qemu.git/tcg/i386 -pthread -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wold-style-declaration -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wimplicit-fallthrough=2 -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-psabi -fstack-protector-strong -fPIE -isystem../../linux-headers -isystemlinux-headers -DNEED_CPU_H '-DCONFIG_TARGET="arm-linux-user-config-target.h"' '-DCONFIG_DEVICES="arm-linux-user-config-devices.h"' -MD -MQ libqemu-arm-linux-user.fa.p/tcg_optimize.c.o -MF libqemu-arm-linux-user.fa.p/tcg_optimize.c.o.d -o libqemu-arm-linux-user.fa.p/tcg_optimize.c.o -c ../../tcg/optimize.c
../../tcg/optimize.c: In function ‘fold_addsub2’:
../../tcg/optimize.c:865:13: error: unknown type name ‘Int128’
865 | Int128 a = int128_make128(al, ah);
| ^~~~~~
../../tcg/optimize.c:865:24: error: implicit declaration of function ‘int128_make128’ [-Werror=implicit-function-declaration]
865 | Int128 a = int128_make128(al, ah);
possibly we are just missing:
#include "qemu/int128.h"
?
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 02/48] tcg/optimize: Split out OptContext
2021-10-19 15:25 ` Alex Bennée
@ 2021-10-19 15:37 ` Richard Henderson
0 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-19 15:37 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel
On 10/19/21 8:25 AM, Alex Bennée wrote:
>> - TCGTempSet temps_used;
>> + OptContext ctx = {};
>>
>> /* Array VALS has an element for each temp.
>> If this temp holds a constant then its value is kept in VALS' element.
>> @@ -615,7 +619,6 @@ void tcg_optimize(TCGContext *s)
>> nb_temps = s->nb_temps;
>> nb_globals = s->nb_globals;
>>
>> - memset(&temps_used, 0, sizeof(temps_used));
>
> Did you mean to drop this memset entirely given I see it being done
> later on?
It went to the struct initialization above.
r~
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 03/48] tcg/optimize: Remove do_default label
2021-10-07 19:54 ` [PATCH v2 03/48] tcg/optimize: Remove do_default label Richard Henderson
@ 2021-10-19 15:37 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Alex Bennée @ 2021-10-19 15:37 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Break the final cleanup clause out of the main switch
> statement. When fully folding an opcode to mov/movi,
> use "continue" to process the next opcode, else break
> to fall into the final cleanup.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface
2021-10-07 19:54 ` [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface Richard Henderson
@ 2021-10-19 15:38 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Alex Bennée @ 2021-10-19 15:38 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Adjust the interface to take the OptContext parameter instead
> of TCGContext or both.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext
2021-10-07 19:54 ` [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext Richard Henderson
@ 2021-10-19 15:44 ` Alex Bennée
2021-10-19 15:59 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 1 reply; 87+ messages in thread
From: Alex Bennée @ 2021-10-19 15:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> This will expose the variable to subroutines that
> will be broken out of tcg_optimize.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 627a5b39f6..b875d76354 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -46,6 +46,7 @@ typedef struct TempOptInfo {
>
> typedef struct OptContext {
> TCGContext *tcg;
> + TCGOp *prev_mb;
> TCGTempSet temps_used;
> } OptContext;
>
> @@ -609,7 +610,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
> void tcg_optimize(TCGContext *s)
> {
> int nb_temps, nb_globals, i;
> - TCGOp *op, *op_next, *prev_mb = NULL;
> + TCGOp *op, *op_next;
> OptContext ctx = { .tcg = s };
Do we need to add .prev_mb = NULL to ensure the ctx doesn't start
corrupted or does the partial initialisation ensure the rest is zeroed
out?
Otherwise:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext
2021-10-19 15:44 ` Alex Bennée
@ 2021-10-19 15:59 ` Richard Henderson
0 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-19 15:59 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel
On 10/19/21 8:44 AM, Alex Bennée wrote:
>> @@ -609,7 +610,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
>> void tcg_optimize(TCGContext *s)
>> {
>> int nb_temps, nb_globals, i;
>> - TCGOp *op, *op_next, *prev_mb = NULL;
>> + TCGOp *op, *op_next;
>> OptContext ctx = { .tcg = s };
>
> Do we need to add .prev_mb = NULL to ensure the ctx doesn't start
> corrupted or does the partial initialisation ensure the rest is zeroed
> out?
All members not explicitly initialized are zeroed.
>
> Otherwise:
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
r~
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
2021-10-19 15:34 ` Alex Bennée
@ 2021-10-19 16:01 ` Richard Henderson
0 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-19 16:01 UTC (permalink / raw)
To: Alex Bennée; +Cc: Philippe Mathieu-Daudé, qemu-devel
On 10/19/21 8:34 AM, Alex Bennée wrote:
> ../../tcg/optimize.c: In function ‘fold_addsub2’:
> ../../tcg/optimize.c:865:13: error: unknown type name ‘Int128’
> 865 | Int128 a = int128_make128(al, ah);
> | ^~~~~~
> ../../tcg/optimize.c:865:24: error: implicit declaration of function ‘int128_make128’ [-Werror=implicit-function-declaration]
> 865 | Int128 a = int128_make128(al, ah);
>
>
> possibly we are just missing:
>
> #include "qemu/int128.h"
Ah, this patch set predates a cleanup to tcg_ldst.h.
Previously we included int128.h in tcg.h.
Will fix.
r~
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 06/48] tcg/optimize: Split out init_arguments
2021-10-07 19:54 ` [PATCH v2 06/48] tcg/optimize: Split out init_arguments Richard Henderson
@ 2021-10-19 16:13 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Alex Bennée @ 2021-10-19 16:13 UTC (permalink / raw)
To: Richard Henderson; +Cc: Philippe Mathieu-Daudé, qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> There was no real reason for calls to have separate code here.
> Unify init for calls vs non-calls using the call path, which
> handles TCG_CALL_DUMMY_ARG.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 07/48] tcg/optimize: Split out copy_propagate
2021-10-07 19:54 ` [PATCH v2 07/48] tcg/optimize: Split out copy_propagate Richard Henderson
@ 2021-10-20 16:01 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Alex Bennée @ 2021-10-20 16:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: Philippe Mathieu-Daudé, qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Continue splitting tcg_optimize.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 08/48] tcg/optimize: Split out fold_call
2021-10-07 19:54 ` [PATCH v2 08/48] tcg/optimize: Split out fold_call Richard Henderson
@ 2021-10-20 16:05 ` Alex Bennée
2021-10-21 2:04 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 1 reply; 87+ messages in thread
From: Alex Bennée @ 2021-10-20 16:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Calls are special in that they have a variable number
> of arguments, and need to be able to clobber globals.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 63 ++++++++++++++++++++++++++++++++------------------
> 1 file changed, 41 insertions(+), 22 deletions(-)
>
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index fad6f5de1f..74b9aa025a 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -624,10 +624,42 @@ static void copy_propagate(OptContext *ctx, TCGOp *op,
> }
> }
>
> +static bool fold_call(OptContext *ctx, TCGOp *op)
> +{
> + TCGContext *s = ctx->tcg;
> + int nb_oargs = TCGOP_CALLO(op);
> + int nb_iargs = TCGOP_CALLI(op);
> + int flags, i;
> +
> + init_arguments(ctx, op, nb_oargs + nb_iargs);
> + copy_propagate(ctx, op, nb_oargs, nb_iargs);
> +
> + /* If the function reads or writes globals, reset temp data. */
> + flags = tcg_call_flags(op);
> + if (!(flags & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
> + int nb_globals = s->nb_globals;
Aren't we missing a trick here?
If the helper is going to read global registers we need to ensure any
temps holding their data is written but we don't need to throw the
existing temps away if the helper is TCG_CALL_NO_WRITE_GLOBALS?
I guess we have to handle the case of temps that are about to get smahed
by the call though....
Otherwise:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 00/48] tcg: optimize redundant sign extensions
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
` (48 preceding siblings ...)
2021-10-15 23:41 ` [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
@ 2021-10-20 16:13 ` Alex Bennée
2021-10-20 23:50 ` Richard Henderson
49 siblings, 1 reply; 87+ messages in thread
From: Alex Bennée @ 2021-10-20 16:13 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Matt Borgerson
Richard Henderson <richard.henderson@linaro.org> writes:
> Currently, we have support for optimizing redundant zero extensions,
> which I think was done with x86 and aarch64 in mind, which zero-extend
> all 32-bit operations into the 64-bit register.
>
> But targets like Alpha, MIPS, and RISC-V do sign-extensions instead.
> The last 5 patches address this.
>
> But before that, split the quite massive tcg_optimize function.
BTW this reminded me of a discussion I was having on another thread:
Subject: Re: TCG Floating Point Support (Work in Progress)
Date: Fri, 01 Oct 2021 09:03:41 +0100
In-reply-to: <CADc=-s5wJ0cBv9r0rXaOk0Ys77Far7mgXq5B+y4KoNr937cC7A@mail.gmail.com>
Message-ID: <87y27d5ezt.fsf@linaro.org>
about a test harness of TCG. With the changes over the years are we any
closer to being able to lift the TCG code into a unit test so we can add
test cases that exercise and validate the optimiser decisions?
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals
2021-10-07 19:54 ` [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals Richard Henderson
@ 2021-10-20 16:17 ` Alex Bennée
2021-10-21 2:09 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 1 reply; 87+ messages in thread
From: Alex Bennée @ 2021-10-20 16:17 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> Rather than try to keep these up-to-date across folding,
> re-read nb_oargs at the end, after re-reading the opcode.
>
> A couple of asserts need dropping, but that will take care
> of itself as we split the function further.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 14 ++++----------
> 1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 74b9aa025a..77cdffaaef 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
<snip>
>
> @@ -1579,6 +1572,7 @@ void tcg_optimize(TCGContext *s)
> if (def->flags & TCG_OPF_BB_END) {
> memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
> } else {
> + int nb_oargs = def->nb_oargs;
> for (i = 0; i < nb_oargs; i++) {
nit: couldn't you just do for (i = 0; i < deb->nb_oargs; i++) or is that
too much for the compiler to wrap it's head around?
Either way:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask"
2021-10-07 19:54 ` [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask" Richard Henderson
2021-10-19 15:23 ` Alex Bennée
@ 2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Richard Henderson <richard.henderson@linaro.org>
> Prepare for tracking different masks by renaming this one.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 142 +++++++++++++++++++++++++------------------------
> 1 file changed, 72 insertions(+), 70 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 02/48] tcg/optimize: Split out OptContext
2021-10-07 19:54 ` [PATCH v2 02/48] tcg/optimize: Split out OptContext Richard Henderson
2021-10-19 15:25 ` Alex Bennée
@ 2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Provide what will become a larger context for splitting the very large
> tcg_optimize function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 77 ++++++++++++++++++++++++++------------------------
> 1 file changed, 40 insertions(+), 37 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 03/48] tcg/optimize: Remove do_default label
2021-10-07 19:54 ` [PATCH v2 03/48] tcg/optimize: Remove do_default label Richard Henderson
2021-10-19 15:37 ` Alex Bennée
@ 2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Break the final cleanup clause out of the main switch statement. When fully
> folding an opcode to mov/movi, use "continue" to process the next opcode, else
> break to fall into the final cleanup.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 190 ++++++++++++++++++++++++-------------------------
> 1 file changed, 94 insertions(+), 96 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface
2021-10-07 19:54 ` [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface Richard Henderson
2021-10-19 15:38 ` Alex Bennée
@ 2021-10-20 22:26 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Adjust the interface to take the OptContext parameter instead of TCGContext or
> both.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 67 +++++++++++++++++++++++++-------------------------
> 1 file changed, 34 insertions(+), 33 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext
2021-10-07 19:54 ` [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext Richard Henderson
2021-10-19 15:44 ` Alex Bennée
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> This will expose the variable to subroutines that will be broken out of
> tcg_optimize.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 06/48] tcg/optimize: Split out init_arguments
2021-10-07 19:54 ` [PATCH v2 06/48] tcg/optimize: Split out init_arguments Richard Henderson
2021-10-19 16:13 ` Alex Bennée
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Richard Henderson <richard.henderson@linaro.org>
> There was no real reason for calls to have separate code here.
> Unify init for calls vs non-calls using the call path, which handles
> TCG_CALL_DUMMY_ARG.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 25 +++++++++++--------------
> 1 file changed, 11 insertions(+), 14 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 07/48] tcg/optimize: Split out copy_propagate
2021-10-07 19:54 ` [PATCH v2 07/48] tcg/optimize: Split out copy_propagate Richard Henderson
2021-10-20 16:01 ` Alex Bennée
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Richard Henderson <richard.henderson@linaro.org>
> Continue splitting tcg_optimize.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 22 ++++++++++++++--------
> 1 file changed, 14 insertions(+), 8 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 08/48] tcg/optimize: Split out fold_call
2021-10-07 19:54 ` [PATCH v2 08/48] tcg/optimize: Split out fold_call Richard Henderson
2021-10-20 16:05 ` Alex Bennée
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Calls are special in that they have a variable number of arguments, and need to
> be able to clobber globals.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 63 ++++++++++++++++++++++++++++++++------------------
> 1 file changed, 41 insertions(+), 22 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals
2021-10-07 19:54 ` [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals Richard Henderson
2021-10-20 16:17 ` Alex Bennée
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
1 sibling, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Rather than try to keep these up-to-date across folding, re-read nb_oargs at the
> end, after re-reading the opcode.
>
> A couple of asserts need dropping, but that will take care of itself as we split the
> function further.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 14 ++++----------
> 1 file changed, 4 insertions(+), 10 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 10/48] tcg/optimize: Change fail return for do_constant_folding_cond*
2021-10-07 19:54 ` [PATCH v2 10/48] tcg/optimize: Change fail return for do_constant_folding_cond* Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Return -1 instead of 2 for failure.
> This us to use comparisons against 0 for all cases.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 145 +++++++++++++++++++++++++------------------------
> 1 file changed, 74 insertions(+), 71 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi}
2021-10-07 19:54 ` [PATCH v2 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi} Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Richard Henderson <richard.henderson@linaro.org>
> This will allow callers to tail call to these functions and return true indicating
> processing complete.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 12/48] tcg/optimize: Split out finish_folding
2021-10-07 19:54 ` [PATCH v2 12/48] tcg/optimize: Split out finish_folding Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Copy z_mask into OptContext, for writeback to the first output within the new
> function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 49 +++++++++++++++++++++++++++++++++----------------
> 1 file changed, 33 insertions(+), 16 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 13/48] tcg/optimize: Use a boolean to avoid a mass of continues
2021-10-07 19:54 ` [PATCH v2 13/48] tcg/optimize: Use a boolean to avoid a mass of continues Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}
2021-10-07 19:54 ` [PATCH v2 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st} Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> This puts the separate mb optimization into the same framework as the others.
> While fold_qemu_{ld,st} are currently identical, that won't last as more code
> gets moved.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 89 +++++++++++++++++++++++++++++---------------------
> 1 file changed, 51 insertions(+), 38 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 15/48] tcg/optimize: Split out fold_const{1,2}
2021-10-07 19:54 ` [PATCH v2 15/48] tcg/optimize: Split out fold_const{1,2} Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Split out a whole bunch of placeholder functions, which are currently identical.
> That won't last as more code gets moved.
>
> Use CASE_32_64_VEC for some logical operators that previously missed the
> addition of vectors.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 254 +++++++++++++++++++++++++++++++++++++++----------
> 1 file changed, 202 insertions(+), 52 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 16/48] tcg/optimize: Split out fold_setcond2
2021-10-07 19:54 ` [PATCH v2 16/48] tcg/optimize: Split out fold_setcond2 Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Reduce some code duplication by folding the NE and EQ cases.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 145 ++++++++++++++++++++++++-------------------------
> 1 file changed, 72 insertions(+), 73 deletions(-)
> - i = do_constant_folding_cond(INDEX_op_setcond_i32,
> - op->args[2], op->args[4],
> - TCG_COND_EQ);
> - if (i == 0) {
> - goto do_setcond_high;
^^^^^^^^^
> - } else if (i < 0) {
> - break;
> - }
I'll just note that the goto in the old code above is wrong - it should be a goto to do_setcond_const. But you fixed that in your new implementation.
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2
2021-10-07 19:54 ` [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2 Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-21 2:32 ` Richard Henderson
0 siblings, 1 reply; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Reduce some code duplication by folding the NE and EQ cases.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 161 +++++++++++++++++++++++++------------------------
> 1 file changed, 83 insertions(+), 78 deletions(-)
> + case TCG_COND_NE:
> + inv = 1;
> + QEMU_FALLTHROUGH;
> + case TCG_COND_EQ:
> + /*
> + * Simplify EQ/NE comparisons where one of the pairs
> + * can be simplified.
> + */
> + i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0],
> + op->args[2], cond);
> + switch (i ^ inv) {
> + case 0:
> + goto do_brcond_false;
I believe this should go to do_brcond_true when cond==TCG_COND_NE.
> + i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1],
> + op->args[3], cond);
> + switch (i ^ inv) {
> + case 0:
> + goto do_brcond_false;
Same here.
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 18/48] tcg/optimize: Split out fold_brcond
2021-10-07 19:54 ` [PATCH v2 18/48] tcg/optimize: Split out fold_brcond Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 33 +++++++++++++++++++--------------
> 1 file changed, 19 insertions(+), 14 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* RE: [PATCH v2 19/48] tcg/optimize: Split out fold_setcond
2021-10-07 19:54 ` [PATCH v2 19/48] tcg/optimize: Split out fold_setcond Richard Henderson
@ 2021-10-20 22:27 ` Luis Fernando Fujita Pires
0 siblings, 0 replies; 87+ messages in thread
From: Luis Fernando Fujita Pires @ 2021-10-20 22:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 23 ++++++++++++++---------
> 1 file changed, 14 insertions(+), 9 deletions(-)
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 00/48] tcg: optimize redundant sign extensions
2021-10-20 16:13 ` Alex Bennée
@ 2021-10-20 23:50 ` Richard Henderson
0 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-20 23:50 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel, Matt Borgerson
On 10/20/21 9:13 AM, Alex Bennée wrote:
>
> Richard Henderson <richard.henderson@linaro.org> writes:
>
>> Currently, we have support for optimizing redundant zero extensions,
>> which I think was done with x86 and aarch64 in mind, which zero-extend
>> all 32-bit operations into the 64-bit register.
>>
>> But targets like Alpha, MIPS, and RISC-V do sign-extensions instead.
>> The last 5 patches address this.
>>
>> But before that, split the quite massive tcg_optimize function.
>
> BTW this reminded me of a discussion I was having on another thread:
>
> Subject: Re: TCG Floating Point Support (Work in Progress)
> Date: Fri, 01 Oct 2021 09:03:41 +0100
> In-reply-to: <CADc=-s5wJ0cBv9r0rXaOk0Ys77Far7mgXq5B+y4KoNr937cC7A@mail.gmail.com>
> Message-ID: <87y27d5ezt.fsf@linaro.org>
>
> about a test harness of TCG. With the changes over the years are we any
> closer to being able to lift the TCG code into a unit test so we can add
> test cases that exercise and validate the optimiser decisions?
Nope.
I'm not even sure true unit testing is worthwhile.
It would require inventing a "tcg front end", parser, etc.
I could imagine, perhaps, something in which we input real asm and look at the optimized
opcode dump. E.g. for x86_64,
_start:
mov %eax, %ebx
mov %ebx, %ecx
hlt
should contain only one ext32u_i64 opcode.
r~
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 08/48] tcg/optimize: Split out fold_call
2021-10-20 16:05 ` Alex Bennée
@ 2021-10-21 2:04 ` Richard Henderson
0 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-21 2:04 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel
On 10/20/21 9:05 AM, Alex Bennée wrote:
>
> Richard Henderson <richard.henderson@linaro.org> writes:
>
>> Calls are special in that they have a variable number
>> of arguments, and need to be able to clobber globals.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> tcg/optimize.c | 63 ++++++++++++++++++++++++++++++++------------------
>> 1 file changed, 41 insertions(+), 22 deletions(-)
>>
>> diff --git a/tcg/optimize.c b/tcg/optimize.c
>> index fad6f5de1f..74b9aa025a 100644
>> --- a/tcg/optimize.c
>> +++ b/tcg/optimize.c
>> @@ -624,10 +624,42 @@ static void copy_propagate(OptContext *ctx, TCGOp *op,
>> }
>> }
>>
>> +static bool fold_call(OptContext *ctx, TCGOp *op)
>> +{
>> + TCGContext *s = ctx->tcg;
>> + int nb_oargs = TCGOP_CALLO(op);
>> + int nb_iargs = TCGOP_CALLI(op);
>> + int flags, i;
>> +
>> + init_arguments(ctx, op, nb_oargs + nb_iargs);
>> + copy_propagate(ctx, op, nb_oargs, nb_iargs);
>> +
>> + /* If the function reads or writes globals, reset temp data. */
>> + flags = tcg_call_flags(op);
>> + if (!(flags & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
>> + int nb_globals = s->nb_globals;
>
> Aren't we missing a trick here?
>
> If the helper is going to read global registers we need to ensure any
> temps holding their data is written but we don't need to throw the
> existing temps away if the helper is TCG_CALL_NO_WRITE_GLOBALS?
Hmm, if NO_WRITE_GLOBALS, then yes, we should be able to preserve the information about
the current contents. There must be some quirk, though; I just don't recall what it is.
This patch preserves existing behaviour.
r~
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals
2021-10-20 16:17 ` Alex Bennée
@ 2021-10-21 2:09 ` Richard Henderson
0 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-21 2:09 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel
On 10/20/21 9:17 AM, Alex Bennée wrote:
>> + int nb_oargs = def->nb_oargs;
>> for (i = 0; i < nb_oargs; i++) {
>
> nit: couldn't you just do for (i = 0; i < deb->nb_oargs; i++) or is that
> too much for the compiler to wrap it's head around?'
That leaves the compiler with non-invariant loop bounds, because memory clobbering inside
the loop.
r~
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2
2021-10-20 22:27 ` Luis Fernando Fujita Pires
@ 2021-10-21 2:32 ` Richard Henderson
0 siblings, 0 replies; 87+ messages in thread
From: Richard Henderson @ 2021-10-21 2:32 UTC (permalink / raw)
To: Luis Fernando Fujita Pires, qemu-devel
On 10/20/21 3:27 PM, Luis Fernando Fujita Pires wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>> Reduce some code duplication by folding the NE and EQ cases.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> tcg/optimize.c | 161 +++++++++++++++++++++++++------------------------
>> 1 file changed, 83 insertions(+), 78 deletions(-)
>
>> + case TCG_COND_NE:
>> + inv = 1;
>> + QEMU_FALLTHROUGH;
>> + case TCG_COND_EQ:
>> + /*
>> + * Simplify EQ/NE comparisons where one of the pairs
>> + * can be simplified.
>> + */
>> + i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0],
>> + op->args[2], cond);
>> + switch (i ^ inv) {
>> + case 0:
>> + goto do_brcond_false;
>
> I believe this should go to do_brcond_true when cond==TCG_COND_NE.
Good eyes, thanks.
This needs to be more like setcond2, with do_brcond_const.
r~
^ permalink raw reply [flat|nested] 87+ messages in thread
end of thread, other threads:[~2021-10-21 2:33 UTC | newest]
Thread overview: 87+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-07 19:54 [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
2021-10-07 19:54 ` [PATCH v2 01/48] tcg/optimize: Rename "mask" to "z_mask" Richard Henderson
2021-10-19 15:23 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 02/48] tcg/optimize: Split out OptContext Richard Henderson
2021-10-19 15:25 ` Alex Bennée
2021-10-19 15:37 ` Richard Henderson
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 03/48] tcg/optimize: Remove do_default label Richard Henderson
2021-10-19 15:37 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 04/48] tcg/optimize: Change tcg_opt_gen_{mov, movi} interface Richard Henderson
2021-10-19 15:38 ` Alex Bennée
2021-10-20 22:26 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 05/48] tcg/optimize: Move prev_mb into OptContext Richard Henderson
2021-10-19 15:44 ` Alex Bennée
2021-10-19 15:59 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 06/48] tcg/optimize: Split out init_arguments Richard Henderson
2021-10-19 16:13 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 07/48] tcg/optimize: Split out copy_propagate Richard Henderson
2021-10-20 16:01 ` Alex Bennée
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 08/48] tcg/optimize: Split out fold_call Richard Henderson
2021-10-20 16:05 ` Alex Bennée
2021-10-21 2:04 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 09/48] tcg/optimize: Drop nb_oargs, nb_iargs locals Richard Henderson
2021-10-20 16:17 ` Alex Bennée
2021-10-21 2:09 ` Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 10/48] tcg/optimize: Change fail return for do_constant_folding_cond* Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov, movi} Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 12/48] tcg/optimize: Split out finish_folding Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 13/48] tcg/optimize: Use a boolean to avoid a mass of continues Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st} Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 15/48] tcg/optimize: Split out fold_const{1,2} Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 16/48] tcg/optimize: Split out fold_setcond2 Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 17/48] tcg/optimize: Split out fold_brcond2 Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-21 2:32 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 18/48] tcg/optimize: Split out fold_brcond Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 19/48] tcg/optimize: Split out fold_setcond Richard Henderson
2021-10-20 22:27 ` Luis Fernando Fujita Pires
2021-10-07 19:54 ` [PATCH v2 20/48] tcg/optimize: Split out fold_mulu2_i32 Richard Henderson
2021-10-07 19:54 ` [PATCH v2 21/48] tcg/optimize: Split out fold_addsub2_i32 Richard Henderson
2021-10-07 19:54 ` [PATCH v2 22/48] tcg/optimize: Split out fold_movcond Richard Henderson
2021-10-07 19:54 ` [PATCH v2 23/48] tcg/optimize: Split out fold_extract2 Richard Henderson
2021-10-07 19:54 ` [PATCH v2 24/48] tcg/optimize: Split out fold_extract, fold_sextract Richard Henderson
2021-10-07 19:54 ` [PATCH v2 25/48] tcg/optimize: Split out fold_deposit Richard Henderson
2021-10-07 19:54 ` [PATCH v2 26/48] tcg/optimize: Split out fold_count_zeros Richard Henderson
2021-10-07 19:54 ` [PATCH v2 27/48] tcg/optimize: Split out fold_bswap Richard Henderson
2021-10-07 19:54 ` [PATCH v2 28/48] tcg/optimize: Split out fold_dup, fold_dup2 Richard Henderson
2021-10-07 19:54 ` [PATCH v2 29/48] tcg/optimize: Split out fold_mov Richard Henderson
2021-10-07 19:54 ` [PATCH v2 30/48] tcg/optimize: Split out fold_xx_to_i Richard Henderson
2021-10-07 19:54 ` [PATCH v2 31/48] tcg/optimize: Split out fold_xx_to_x Richard Henderson
2021-10-07 19:54 ` [PATCH v2 32/48] tcg/optimize: Split out fold_xi_to_i Richard Henderson
2021-10-07 19:54 ` [PATCH v2 33/48] tcg/optimize: Add type to OptContext Richard Henderson
2021-10-07 19:54 ` [PATCH v2 34/48] tcg/optimize: Split out fold_to_not Richard Henderson
2021-10-07 19:54 ` [PATCH v2 35/48] tcg/optimize: Split out fold_sub_to_neg Richard Henderson
2021-10-07 19:54 ` [PATCH v2 36/48] tcg/optimize: Split out fold_xi_to_x Richard Henderson
2021-10-07 19:54 ` [PATCH v2 37/48] tcg/optimize: Split out fold_ix_to_i Richard Henderson
2021-10-07 19:54 ` [PATCH v2 38/48] tcg/optimize: Split out fold_masks Richard Henderson
2021-10-07 19:54 ` [PATCH v2 39/48] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies Richard Henderson
2021-10-07 19:54 ` [PATCH v2 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops Richard Henderson
2021-10-19 15:34 ` Alex Bennée
2021-10-19 16:01 ` Richard Henderson
2021-10-07 19:54 ` [PATCH v2 41/48] tcg/optimize: Sink commutative operand swapping into fold functions Richard Henderson
2021-10-07 19:54 ` [PATCH v2 42/48] tcg/optimize: Add more simplifications for orc Richard Henderson
2021-10-07 19:54 ` [PATCH v2 43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values Richard Henderson
2021-10-07 19:54 ` [PATCH v2 44/48] tcg/optimize: Optimize sign extensions Richard Henderson
2021-10-07 19:54 ` [PATCH v2 45/48] tcg/optimize: Propagate sign info for logical operations Richard Henderson
2021-10-07 19:54 ` [PATCH v2 46/48] tcg/optimize: Propagate sign info for setcond Richard Henderson
2021-10-07 19:54 ` [PATCH v2 47/48] tcg/optimize: Propagate sign info for bit counting Richard Henderson
2021-10-07 19:54 ` [PATCH v2 48/48] tcg/optimize: Propagate sign info for shifting Richard Henderson
2021-10-15 23:41 ` [PATCH v2 00/48] tcg: optimize redundant sign extensions Richard Henderson
2021-10-20 16:13 ` Alex Bennée
2021-10-20 23:50 ` Richard Henderson
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