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Sun, 26 Mar 2023 21:26:46 -0700 (PDT) Received: from localhost ([203.221.180.225]) by smtp.gmail.com with ESMTPSA id 22-20020aa79256000000b00582f222f088sm17814740pfp.47.2023.03.26.21.26.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 26 Mar 2023 21:26:45 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 27 Mar 2023 14:26:42 +1000 Message-Id: Cc: Subject: Re: [PATCH 4/6] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward From: "Nicholas Piggin" To: "Fabiano Rosas" , X-Mailer: aerc 0.13.0 References: <20230323022237.1807512-1-npiggin@gmail.com> <20230323022237.1807512-4-npiggin@gmail.com> <87wn36feuy.fsf@suse.de> In-Reply-To: <87wn36feuy.fsf@suse.de> Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Mar 24, 2023 at 11:39 PM AEST, Fabiano Rosas wrote: > Nicholas Piggin writes: > > > This optional behavior was removed from the ISA in v3.0, see > > Summary of Changes preface: > > > > Data Storage Interrupt Status Register for Alignment Interrupt: > > Simplifies the Alignment interrupt by remov- ing the Data Storage > > Interrupt Status Register (DSISR) from the set of registers modified > > by the Alignment interrupt. > > > > Signed-off-by: Nicholas Piggin > > --- > > target/ppc/excp_helper.c | 23 ++++++++++++++++------- > > 1 file changed, 16 insertions(+), 7 deletions(-) > > > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > > index 5f0e363363..c8b8eca3b1 100644 > > --- a/target/ppc/excp_helper.c > > +++ b/target/ppc/excp_helper.c > > @@ -1456,13 +1456,22 @@ static void powerpc_excp_books(PowerPCCPU *cpu,= int excp) > > break; > > } > > case POWERPC_EXCP_ALIGN: /* Alignment exception = */ > > - /* Get rS/rD and rA from faulting opcode */ > > - /* > > - * Note: the opcode fields will not be set properly for a > > - * direct store load/store, but nobody cares as nobody > > - * actually uses direct store segments. > > - */ > > - env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; > > + switch (env->excp_model) { > > Slightly better would be to check on (env->insn_flags2 & PPC2_ISA300). > We were trying to phase out the usage of "exception models" wherever > possible in favor of specific feature/isa level flags. Oh good point, thanks for catching that. Will fix and resend the series (I've done the same thing in a few other places too). Thanks, Nick