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Mon, 19 Aug 2019 14:40:35 +0000 From: Aleksandar Rikalo To: Aleksandar Markovic , "qemu-devel@nongnu.org" Thread-Topic: [EXTERNAL][PATCH v8 10/37] target/mips: Style improvements in helper.c Thread-Index: AQHVVobVuR9CiX5/8kuStKYomEeCr6cCiuRU Date: Mon, 19 Aug 2019 14:40:35 +0000 Message-ID: References: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com>, <1566216496-17375-11-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1566216496-17375-11-git-send-email-aleksandar.markovic@rt-rk.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=arikalo@wavecomp.com; x-originating-ip: [82.117.201.26] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9dc9de1c-b4fc-4a97-1cbc-08d724b33215 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: [Qemu-devel] [EXTERNAL][PATCH v8 10/37] target/mips: Style improvements in helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "philmd@redhat.com" , Aleksandar Markovic Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" > From: Aleksandar Markovic > Sent: Monday, August 19, 2019 2:07 PM > To: qemu-devel@nongnu.org > Cc: philmd@redhat.com ; Aleksandar Markovic ; Aleksandar Rikalo > Subject: [EXTERNAL][PATCH v8 10/37] target/mips: Style improvements in he= lper.c > > From: Aleksandar Markovic > > Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. > > Signed-off-by: Aleksandar Markovic > --- > target/mips/helper.c | 98 ++++++++++++++++++++++++++++++++--------------= ------ > 1 file changed, 60 insertions(+), 38 deletions(-) > > diff --git a/target/mips/helper.c b/target/mips/helper.c > index 6e583d3..d7a2c77 100644 > --- a/target/mips/helper.c > +++ b/target/mips/helper.c > @@ -39,8 +39,8 @@ enum { > #if !defined(CONFIG_USER_ONLY) > > /* no MMU emulation */ > -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, > - target_ulong address, int rw, int access_type) > +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, > + target_ulong address, int rw, int access_type) > { > *physical =3D address; > *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; > @@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *ph= ysical, int *prot, > } > > /* fixed mapping MMU emulation */ > -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *pro= t, > - target_ulong address, int rw, int access_type= ) > +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot= , > + target_ulong address, int rw, int access_type) > { > if (address <=3D (int32_t)0x7FFFFFFFUL) { > - if (!(env->CP0_Status & (1 << CP0St_ERL))) > + if (!(env->CP0_Status & (1 << CP0St_ERL))) { > *physical =3D address + 0x40000000UL; > - else > + } else { > *physical =3D address; > - } else if (address <=3D (int32_t)0xBFFFFFFFUL) > + } > + } else if (address <=3D (int32_t)0xBFFFFFFFUL) { > *physical =3D address & 0x1FFFFFFF; > - else > + } else { > *physical =3D address; > + } > > *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; > return TLBRET_MATCH; > } > > /* MIPS32/MIPS64 R4000-style MMU emulation */ > -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, > - target_ulong address, int rw, int access_type) > +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, > + target_ulong address, int rw, int access_type) > { > uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; > uint32_t MMID =3D env->CP0_MemoryMapID; > @@ -105,8 +107,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physi= cal, int *prot, > if (rw !=3D MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { > *physical =3D tlb->PFN[n] | (address & (mask >> 1)); > *prot =3D PAGE_READ; > - if (n ? tlb->D1 : tlb->D0) > + if (n ? tlb->D1 : tlb->D0) { > *prot |=3D PAGE_WRITE; > + } > if (!(n ? tlb->XI1 : tlb->XI0)) { > *prot |=3D PAGE_EXEC; > } > @@ -136,9 +139,10 @@ static int is_seg_am_mapped(unsigned int am, bool eu= , int mmu_idx) > int32_t adetlb_mask; > > switch (mmu_idx) { > - case 3 /* ERL */: > - /* If EU is set, always unmapped */ > + case 3: > + /* ERL */ > if (eu) { > + /* If EU is set, always unmapped */ > return 0; > } > /* fall through */ > @@ -210,7 +214,7 @@ static int get_segctl_physical_address(CPUMIPSState *= env, hwaddr *physical, > pa & ~(hwaddr)segmask); > } > > -static int get_physical_address (CPUMIPSState *env, hwaddr *physical, > +static int get_physical_address(CPUMIPSState *env, hwaddr *physical, > int *prot, target_ulong real_address, > int rw, int access_type, int mmu_idx) > { > @@ -265,7 +269,8 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, > } else if (address < 0x4000000000000000ULL) { > /* xuseg */ > if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { > - ret =3D env->tlb->map_address(env, physical, prot, real_addr= ess, rw, access_type); > + ret =3D env->tlb->map_address(env, physical, prot, real_addr= ess, rw, > + access_type); > } else { > ret =3D TLBRET_BADADDR; > } > @@ -273,7 +278,8 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, > /* xsseg */ > if ((supervisor_mode || kernel_mode) && > SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { > - ret =3D env->tlb->map_address(env, physical, prot, real_addr= ess, rw, access_type); > + ret =3D env->tlb->map_address(env, physical, prot, real_addr= ess, rw, > + access_type); > } else { > ret =3D TLBRET_BADADDR; > } > @@ -313,7 +319,8 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, > /* xkseg */ > if (kernel_mode && KX && > address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { > - ret =3D env->tlb->map_address(env, physical, prot, real_addr= ess, rw, access_type); > + ret =3D env->tlb->map_address(env, physical, prot, real_addr= ess, rw, > + access_type); > } else { > ret =3D TLBRET_BADADDR; > } > @@ -669,7 +676,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t= *vaddr, > } > > static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int= rw, > - int mmu_idx) > + int mmu_idx) > { > int gdw =3D (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; > int udw =3D (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; > @@ -951,7 +958,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, > } > > #ifndef CONFIG_USER_ONLY > -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong addres= s, int rw) > +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong addres= s, > + int rw) > { > hwaddr physical; > int prot; > @@ -1011,7 +1019,7 @@ static const char * const excp_names[EXCP_LAST + 1]= =3D { > }; > #endif > > -target_ulong exception_resume_pc (CPUMIPSState *env) > +target_ulong exception_resume_pc(CPUMIPSState *env) > { > target_ulong bad_pc; > target_ulong isa_mode; > @@ -1019,8 +1027,10 @@ target_ulong exception_resume_pc (CPUMIPSState *en= v) > isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); > bad_pc =3D env->active_tc.PC | isa_mode; > if (env->hflags & MIPS_HFLAG_BMASK) { > - /* If the exception was raised from a delay slot, come back to > - the jump. */ > + /* > + * If the exception was raised from a delay slot, come back to > + * the jump. > + */ > bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); > } > > @@ -1102,10 +1112,12 @@ void mips_cpu_do_interrupt(CPUState *cs) > switch (cs->exception_index) { > case EXCP_DSS: > env->CP0_Debug |=3D 1 << CP0DB_DSS; > - /* Debug single step cannot be raised inside a delay slot and > - resume will always occur on the next instruction > - (but we assume the pc has always been updated during > - code translation). */ > + /* > + * Debug single step cannot be raised inside a delay slot and > + * resume will always occur on the next instruction > + * (but we assume the pc has always been updated during > + * code translation). > + */ > env->CP0_DEPC =3D env->active_tc.PC | !!(env->hflags & MIPS_HFLA= G_M16); > goto enter_debug_mode; > case EXCP_DINT: > @@ -1117,7 +1129,8 @@ void mips_cpu_do_interrupt(CPUState *cs) > case EXCP_DBp: > env->CP0_Debug |=3D 1 << CP0DB_DBp; > /* Setup DExcCode - SDBBP instruction */ > - env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | = 9 << CP0DB_DEC; > + env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | > + (9 << CP0DB_DEC); > goto set_DEPC; > case EXCP_DDBS: > env->CP0_Debug |=3D 1 << CP0DB_DDBS; > @@ -1138,8 +1151,9 @@ void mips_cpu_do_interrupt(CPUState *cs) > env->hflags |=3D MIPS_HFLAG_DM | MIPS_HFLAG_CP0; > env->hflags &=3D ~(MIPS_HFLAG_KSU); > /* EJTAG probe trap enable is not implemented... */ > - if (!(env->CP0_Status & (1 << CP0St_EXL))) > + if (!(env->CP0_Status & (1 << CP0St_EXL))) { > env->CP0_Cause &=3D ~(1U << CP0Ca_BD); > + } > env->active_tc.PC =3D env->exception_base + 0x480; > set_hflags_for_handler(env); > break; > @@ -1165,8 +1179,9 @@ void mips_cpu_do_interrupt(CPUState *cs) > } > env->hflags |=3D MIPS_HFLAG_CP0; > env->hflags &=3D ~(MIPS_HFLAG_KSU); > - if (!(env->CP0_Status & (1 << CP0St_EXL))) > + if (!(env->CP0_Status & (1 << CP0St_EXL))) { > env->CP0_Cause &=3D ~(1U << CP0Ca_BD); > + } > env->active_tc.PC =3D env->exception_base; > set_hflags_for_handler(env); > break; > @@ -1182,12 +1197,16 @@ void mips_cpu_do_interrupt(CPUState *cs) > uint32_t pending =3D (env->CP0_Cause & CP0Ca_IP_mask) >>= CP0Ca_IP; > > if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { > - /* For VEIC mode, the external interrupt controller = feeds > - * the vector through the CP0Cause IP lines. */ > + /* > + * For VEIC mode, the external interrupt controller = feeds > + * the vector through the CP0Cause IP lines. > + */ > vector =3D pending; > } else { > - /* Vectored Interrupts > - * Mask with Status.IM7-IM0 to get enabled interrupt= s. */ > + /* > + * Vectored Interrupts > + * Mask with Status.IM7-IM0 to get enabled interrupt= s. > + */ > pending &=3D (env->CP0_Status >> CP0St_IM) & 0xff; > /* Find the highest-priority interrupt. */ > while (pending >>=3D 1) { > @@ -1360,7 +1379,8 @@ void mips_cpu_do_interrupt(CPUState *cs) > > env->active_tc.PC +=3D offset; > set_hflags_for_handler(env); > - env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cau= se << CP0Ca_EC); > + env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | > + (cause << CP0Ca_EC); > break; > default: > abort(); > @@ -1396,7 +1416,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int inte= rrupt_request) > } > > #if !defined(CONFIG_USER_ONLY) > -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) > +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) > { > CPUState *cs =3D env_cpu(env); > r4k_tlb_t *tlb; > @@ -1421,9 +1441,11 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int id= x, int use_extra) > } > > if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { > - /* For tlbwr, we can shadow the discarded entry into > - a new (fake) TLB entry, as long as the guest can not > - tell that it's there. */ > + /* > + * For tlbwr, we can shadow the discarded entry into > + * a new (fake) TLB entry, as long as the guest can not > + * tell that it's there. > + */ > env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] =3D *tlb; > env->tlb->tlb_in_use++; > return; > -- > 2.7.4 > Reviewed-by: Aleksandar Rikalo