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Tue, 29 Oct 2019 10:07:19 +0000 From: Sai Pavan Boddu To: Francisco Iglesias Subject: RE: [PATCH v5] ssi: xilinx_spips: Skip spi bus update for a few register writes Thread-Topic: [PATCH v5] ssi: xilinx_spips: Skip spi bus update for a few register writes Thread-Index: AQHVizaJS7lTJ/WsXEWclDEjOUkX3qdxaPAA Date: Tue, 29 Oct 2019 10:07:19 +0000 Message-ID: References: <1571981531-27498-1-git-send-email-sai.pavan.boddu@xilinx.com> <20191025131713.pthu3ihbuhllzszd@fralle-msi> In-Reply-To: <20191025131713.pthu3ihbuhllzszd@fralle-msi> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=saipava@xilinx.com; x-originating-ip: [149.199.50.133] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: d06c236f-e256-425f-5507-08d75c57c89b x-ms-traffictypediagnostic: MN2PR02MB6333:|MN2PR02MB6333: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:139; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: d06c236f-e256-425f-5507-08d75c57c89b X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 10:07:19.1439 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SIrn3QGgBmm/tjG92ccfl3ucwtNFqoV2EH8BVcz4aMwUlXa1dqeRNY99znYN0Ahz9xILTJlmIRzikMzYALsjeQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6333 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.69.53 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Edgar Iglesias , Alistair Francis , "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Thanks Francisco & Alistair for review. I have sent V6 with Review tags and commit message fix. Regards, Sai Pavan > -----Original Message----- > From: Francisco Iglesias > Sent: Friday, October 25, 2019 6:47 PM > To: Sai Pavan Boddu > Cc: Alistair Francis ; Peter Maydell > ; Edgar Iglesias ; qemu- > devel@nongnu.org > Subject: Re: [PATCH v5] ssi: xilinx_spips: Skip spi bus update for a few = register > writes >=20 > Hi Sai, >=20 > On [2019 Oct 25] Fri 11:02:11, Sai Pavan Boddu wrote: > > A few configuration register writes need not update the spi bus state, > > so just return after register write. >=20 > s/register write/the register write/ >=20 > > > > Signed-off-by: Sai Pavan Boddu >=20 > After above change: >=20 > Reviewed-by: Francisco Iglesias > Tested-by: Francisco Iglesias >=20 > Best regards, > Francisco Iglesias >=20 > > --- > > > > Changes for V2: > > Just skip update of spips cs and fifos > > Update commit message accordingly > > Changes for V4: > > Avoid checking for zynqmp qspi > > Skip spi bus update for few of the registers Changes for V4: > > Move the register list to existing switch case above. > > Change for V5: > > Fixed Commit message. > > > > hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++---- > > 1 file changed, 18 insertions(+), 4 deletions(-) > > > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index > > a309c71..0d6c2e1 100644 > > --- a/hw/ssi/xilinx_spips.c > > +++ b/hw/ssi/xilinx_spips.c > > @@ -109,6 +109,7 @@ > > #define R_GPIO (0x30 / 4) > > #define R_LPBK_DLY_ADJ (0x38 / 4) > > #define R_LPBK_DLY_ADJ_RESET (0x33) > > +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) > > #define R_TXD1 (0x80 / 4) > > #define R_TXD2 (0x84 / 4) > > #define R_TXD3 (0x88 / 4) > > @@ -139,6 +140,8 @@ > > #define R_LQSPI_STS (0xA4 / 4) > > #define LQSPI_STS_WR_RECVD (1 << 1) > > > > +#define R_DUMMY_CYCLE_EN (0xC8 / 4) > > +#define R_ECO (0xF8 / 4) > > #define R_MOD_ID (0xFC / 4) > > > > #define R_GQSPI_SELECT (0x144 / 4) > > @@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque, > > hwaddr addr, { > > int mask =3D ~0; > > XilinxSPIPS *s =3D opaque; > > + bool try_flush =3D true; > > > > DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr, > (unsigned)value); > > addr >>=3D 2; > > @@ -1019,13 +1023,23 @@ static void xilinx_spips_write(void *opaque, > hwaddr addr, > > tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, > > s->regs[R_CONFIG] & R_CONFIG_ENDIAN); > > goto no_reg_update; > > + /* Skip SPI bus update for below registers writes */ > > + case R_GPIO: > > + case R_LPBK_DLY_ADJ: > > + case R_IOU_TAPDLY_BYPASS: > > + case R_DUMMY_CYCLE_EN: > > + case R_ECO: > > + try_flush =3D false; > > + break; > > } > > s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); > > no_reg_update: > > - xilinx_spips_update_cs_lines(s); > > - xilinx_spips_check_flush(s); > > - xilinx_spips_update_cs_lines(s); > > - xilinx_spips_update_ixr(s); > > + if (try_flush) { > > + xilinx_spips_update_cs_lines(s); > > + xilinx_spips_check_flush(s); > > + xilinx_spips_update_cs_lines(s); > > + xilinx_spips_update_ixr(s); > > + } > > } > > > > static const MemoryRegionOps spips_ops =3D { > > -- > > 2.7.4 > >