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Fri, 4 Jun 2021 08:29:25 +0000 From: "ishii.shuuichir@fujitsu.com" To: 'Richard Henderson' , Peter Maydell Subject: RE: [RFC] Adding the A64FX's HPC funtions. Thread-Topic: [RFC] Adding the A64FX's HPC funtions. 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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: fujitsu.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYCPR01MB6160.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e2f354ff-8c95-4f04-02f3-08d92732dcff X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Jun 2021 08:29:25.8337 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a19f121d-81e1-4858-a9d8-736e267fd4c7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9jEqmPdjHI/hDfpndPh7733R4IdNV6GXwNA8fZN1KOOjX4az3LDvA9RXbU4hI2bR4SIwS9MhmmKeIhuQfWTSSsufvroJA5+GyiZOz4F9GFQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYAPR01MB5642 Received-SPF: pass client-ip=216.71.158.65; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa20.fujitsucc.c3s2.iphmx.com X-Spam_action: no action Received-SPF: pass client-ip=96.88.95.61; envelope-from=mlmgr@proulx.com; helo=havoc.proulx.com X-Spam_score_int: 20 X-Spam_score: 2.0 X-Spam_bar: ++ X-Spam_report: (2.0 / 5.0 requ) BAYES_50=0.8, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, HK_RANDOM_ENVFROM=0.998, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, Richard. > Well, Peter disagreed with having them enabled by default in -cpu max, so= we > might need at least one extra property. I see no reason to have three > properties -- one property a64fx-hpc should be sufficient. But we might = not > want any command-line properties, see below... I understood. > For comparison, in the Arm Cortex-A76 manual, > https://developer.arm.com/documentation/100798/0301/ > section B2.4 "AArch64 registers by functional group", there is a concise > listing of all of the system registers and their reset values. Thank you for the information. > The most important of these for QEMU to create '-cpu a64fx' are the > ID_AA64{ISAR,MMFR,PFR} and MIDR values. These values determine all of > the > standard architectural features, The values of ID_AA64{ISAR,MMFR,PFR} and MIDR are not listed in the specifi= cations published at this time.=20 Of course, they are listed in the A64FX specification document managed with= in Fujitsu, but we cannot tell how far these setting values can be disclosed=20 without checking with the A64FX specification staff within Fujitsu. In order to make the "-cpu a64fx" option, the above problem needs to be sol= ved. When the necessary register specifications are released, it will be possible to implement the "-cpu a64fx" option, but I thought it would be better to implement the "-cpu max" option as a fi= rst step, partly because I don't know when it will be possible to solve this problem. However, MIDR.partnum can be found in "CPU implementer" of /proc/cpuinfo, and CPU FEAT is partially displayed in kernel boot messages. It is true that there are some values that are publicly known in a sense fr= om Linux on A64FX-equipped machines, even if they are not listed in the existing public A64FX|specification. To what extent ID_AA64{ISAR,MMFR,PFR} can be made public needs to be confir= med=20 with the A64FX specification staff. As for the MIDR register values, I think they can be implemented in QEMU as publicly known information that = can be recognized by the OS. When considering implementation with the "-cpu a64fx" option, is there any problem to define only the value of MIDR, using a temporary value for now until the information of ID_AA64{ISAR,MMFR,= PFR} can be disclosed? > Peter is suggesting that if full support for -cpu a64fx apart from the hp= c > extensions is close, then we shouldn't implementing a property for -cpu m= ax, > but only implement -cpu a64fx. (Because how does the OS detect the hpc > feature, apart from the MIDR value?) The HPC extension is implemented as an impldef register as a unique feature= for HPC in the A64FX processor. the existence of the HPC extension would be determined from the fact that M= IDR.partnum is A64FX (0x46). Best regards. > -----Original Message----- > From: Richard Henderson > Sent: Friday, June 4, 2021 5:08 AM > To: Ishii, Shuuichirou/=1B$B@P0f=1B(B =1B$B<~0lO:=1B(B ; Peter > Maydell > Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org > Subject: Re: [RFC] Adding the A64FX's HPC funtions. >=20 > On 6/3/21 1:17 AM, ishii.shuuichir@fujitsu.com wrote: > > Hi, Richard. > > > > Thank you for your comment. > > > >> My first thought is that -cpu max can simply enable the extensions, > >> without extra flags. The max cpu has all of the features that we can > >> enable, and as I see it this is just one more. > > > > Let me confirm a few things about the above comment. > > Does it mean that I don't need to explicitly enable individual > > extensions such as a64fx-hpc-sec, a64fx-hpc-hwpf, and a64fx-hpc-hwb, > > since all extensions can be enabled by specifying -cpu max? >=20 > Well, Peter disagreed with having them enabled by default in -cpu max, so= we > might need at least one extra property. I see no reason to have three > properties -- one property a64fx-hpc should be sufficient. But we might = not > want any command-line properties, see below... >=20 > > > >> The microarchitectural document provided does not list all of the syst= em > >> register reset values for the A64FX, and I would be surprised if there= were > an > >> architectural id register that specified a non-standard extension like= this. > >> Thus I would expect to add ARM_FEATURE_A64FX with which to enable > these > >> extensions in helper.c. > > > > As you said, > > some of the published specifications do not describe the reset values o= f the > registers. > > I would like to implement this in QEMU by referring to a real machine w= ith > A64FX. >=20 > I presume there exists some documentation for this somewhere, though > possibly > only internal to Fujitsu so far. >=20 > For comparison, in the Arm Cortex-A76 manual, > https://developer.arm.com/documentation/100798/0301/ > section B2.4 "AArch64 registers by functional group", there is a concise > listing of all of the system registers and their reset values. >=20 > The most important of these for QEMU to create '-cpu a64fx' are the > ID_AA64{ISAR,MMFR,PFR} and MIDR values. These values determine all of > the > standard architectural features, and from them we can tell what QEMU may = (or > may not) be missing for proper emulation of the cpu. For comparison, loo= k at > aarch64_a72_initfn in target/arm/cpu64.c. >=20 > Peter is suggesting that if full support for -cpu a64fx apart from the hp= c > extensions is close, then we shouldn't implementing a property for -cpu m= ax, > but only implement -cpu a64fx. (Because how does the OS detect the hpc > feature, apart from the MIDR value?) >=20 >=20 > r~