From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67011C433E0 for ; Fri, 12 Mar 2021 01:25:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7AE3264F6D for ; Fri, 12 Mar 2021 01:25:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7AE3264F6D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lKWYZ-0002Ps-Fr for qemu-devel@archiver.kernel.org; Thu, 11 Mar 2021 20:25:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKWXH-0001wg-AB; Thu, 11 Mar 2021 20:24:15 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:52443 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lKWXE-0000uj-KQ; Thu, 11 Mar 2021 20:24:15 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4DxSlD3WLCz9sW4; Fri, 12 Mar 2021 12:24:08 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1615512248; bh=hlFk5kiyLpMF793LoHbPsPwJ4htztunCmXarUYrHbcE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=myxO1XMLGd5t3/mR4BUk5m8nEboKurSuN0lfUx6kEBuqMhkWJ5SQHNlwBKc8q22eu THkW9e2qnI1ATPnJUD7mz5q9lqdVv3gQdKXGnC9BRawJzMrEmfs8dGo9LmhovYEEIG jRlEZRZgb+ErcZpl5DegwHn/BaGdzuCD/LWaBZok= Date: Fri, 12 Mar 2021 12:20:33 +1100 From: David Gibson To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs Message-ID: References: <8cf90aad5a9fce1a20cbf49e4ef71c51ba04faed.1615345138.git.balaton@eik.bme.hu> <3c1c3d6b-44e4-66e1-366e-e40245589f7e@amsat.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="eDrVpvzkDffO7C4+" Content-Disposition: inline In-Reply-To: <3c1c3d6b-44e4-66e1-366e-e40245589f7e@amsat.org> Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --eDrVpvzkDffO7C4+ Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 12, 2021 at 12:47:54AM +0100, Philippe Mathieu-Daud=E9 wrote: > ping for review? I'm not sure who you're asking for a review from. >=20 > On 3/10/21 3:58 AM, BALATON Zoltan wrote: > > In VIA super south bridge the io ranges of superio components > > (parallel and serial ports and FDC) can be controlled by superio > > config registers to set their base address and enable/disable them. > > This is not easy to implement in QEMU because ISA emulation is only > > designed to set io base address once on creating the device and io > > ranges are registered at creation and cannot easily be disabled or > > moved later. > >=20 > > In this patch we hack around that but only for serial ports because > > those have a single io range at port base that's relatively easy to > > handle and it's what guests actually use and set address different > > than the default. > >=20 > > We do not attempt to handle controlling the parallel and FDC regions > > because those have multiple io ranges so handling them would be messy > > and guests either don't change their deafult or don't care. We could > > even get away with disabling and not emulating them, but since they > > are already there, this patch leaves them mapped at their default > > address just in case this could be useful for a guest in the future. > >=20 > > Signed-off-by: BALATON Zoltan > > --- > > hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++++++++-- > > 1 file changed, 82 insertions(+), 2 deletions(-) > >=20 > > diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c > > index 05d084f698..a3353ec5db 100644 > > --- a/hw/isa/vt82c686.c > > +++ b/hw/isa/vt82c686.c > > @@ -252,8 +252,24 @@ static const TypeInfo vt8231_pm_info =3D { > > typedef struct SuperIOConfig { > > uint8_t regs[0x100]; > > MemoryRegion io; > > + ISASuperIODevice *superio; > > + MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS]; > > } SuperIOConfig; > > =20 > > +static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent, > > + int offs) > > +{ > > + MemoryRegion *subregion, *mr =3D NULL; > > + > > + QTAILQ_FOREACH(subregion, &parent->subregions, subregions_link) { > > + if (subregion->addr =3D=3D offs) { > > + mr =3D subregion; > > + break; > > + } > > + } > > + return mr; > > +} > > + > > static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, > > unsigned size) > > { > > @@ -279,7 +295,53 @@ static void superio_cfg_write(void *opaque, hwaddr= addr, uint64_t data, > > case 0xfd ... 0xff: > > /* ignore write to read only registers */ > > return; > > - /* case 0xe6 ... 0xe8: Should set base port of parallel and serial= */ > > + case 0xe2: > > + { > > + data &=3D 0x1f; > > + if (data & BIT(2)) { /* Serial port 1 enable */ > > + ISADevice *dev =3D sc->superio->serial[0]; > > + if (!memory_region_is_mapped(sc->serial_io[0])) { > > + memory_region_add_subregion(isa_address_space_io(dev), > > + dev->ioport_id, sc->serial= _io[0]); > > + } > > + } else { > > + MemoryRegion *io =3D isa_address_space_io(sc->superio->ser= ial[0]); > > + if (memory_region_is_mapped(sc->serial_io[0])) { > > + memory_region_del_subregion(io, sc->serial_io[0]); > > + } > > + } > > + if (data & BIT(3)) { /* Serial port 2 enable */ > > + ISADevice *dev =3D sc->superio->serial[1]; > > + if (!memory_region_is_mapped(sc->serial_io[1])) { > > + memory_region_add_subregion(isa_address_space_io(dev), > > + dev->ioport_id, sc->serial= _io[1]); > > + } > > + } else { > > + MemoryRegion *io =3D isa_address_space_io(sc->superio->ser= ial[1]); > > + if (memory_region_is_mapped(sc->serial_io[1])) { > > + memory_region_del_subregion(io, sc->serial_io[1]); > > + } > > + } > > + break; > > + } > > + case 0xe7: /* Serial port 1 io base address */ > > + { > > + data &=3D 0xfe; > > + sc->superio->serial[0]->ioport_id =3D data << 2; > > + if (memory_region_is_mapped(sc->serial_io[0])) { > > + memory_region_set_address(sc->serial_io[0], data << 2); > > + } > > + break; > > + } > > + case 0xe8: /* Serial port 2 io base address */ > > + { > > + data &=3D 0xfe; > > + sc->superio->serial[1]->ioport_id =3D data << 2; > > + if (memory_region_is_mapped(sc->serial_io[1])) { > > + memory_region_set_address(sc->serial_io[1], data << 2); > > + } > > + break; > > + } > > default: > > qemu_log_mask(LOG_UNIMP, > > "via_superio_cfg: unimplemented register 0x%x\n"= , idx); > > @@ -385,6 +447,7 @@ static void vt82c686b_realize(PCIDevice *d, Error *= *errp) > > DeviceState *dev =3D DEVICE(d); > > ISABus *isa_bus; > > qemu_irq *isa_irq; > > + ISASuperIOClass *ic; > > int i; > > =20 > > qdev_init_gpio_out(dev, &s->cpu_intr, 1); > > @@ -394,7 +457,9 @@ static void vt82c686b_realize(PCIDevice *d, Error *= *errp) > > isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); > > i8254_pit_init(isa_bus, 0x40, 0, NULL); > > i8257_dma_init(isa_bus, 0); > > - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); > > + s->superio_cfg.superio =3D ISA_SUPERIO(isa_create_simple(isa_bus, > > + TYPE_VT82C686B_S= UPERIO)); > > + ic =3D ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio); > > mc146818_rtc_init(isa_bus, 2000, NULL); > > =20 > > for (i =3D 0; i < PCI_CONFIG_HEADER_SIZE; i++) { > > @@ -412,6 +477,21 @@ static void vt82c686b_realize(PCIDevice *d, Error = **errp) > > */ > > memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, > > &s->superio_cfg.io); > > + > > + /* Grab io regions of serial devices so we can control them */ > > + for (i =3D 0; i < ic->serial.count; i++) { > > + ISADevice *sd =3D s->superio_cfg.superio->serial[i]; > > + MemoryRegion *io =3D isa_address_space_io(sd); > > + MemoryRegion *mr =3D find_subregion(sd, io, sd->ioport_id); > > + if (!mr) { > > + error_setg(errp, "Could not get io region for serial %d", = i); > > + return; > > + } > > + s->superio_cfg.serial_io[i] =3D mr; > > + if (memory_region_is_mapped(mr)) { > > + memory_region_del_subregion(io, mr); > > + } > > + } > > } > > =20 > > static void via_class_init(ObjectClass *klass, void *data) > >=20 >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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