* [PATCH v3 0/7] target/ppc: untangle CPU init from translation
@ 2021-04-30 19:35 Bruno Larsen (billionai)
2021-04-30 19:35 ` [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro Bruno Larsen (billionai)
` (6 more replies)
0 siblings, 7 replies; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
Based-on: 20210429162130.2412-2-bruno.larsen@eldorado.org.br
([PATCH v2 1/7] target/ppc: move opcode table logic to translate.c)
which is based on: 20210426184706.48040-1-bruno.larsen@eldorado.org.br
([PATCH v4] target/ppc: code motion from translate_init.c.inc to gdbstub.c)
This patch series aims to remove the logic of initializing CPU from
the file related to TCG translation. To achieve this, we have to make
it so registering SPRs isn't directly tied to TCG, and move code only
related to translation out of translate_init.c.inc and into translate.c.
This is in preparation to compile this target without TCG.
Changes for v3:
* fixed the parameters of _spr_register
* remove some redundant #include statements
* removed some functions that were mentioned in v2 as unnecessary
* added copyright header to relevant files
* removed first patch, that was already applied
* removed a changed that would add a regression
Changes for v2:
* split and reordered patches, to make it easier to review
* improved commit messages
* Undid creation of spr_common, as it was unnecessary
* kept more functions as static
* ensured that the project builds after every commit
Bruno Larsen (billionai) (7):
target/ppc: Created !TCG SPR registration macro
target/ppc: Isolated SPR read/write callbacks
target/ppc: remove unnecessary SPR functions
target/ppc: turned SPR R/W callbacks not static
target/ppc: removed VSCR from SPR registration
target/ppc: renamed SPR registration functions
target/ppc: isolated cpu init from translation logic
.../ppc/{translate_init.c.inc => cpu_init.c} | 1892 ++++-------------
target/ppc/internal.h | 3 +
target/ppc/meson.build | 1 +
target/ppc/spr_tcg.c.inc | 1041 +++++++++
target/ppc/spr_tcg.h | 134 ++
target/ppc/translate.c | 50 +-
6 files changed, 1651 insertions(+), 1470 deletions(-)
rename target/ppc/{translate_init.c.inc => cpu_init.c} (89%)
create mode 100644 target/ppc/spr_tcg.c.inc
create mode 100644 target/ppc/spr_tcg.h
--
2.17.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
@ 2021-04-30 19:35 ` Bruno Larsen (billionai)
2021-05-01 0:27 ` Richard Henderson
2021-04-30 19:35 ` [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks Bruno Larsen (billionai)
` (5 subsequent siblings)
6 siblings, 1 reply; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
moved RW callback parameters of _spr_register into an ifdef, to support
building without TCG in the future, and added definitions for
spr_register and spr_register_kvm, to keep the same call regardless of
build options
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/translate_init.c.inc | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 6235eb7536..22b23793fd 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -720,6 +720,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
helper_mtvscr(env, val);
}
+#ifdef CONFIG_TCG
#ifdef CONFIG_USER_ONLY
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, one_reg_id, initial_value) \
@@ -728,7 +729,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
oea_read, oea_write, hea_read, hea_write, \
one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, initial_value)
-#else
+#else /* CONFIG_USER_ONLY */
#if !defined(CONFIG_KVM)
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, one_reg_id, initial_value) \
@@ -739,7 +740,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, \
oea_read, oea_write, hea_read, hea_write, initial_value)
-#else
+#else /* CONFIG_KVM */
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, \
@@ -751,8 +752,21 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
_spr_register(env, num, name, uea_read, uea_write, \
oea_read, oea_write, hea_read, hea_write, \
one_reg_id, initial_value)
-#endif
-#endif
+#endif /* CONFIG_KVM */
+#endif /* CONFIG_USER_ONLY */
+#else /* CONFIG_TCG */
+#ifdef CONFIG_KVM /* sanity check. should always enter this */
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, one_reg_id, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, one_reg_id, initial_value)
+#else /* CONFIG_KVM */
+#error "Either TCG or KVM should be configured"
+#endif /* CONFIG_KVM */
+#endif /* CONFIG_TCG */
#define spr_register(env, num, name, uea_read, uea_write, \
oea_read, oea_write, initial_value) \
@@ -768,6 +782,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
static inline void _spr_register(CPUPPCState *env, int num,
const char *name,
+#if defined(CONFIG_TCG)
void (*uea_read)(DisasContext *ctx,
int gprn, int sprn),
void (*uea_write)(DisasContext *ctx,
@@ -782,7 +797,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
int gprn, int sprn),
void (*hea_write)(DisasContext *opaque,
int sprn, int gprn),
-#endif
+#endif /* CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
#if defined(CONFIG_KVM)
uint64_t one_reg_id,
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
2021-04-30 19:35 ` [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro Bruno Larsen (billionai)
@ 2021-04-30 19:35 ` Bruno Larsen (billionai)
2021-05-01 0:55 ` Richard Henderson
2021-05-03 4:54 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions Bruno Larsen (billionai)
` (4 subsequent siblings)
6 siblings, 2 replies; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
Moved all SPR read/write callback, and some related functions, to a
new file specific for it. These callbacks are TCG only, so separating
them is required to support the build flag disable-tcg.
Making the spr_noaccess function not static, and moving the define to
internal.h is required, otherwise the project doesn't build
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/internal.h | 3 +
target/ppc/spr_tcg.c.inc | 1052 +++++++++++++++++++++++++++++++
target/ppc/translate.c | 47 +-
target/ppc/translate_init.c.inc | 981 ----------------------------
4 files changed, 1056 insertions(+), 1027 deletions(-)
create mode 100644 target/ppc/spr_tcg.c.inc
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 184ba6d6b3..1de15acfbd 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -228,4 +228,7 @@ void destroy_ppc_opcodes(PowerPCCPU *cpu);
void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *ppc);
gchar *ppc_gdb_arch_name(CPUState *cs);
+void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
+#define SPR_NOACCESS (&spr_noaccess)
+
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/spr_tcg.c.inc b/target/ppc/spr_tcg.c.inc
new file mode 100644
index 0000000000..8d033dae6f
--- /dev/null
+++ b/target/ppc/spr_tcg.c.inc
@@ -0,0 +1,1052 @@
+/*
+ * PowerPC emulation for qemu: read/write callbacks for SPRs
+ *
+ * Copyright (C) 2021 Instituto de Pesquisas Eldorado
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*****************************************************************************/
+/* Reader and writer functions for SPRs */
+
+static void gen_read_xer(DisasContext *ctx, TCGv dst)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ tcg_gen_mov_tl(dst, cpu_xer);
+ tcg_gen_shli_tl(t0, cpu_so, XER_SO);
+ tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
+ tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_or_tl(dst, dst, t2);
+ tcg_gen_or_tl(dst, dst, t0);
+ if (is_isa300(ctx)) {
+ tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
+ tcg_gen_or_tl(dst, dst, t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void gen_write_xer(TCGv src)
+{
+ /* Write all flags, while reading back check for isa300 */
+ tcg_gen_andi_tl(cpu_xer, src,
+ ~((1u << XER_SO) |
+ (1u << XER_OV) | (1u << XER_OV32) |
+ (1u << XER_CA) | (1u << XER_CA32)));
+ tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
+ tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
+ tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
+ tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
+ tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
+}
+
+void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
+{
+#if 0
+ sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
+ printf("ERROR: try to access SPR %d !\n", sprn);
+#endif
+}
+
+/* #define PPC_DUMP_SPR_ACCESSES */
+
+/*
+ * Generic callbacks:
+ * do nothing but store/retrieve spr value
+ */
+static void spr_load_dump_spr(int sprn)
+{
+#ifdef PPC_DUMP_SPR_ACCESSES
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_load_dump_spr(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+#endif
+}
+
+static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], sprn);
+ spr_load_dump_spr(sprn);
+}
+
+static void spr_store_dump_spr(int sprn)
+{
+#ifdef PPC_DUMP_SPR_ACCESSES
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_store_dump_spr(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+#endif
+}
+
+static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_store_spr(sprn, cpu_gpr[gprn]);
+ spr_store_dump_spr(sprn);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
+{
+#ifdef TARGET_PPC64
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ spr_store_dump_spr(sprn);
+#else
+ spr_write_generic(ctx, sprn, gprn);
+#endif
+}
+
+static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_load_spr(t0, sprn);
+ tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
+ tcg_gen_and_tl(t0, t0, t1);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
+{
+}
+
+#endif
+
+/* SPR common to all PowerPC */
+/* XER */
+static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_read_xer(ctx, cpu_gpr[gprn]);
+}
+
+static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_write_xer(cpu_gpr[gprn]);
+}
+
+/* LR */
+static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
+}
+
+static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
+}
+
+/* CFAR */
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
+}
+
+static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
+}
+#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
+
+/* CTR */
+static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
+}
+
+static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
+}
+
+/* User read access to SPR */
+/* USPRx */
+/* UMMCRx */
+/* UPMCx */
+/* USIA */
+/* UDECR */
+static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
+}
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
+}
+#endif
+
+/* SPR common to all non-embedded PowerPC */
+/* DECR */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+#endif
+
+/* SPR common to all non-embedded PowerPC, except 601 */
+/* Time base */
+static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+ATTRIBUTE_UNUSED
+static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
+}
+
+ATTRIBUTE_UNUSED
+static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+ATTRIBUTE_UNUSED
+static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
+}
+
+ATTRIBUTE_UNUSED
+static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
+}
+
+#if defined(TARGET_PPC64)
+ATTRIBUTE_UNUSED
+static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+/* HDECR */
+static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+#endif
+#endif
+
+#if !defined(CONFIG_USER_ONLY)
+/* IBAT0U...IBAT0U */
+/* IBAT0L...IBAT7L */
+static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+}
+
+static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
+}
+
+static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
+ gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
+ gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
+ gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+/* DBAT0U...DBAT7U */
+/* DBAT0L...DBAT7L */
+static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
+}
+
+static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
+}
+
+static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
+ gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
+ gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
+ gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
+ gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+/* SDR1 */
+static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
+}
+
+#if defined(TARGET_PPC64)
+/* 64 bits PowerPC specific SPRs */
+/* PIDR */
+static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
+}
+
+static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ tcg_temp_free(t0);
+}
+
+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
+}
+
+/* DPDES */
+static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
+}
+#endif
+#endif
+
+/* PowerPC 601 specific registers */
+/* RTC */
+static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
+ /* Must stop the translation as endianness may have changed */
+ gen_stop_exception(ctx);
+}
+#endif
+
+/* Unified bats */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+}
+
+static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+#endif
+
+/* PowerPC 40x specific registers */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_store_spr(sprn, cpu_gpr[gprn]);
+ gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
+ /* We must stop translation as we may have rebooted */
+ gen_stop_exception(ctx);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+#endif
+
+/* PowerPC 403 specific registers */
+/* PBL1 / PBU1 / PBL2 / PBU2 */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
+}
+
+static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
+ gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
+ gen_store_spr(SPR_PIR, t0);
+ tcg_temp_free(t0);
+}
+#endif
+
+/* SPE specific registers */
+static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
+ tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_temp_free_i32(t0);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+
+/* Callback used to write the exception vector base */
+static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
+{
+ int sprn_offs;
+
+ if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR0;
+ } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
+ } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
+ } else {
+ printf("Trying to write an unknown exception vector %d %03x\n",
+ sprn, sprn);
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+ return;
+ }
+
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+#endif
+
+#ifdef TARGET_PPC64
+#ifndef CONFIG_USER_ONLY
+static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 PR=0 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ if (ctx->pr) {
+ gen_load_spr(t1, SPR_UAMOR);
+ } else {
+ gen_load_spr(t1, SPR_AMOR);
+ }
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_AMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_AMR, t0);
+ spr_store_dump_spr(SPR_AMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_UAMOR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_UAMOR, t0);
+ spr_store_dump_spr(SPR_UAMOR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_IAMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_IAMR, t0);
+ spr_store_dump_spr(SPR_IAMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+#endif /* CONFIG_USER_ONLY */
+#endif /* TARGET_PPC64 */
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_fixup_thrm(cpu_env);
+ gen_load_spr(cpu_gpr[gprn], sprn);
+ spr_load_dump_spr(sprn);
+}
+
+static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn],
+ ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv val = tcg_temp_new();
+ tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
+ gen_store_spr(SPR_BOOKE_MAS3, val);
+ tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
+ gen_store_spr(SPR_BOOKE_MAS7, val);
+ tcg_temp_free(val);
+}
+
+static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv mas7 = tcg_temp_new();
+ TCGv mas3 = tcg_temp_new();
+ gen_load_spr(mas7, SPR_BOOKE_MAS7);
+ tcg_gen_shli_tl(mas7, mas7, 32);
+ gen_load_spr(mas3, SPR_BOOKE_MAS3);
+ tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
+ tcg_temp_free(mas3);
+ tcg_temp_free(mas7);
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+#ifdef TARGET_PPC64
+static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
+ int bit, int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
+static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
+ int bit, int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
+static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv spr_up = tcg_temp_new();
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_shri_tl(spr_up, spr, 32);
+ tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
+
+ tcg_temp_free(spr);
+ tcg_temp_free(spr_up);
+}
+
+static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
+ gen_store_spr(sprn - 1, spr);
+
+ tcg_temp_free(spr);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv hmer = tcg_temp_new();
+
+ gen_load_spr(hmer, sprn);
+ tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
+ gen_store_spr(sprn, hmer);
+ spr_store_dump_spr(sprn);
+ tcg_temp_free(hmer);
+}
+
+static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
+}
+#endif
+
+static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_prev_upper32(ctx, gprn, sprn);
+}
+
+static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_prev_upper32(ctx, sprn, gprn);
+}
+
+static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_prev_upper32(ctx, gprn, sprn);
+}
+
+static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_prev_upper32(ctx, sprn, gprn);
+}
+#endif
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b319d409c6..dba112087e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4175,43 +4175,6 @@ static void gen_tdi(DisasContext *ctx)
/*** Processor control ***/
-static void gen_read_xer(DisasContext *ctx, TCGv dst)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_mov_tl(dst, cpu_xer);
- tcg_gen_shli_tl(t0, cpu_so, XER_SO);
- tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
- tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_or_tl(dst, dst, t2);
- tcg_gen_or_tl(dst, dst, t0);
- if (is_isa300(ctx)) {
- tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
- tcg_gen_or_tl(dst, dst, t0);
- tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
- tcg_gen_or_tl(dst, dst, t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void gen_write_xer(TCGv src)
-{
- /* Write all flags, while reading back check for isa300 */
- tcg_gen_andi_tl(cpu_xer, src,
- ~((1u << XER_SO) |
- (1u << XER_OV) | (1u << XER_OV32) |
- (1u << XER_CA) | (1u << XER_CA32)));
- tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
- tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
- tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
- tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
- tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
-}
-
/* mcrxr */
static void gen_mcrxr(DisasContext *ctx)
{
@@ -4299,15 +4262,6 @@ static void gen_mfmsr(DisasContext *ctx)
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
}
-static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
-{
-#if 0
- sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
- printf("ERROR: try to access SPR %d !\n", sprn);
-#endif
-}
-#define SPR_NOACCESS (&spr_noaccess)
-
/* mfspr */
static inline void gen_op_mfspr(DisasContext *ctx)
{
@@ -7639,6 +7593,7 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
};
#include "helper_regs.h"
+#include "spr_tcg.c.inc"
#include "translate_init.c.inc"
/*****************************************************************************/
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 22b23793fd..13ad58863e 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -43,676 +43,8 @@
#include "qapi/qapi-commands-machine-target.h"
/* #define PPC_DEBUG_SPR */
-/* #define PPC_DUMP_SPR_ACCESSES */
/* #define USE_APPLE_GDB */
-/*
- * Generic callbacks:
- * do nothing but store/retrieve spr value
- */
-static void spr_load_dump_spr(int sprn)
-{
-#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_load_dump_spr(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif
-}
-
-static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
-{
- gen_load_spr(cpu_gpr[gprn], sprn);
- spr_load_dump_spr(sprn);
-}
-
-static void spr_store_dump_spr(int sprn)
-{
-#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_store_dump_spr(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif
-}
-
-static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(sprn, cpu_gpr[gprn]);
- spr_store_dump_spr(sprn);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
-{
-#ifdef TARGET_PPC64
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
- spr_store_dump_spr(sprn);
-#else
- spr_write_generic(ctx, sprn, gprn);
-#endif
-}
-
-static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_load_spr(t0, sprn);
- tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
- tcg_gen_and_tl(t0, t0, t1);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
-{
-}
-
-#endif
-
-/* SPR common to all PowerPC */
-/* XER */
-static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
-{
- gen_read_xer(ctx, cpu_gpr[gprn]);
-}
-
-static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
-{
- gen_write_xer(cpu_gpr[gprn]);
-}
-
-/* LR */
-static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
-}
-
-static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
-}
-
-/* CFAR */
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
-}
-
-static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
-}
-#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
-
-/* CTR */
-static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
-}
-
-static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
-}
-
-/* User read access to SPR */
-/* USPRx */
-/* UMMCRx */
-/* UPMCx */
-/* USIA */
-/* UDECR */
-static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
-{
- gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
-}
-
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
-}
-#endif
-
-/* SPR common to all non-embedded PowerPC */
-/* DECR */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-#endif
-
-/* SPR common to all non-embedded PowerPC, except 601 */
-/* Time base */
-static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-ATTRIBUTE_UNUSED
-static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
-}
-
-ATTRIBUTE_UNUSED
-static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-ATTRIBUTE_UNUSED
-static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
-}
-
-ATTRIBUTE_UNUSED
-static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
-}
-
-#if defined(TARGET_PPC64)
-ATTRIBUTE_UNUSED
-static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-/* HDECR */
-static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-#endif
-#endif
-
-#if !defined(CONFIG_USER_ONLY)
-/* IBAT0U...IBAT0U */
-/* IBAT0L...IBAT7L */
-static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
-}
-
-static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
-}
-
-static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-/* DBAT0U...DBAT7U */
-/* DBAT0L...DBAT7L */
-static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
-}
-
-static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
-}
-
-static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-/* SDR1 */
-static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
-}
-
-#if defined(TARGET_PPC64)
-/* 64 bits PowerPC specific SPRs */
-/* PIDR */
-static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
-}
-
-static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
- tcg_temp_free(t0);
-}
-static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
-}
-
-/* DPDES */
-static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
-}
-#endif
-#endif
-
-/* PowerPC 601 specific registers */
-/* RTC */
-static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
- /* Must stop the translation as endianness may have changed */
- gen_stop_exception(ctx);
-}
-#endif
-
-/* Unified bats */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
-}
-
-static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-#endif
-
-/* PowerPC 40x specific registers */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_store_spr(sprn, cpu_gpr[gprn]);
- gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
- /* We must stop translation as we may have rebooted */
- gen_stop_exception(ctx);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-#endif
-
-/* PowerPC 403 specific registers */
-/* PBL1 / PBU1 / PBL2 / PBU2 */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
-}
-
-static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
- gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
- gen_store_spr(SPR_PIR, t0);
- tcg_temp_free(t0);
-}
-#endif
-
-/* SPE specific registers */
-static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
- tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
- tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
- tcg_temp_free_i32(t0);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-/* Callback used to write the exception vector base */
-static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
-{
- int sprn_offs;
-
- if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
- sprn_offs = sprn - SPR_BOOKE_IVOR0;
- } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
- sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
- } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
- sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
- } else {
- printf("Trying to write an unknown exception vector %d %03x\n",
- sprn, sprn);
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
- return;
- }
-
- TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-#endif
-
static inline void vscr_init(CPUPPCState *env, uint32_t val)
{
/* Altivec always uses round-to-nearest */
@@ -1247,104 +579,6 @@ static void gen_spr_7xx(CPUPPCState *env)
}
#ifdef TARGET_PPC64
-#ifndef CONFIG_USER_ONLY
-static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 PR=0 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- if (ctx->pr) {
- gen_load_spr(t1, SPR_UAMOR);
- } else {
- gen_load_spr(t1, SPR_AMOR);
- }
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_AMR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_AMR, t0);
- spr_store_dump_spr(SPR_AMR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- gen_load_spr(t1, SPR_AMOR);
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_UAMOR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_UAMOR, t0);
- spr_store_dump_spr(SPR_UAMOR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- gen_load_spr(t1, SPR_AMOR);
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_IAMR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_IAMR, t0);
- spr_store_dump_spr(SPR_IAMR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-#endif /* CONFIG_USER_ONLY */
static void gen_spr_amr(CPUPPCState *env)
{
@@ -1390,15 +624,6 @@ static void gen_spr_iamr(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-#ifndef CONFIG_USER_ONLY
-static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_fixup_thrm(cpu_env);
- gen_load_spr(cpu_gpr[gprn], sprn);
- spr_load_dump_spr(sprn);
-}
-#endif /* !CONFIG_USER_ONLY */
-
static void gen_spr_thrm(CPUPPCState *env)
{
/* Thermal management */
@@ -1766,57 +991,6 @@ static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
#endif
}
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn],
- ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
-}
-static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
-}
-
-#endif
-
static void gen_spr_usprg3(CPUPPCState *env)
{
spr_register(env, SPR_USPRG3, "USPRG3",
@@ -4897,31 +4071,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv val = tcg_temp_new();
- tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
- gen_store_spr(SPR_BOOKE_MAS3, val);
- tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
- gen_store_spr(SPR_BOOKE_MAS7, val);
- tcg_temp_free(val);
-}
-
-static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv mas7 = tcg_temp_new();
- TCGv mas3 = tcg_temp_new();
- gen_load_spr(mas7, SPR_BOOKE_MAS7);
- tcg_gen_shli_tl(mas7, mas7, 32);
- gen_load_spr(mas3, SPR_BOOKE_MAS3);
- tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
- tcg_temp_free(mas3);
- tcg_temp_free(mas7);
-}
-
-#endif
-
enum fsl_e500_version {
fsl_e500v1,
fsl_e500v2,
@@ -7625,58 +6774,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
#define POWERPC970_HID5_INIT 0x00000000
#endif
-static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
- int bit, int sprn, int cause)
-{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
-
- gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
-
- tcg_temp_free_i32(t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t1);
-}
-
-static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
- int bit, int sprn, int cause)
-{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
-
- gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
-
- tcg_temp_free_i32(t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t1);
-}
-
-static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv spr_up = tcg_temp_new();
- TCGv spr = tcg_temp_new();
-
- gen_load_spr(spr, sprn - 1);
- tcg_gen_shri_tl(spr_up, spr, 32);
- tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
-
- tcg_temp_free(spr);
- tcg_temp_free(spr_up);
-}
-
-static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv spr = tcg_temp_new();
-
- gen_load_spr(spr, sprn - 1);
- tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
- gen_store_spr(sprn - 1, spr);
-
- tcg_temp_free(spr);
-}
-
static int check_pow_970(CPUPPCState *env)
{
if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
@@ -7976,24 +7073,6 @@ static void gen_spr_power5p_tb(CPUPPCState *env)
0x00000000);
}
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv hmer = tcg_temp_new();
-
- gen_load_spr(hmer, sprn);
- tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
- gen_store_spr(sprn, hmer);
- spr_store_dump_spr(sprn);
- tcg_temp_free(hmer);
-}
-
-static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
-}
-#endif /* !defined(CONFIG_USER_ONLY) */
-
static void gen_spr_970_lpar(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -8191,18 +7270,6 @@ static void gen_spr_power6_common(CPUPPCState *env)
0x00000000);
}
-static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
- spr_write_generic(ctx, sprn, gprn);
-}
-
static void gen_spr_power8_tce_address_control(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TAR, "TAR",
@@ -8211,30 +7278,6 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
KVM_REG_PPC_TAR, 0x00000000);
}
-static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_write_generic(ctx, sprn, gprn);
-}
-
-static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_read_prev_upper32(ctx, gprn, sprn);
-}
-
-static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_write_prev_upper32(ctx, sprn, gprn);
-}
-
static void gen_spr_power8_tm(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TFHAR, "TFHAR",
@@ -8255,30 +7298,6 @@ static void gen_spr_power8_tm(CPUPPCState *env)
0x00000000);
}
-static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_write_generic(ctx, sprn, gprn);
-}
-
-static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_read_prev_upper32(ctx, gprn, sprn);
-}
-
-static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_write_prev_upper32(ctx, sprn, gprn);
-}
-
static void gen_spr_power8_ebb(CPUPPCState *env)
{
spr_register(env, SPR_BESCRS, "BESCRS",
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
2021-04-30 19:35 ` [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro Bruno Larsen (billionai)
2021-04-30 19:35 ` [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks Bruno Larsen (billionai)
@ 2021-04-30 19:35 ` Bruno Larsen (billionai)
2021-05-01 0:58 ` Richard Henderson
2021-04-30 19:35 ` [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
` (3 subsequent siblings)
6 siblings, 1 reply; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
Removed functions gen_read_xer and gen_write_xer, moving their logic
directly into spr_read_xer and spr_write_xer, respectively.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/spr_tcg.c.inc | 70 ++++++++++++++++++----------------------
1 file changed, 31 insertions(+), 39 deletions(-)
diff --git a/target/ppc/spr_tcg.c.inc b/target/ppc/spr_tcg.c.inc
index 8d033dae6f..253b344ba7 100644
--- a/target/ppc/spr_tcg.c.inc
+++ b/target/ppc/spr_tcg.c.inc
@@ -20,43 +20,6 @@
/*****************************************************************************/
/* Reader and writer functions for SPRs */
-static void gen_read_xer(DisasContext *ctx, TCGv dst)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_mov_tl(dst, cpu_xer);
- tcg_gen_shli_tl(t0, cpu_so, XER_SO);
- tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
- tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_or_tl(dst, dst, t2);
- tcg_gen_or_tl(dst, dst, t0);
- if (is_isa300(ctx)) {
- tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
- tcg_gen_or_tl(dst, dst, t0);
- tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
- tcg_gen_or_tl(dst, dst, t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void gen_write_xer(TCGv src)
-{
- /* Write all flags, while reading back check for isa300 */
- tcg_gen_andi_tl(cpu_xer, src,
- ~((1u << XER_SO) |
- (1u << XER_OV) | (1u << XER_OV32) |
- (1u << XER_CA) | (1u << XER_CA32)));
- tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
- tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
- tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
- tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
- tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
-}
-
void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
{
#if 0
@@ -137,12 +100,41 @@ static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
/* XER */
static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
{
- gen_read_xer(ctx, cpu_gpr[gprn]);
+ TCGv dst = cpu_gpr[gprn];
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ tcg_gen_mov_tl(dst, cpu_xer);
+ tcg_gen_shli_tl(t0, cpu_so, XER_SO);
+ tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
+ tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_or_tl(dst, dst, t2);
+ tcg_gen_or_tl(dst, dst, t0);
+ if (is_isa300(ctx)) {
+ tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
+ tcg_gen_or_tl(dst, dst, t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
}
static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
{
- gen_write_xer(cpu_gpr[gprn]);
+ TCGv src = cpu_gpr[gprn];
+ /* Write all flags, while reading back check for isa300 */
+ tcg_gen_andi_tl(cpu_xer, src,
+ ~((1u << XER_SO) |
+ (1u << XER_OV) | (1u << XER_OV32) |
+ (1u << XER_CA) | (1u << XER_CA32)));
+ tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
+ tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
+ tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
+ tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
+ tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
}
/* LR */
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
` (2 preceding siblings ...)
2021-04-30 19:35 ` [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions Bruno Larsen (billionai)
@ 2021-04-30 19:35 ` Bruno Larsen (billionai)
2021-05-01 1:05 ` Richard Henderson
2021-04-30 19:35 ` [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration Bruno Larsen (billionai)
` (2 subsequent siblings)
6 siblings, 1 reply; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
To be able to compile translate_init.c.inc as a standalone file,
we have to make the callbacks accessible outside of translate.c;
This patch does exactly that
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/spr_tcg.c.inc | 209 ++++++++++++++++----------------
target/ppc/spr_tcg.h | 134 ++++++++++++++++++++
target/ppc/translate_init.c.inc | 1 +
3 files changed, 238 insertions(+), 106 deletions(-)
create mode 100644 target/ppc/spr_tcg.h
diff --git a/target/ppc/spr_tcg.c.inc b/target/ppc/spr_tcg.c.inc
index 253b344ba7..30602d0087 100644
--- a/target/ppc/spr_tcg.c.inc
+++ b/target/ppc/spr_tcg.c.inc
@@ -17,6 +17,8 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "spr_tcg.h"
+
/*****************************************************************************/
/* Reader and writer functions for SPRs */
@@ -43,7 +45,7 @@ static void spr_load_dump_spr(int sprn)
#endif
}
-static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
+void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
{
gen_load_spr(cpu_gpr[gprn], sprn);
spr_load_dump_spr(sprn);
@@ -58,14 +60,14 @@ static void spr_store_dump_spr(int sprn)
#endif
}
-static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
+void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
{
gen_store_spr(sprn, cpu_gpr[gprn]);
spr_store_dump_spr(sprn);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
{
#ifdef TARGET_PPC64
TCGv t0 = tcg_temp_new();
@@ -78,7 +80,7 @@ static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
#endif
}
-static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
+void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -90,7 +92,7 @@ static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t1);
}
-static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
+void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
{
}
@@ -98,7 +100,7 @@ static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
/* SPR common to all PowerPC */
/* XER */
-static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
+void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
{
TCGv dst = cpu_gpr[gprn];
TCGv t0 = tcg_temp_new();
@@ -122,7 +124,7 @@ static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
tcg_temp_free(t2);
}
-static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
+void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
{
TCGv src = cpu_gpr[gprn];
/* Write all flags, while reading back check for isa300 */
@@ -138,36 +140,36 @@ static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
}
/* LR */
-static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
}
-static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
{
tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
}
/* CFAR */
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
+void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
}
-static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
+void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
{
tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
}
#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
/* CTR */
-static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
}
-static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
{
tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
}
@@ -178,13 +180,13 @@ static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
/* UPMCx */
/* USIA */
/* UDECR */
-static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
{
gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
}
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
{
gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
}
@@ -193,7 +195,7 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
/* SPR common to all non-embedded PowerPC */
/* DECR */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -204,7 +206,7 @@ static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -218,7 +220,7 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
/* SPR common to all non-embedded PowerPC, except 601 */
/* Time base */
-static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -230,7 +232,7 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -242,20 +244,18 @@ static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
}
}
-ATTRIBUTE_UNUSED
-static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
}
-ATTRIBUTE_UNUSED
-static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
+void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -267,7 +267,7 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -279,21 +279,18 @@ static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
}
}
-ATTRIBUTE_UNUSED
-static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
}
-ATTRIBUTE_UNUSED
-static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
}
#if defined(TARGET_PPC64)
-ATTRIBUTE_UNUSED
-static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -304,7 +301,7 @@ static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -316,7 +313,7 @@ static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
}
/* HDECR */
-static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -328,7 +325,7 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -340,7 +337,7 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
+void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -351,7 +348,7 @@ static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
+void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -362,7 +359,7 @@ static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -379,42 +376,42 @@ static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
/* IBAT0U...IBAT0U */
/* IBAT0L...IBAT7L */
-static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
-static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
}
-static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
@@ -423,42 +420,42 @@ static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
/* DBAT0U...DBAT7U */
/* DBAT0L...DBAT7L */
-static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
+void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
}
-static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
+void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
}
-static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
@@ -466,7 +463,7 @@ static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
}
/* SDR1 */
-static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
+void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
}
@@ -474,22 +471,22 @@ static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
#if defined(TARGET_PPC64)
/* 64 bits PowerPC specific SPRs */
/* PIDR */
-static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
}
-static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
+void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
}
-static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
@@ -497,23 +494,23 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
}
/* DPDES */
-static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
+void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
}
-static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
}
@@ -522,28 +519,28 @@ static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
/* PowerPC 601 specific registers */
/* RTC */
-static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
}
-static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
+void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
/* Must stop the translation as endianness may have changed */
@@ -553,21 +550,21 @@ static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
/* Unified bats */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
+void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
-static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
@@ -577,7 +574,7 @@ static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
/* PowerPC 40x specific registers */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
+void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -588,7 +585,7 @@ static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
+void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -599,7 +596,7 @@ static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -613,7 +610,7 @@ static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
+void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -624,7 +621,7 @@ static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -635,7 +632,7 @@ static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -650,20 +647,20 @@ static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
/* PowerPC 403 specific registers */
/* PBL1 / PBU1 / PBL2 / PBU2 */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
}
-static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
+void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
@@ -673,7 +670,7 @@ static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
#endif
/* SPE specific registers */
-static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
@@ -681,7 +678,7 @@ static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
tcg_temp_free_i32(t0);
}
-static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
@@ -692,7 +689,7 @@ static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
/* Callback used to write the exception vector base */
-static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
+void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
@@ -702,7 +699,7 @@ static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
+void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
{
int sprn_offs;
@@ -730,7 +727,7 @@ static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
#ifdef TARGET_PPC64
#ifndef CONFIG_USER_ONLY
-static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -765,7 +762,7 @@ static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t2);
}
-static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
+void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -796,7 +793,7 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t2);
}
-static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -830,14 +827,14 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
#endif /* TARGET_PPC64 */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
+void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_fixup_thrm(cpu_env);
gen_load_spr(cpu_gpr[gprn], sprn);
spr_load_dump_spr(sprn);
}
-static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
@@ -846,7 +843,7 @@ static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
+void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
@@ -855,7 +852,7 @@ static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
@@ -865,29 +862,29 @@ static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(sprn);
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
+void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
+void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
+void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
{
TCGv val = tcg_temp_new();
tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
@@ -897,7 +894,7 @@ static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(val);
}
-static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
+void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
{
TCGv mas7 = tcg_temp_new();
TCGv mas3 = tcg_temp_new();
@@ -940,7 +937,7 @@ static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
tcg_temp_free_i32(t1);
}
-static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
+void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
{
TCGv spr_up = tcg_temp_new();
TCGv spr = tcg_temp_new();
@@ -953,7 +950,7 @@ static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
tcg_temp_free(spr_up);
}
-static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
{
TCGv spr = tcg_temp_new();
@@ -965,7 +962,7 @@ static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
{
TCGv hmer = tcg_temp_new();
@@ -976,67 +973,67 @@ static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(hmer);
}
-static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
}
#endif
-static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
spr_read_generic(ctx, gprn, sprn);
}
-static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
spr_write_generic(ctx, sprn, gprn);
}
-static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_read_generic(ctx, gprn, sprn);
}
-static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_write_generic(ctx, sprn, gprn);
}
-static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_read_prev_upper32(ctx, gprn, sprn);
}
-static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_write_prev_upper32(ctx, sprn, gprn);
}
-static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_read_generic(ctx, gprn, sprn);
}
-static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_write_generic(ctx, sprn, gprn);
}
-static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_read_prev_upper32(ctx, gprn, sprn);
}
-static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_write_prev_upper32(ctx, sprn, gprn);
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
new file mode 100644
index 0000000000..fbc6a43f90
--- /dev/null
+++ b/target/ppc/spr_tcg.h
@@ -0,0 +1,134 @@
+/*
+ * PowerPC emulation for qemu: read/write callbacks for SPRs
+ *
+ * Copyright (C) 2021 Instituto de Pesquisas Eldorado
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef SPR_TCG_H
+#define SPR_TCG_H
+
+/* prototypes for readers and writers for SPRs */
+
+void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
+void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
+void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
+void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
+void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_lr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ctr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ctr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ureg(DisasContext *ctx, int gprn, int sprn);
+void spr_read_tbl(DisasContext *ctx, int gprn, int sprn);
+void spr_read_tbu(DisasContext *ctx, int gprn, int sprn);
+void spr_read_atbl(DisasContext *ctx, int gprn, int sprn);
+void spr_read_atbu(DisasContext *ctx, int gprn, int sprn);
+void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn);
+void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn);
+void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn);
+
+#ifndef CONFIG_USER_ONLY
+void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
+void spr_write_clear(DisasContext *ctx, int sprn, int gprn);
+void spr_access_nop(DisasContext *ctx, int sprn, int gprn);
+void spr_read_decr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_decr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_tbl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_tbu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_atbl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_atbu(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ibat(DisasContext *ctx, int gprn, int sprn);
+void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn);
+void spr_read_dbat(DisasContext *ctx, int gprn, int sprn);
+void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn);
+void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn);
+void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn);
+void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn);
+void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn);
+void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn);
+void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn);
+void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
+void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_pir(DisasContext *ctx, int sprn, int gprn);
+void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn);
+void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn);
+void spr_read_thrm(DisasContext *ctx, int gprn, int sprn);
+void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn);
+void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn);
+void spr_write_eplc(DisasContext *ctx, int sprn, int gprn);
+void spr_write_epsc(DisasContext *ctx, int sprn, int gprn);
+void spr_write_mas73(DisasContext *ctx, int sprn, int gprn);
+void spr_read_mas73(DisasContext *ctx, int gprn, int sprn);
+#ifdef TARGET_PPC64
+void spr_read_cfar(DisasContext *ctx, int gprn, int sprn);
+void spr_write_cfar(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ureg(DisasContext *ctx, int sprn, int gprn);
+void spr_read_purr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_purr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_vtb(DisasContext *ctx, int gprn, int sprn);
+void spr_write_vtb(DisasContext *ctx, int sprn, int gprn);
+void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn);
+void spr_write_pidr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_hior(DisasContext *ctx, int gprn, int sprn);
+void spr_write_hior(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_pcr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn);
+void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn);
+void spr_write_amr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_uamor(DisasContext *ctx, int sprn, int gprn);
+void spr_write_iamr(DisasContext *ctx, int sprn, int gprn);
+#endif
+#endif
+
+#ifdef TARGET_PPC64
+void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn);
+void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn);
+void spr_read_tar(DisasContext *ctx, int gprn, int sprn);
+void spr_write_tar(DisasContext *ctx, int sprn, int gprn);
+void spr_read_tm(DisasContext *ctx, int gprn, int sprn);
+void spr_write_tm(DisasContext *ctx, int sprn, int gprn);
+void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn);
+void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ebb(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ebb(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn);
+void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
+void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
+#endif
+
+#endif
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 13ad58863e..67529e8648 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -42,6 +42,7 @@
#include "fpu/softfloat.h"
#include "qapi/qapi-commands-machine-target.h"
+#include "spr_tcg.h"
/* #define PPC_DEBUG_SPR */
/* #define USE_APPLE_GDB */
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
` (3 preceding siblings ...)
2021-04-30 19:35 ` [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
@ 2021-04-30 19:35 ` Bruno Larsen (billionai)
2021-05-01 1:06 ` Richard Henderson
2021-05-03 4:47 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 6/7] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
2021-04-30 19:35 ` [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
6 siblings, 2 replies; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
Since vscr is not an spr, its initialization was removed from the
spr registration functions, and moved to the relevant init_procs.
We may look into adding vscr to the reset path instead of the init
path (as suggested by David Gibson), but this looked like a good
enough solution for now.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/translate_init.c.inc | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 67529e8648..b922b04f25 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -941,8 +941,6 @@ static void gen_spr_74xx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Not strictly an SPR */
- vscr_init(env, 0x00010000);
}
static void gen_l3_ctrl(CPUPPCState *env)
@@ -5790,6 +5788,7 @@ static void init_proc_7400(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -5869,6 +5868,7 @@ static void init_proc_7410(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -5954,6 +5954,7 @@ static void init_proc_7440(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -6062,6 +6063,7 @@ static void init_proc_7450(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* Level 3 cache control */
gen_l3_ctrl(env);
/* L3ITCR1 */
@@ -6196,6 +6198,7 @@ static void init_proc_7445(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
@@ -6333,6 +6336,7 @@ static void init_proc_7455(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* Level 3 cache control */
gen_l3_ctrl(env);
/* LDSTCR */
@@ -6472,6 +6476,7 @@ static void init_proc_7457(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* Level 3 cache control */
gen_l3_ctrl(env);
/* L3ITCR1 */
@@ -6635,6 +6640,7 @@ static void init_proc_e600(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -6833,11 +6839,6 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_VRSAVE, 0x00000000);
- /*
- * Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors.
- */
- vscr_init(env, 0x00010000);
}
static void gen_spr_book3s_dbg(CPUPPCState *env)
@@ -7457,6 +7458,11 @@ static void init_proc_book3s_common(CPUPPCState *env)
gen_spr_book3s_pmu_sup(env);
gen_spr_book3s_pmu_user(env);
gen_spr_book3s_ctrl(env);
+ /*
+ * Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors.
+ */
+ vscr_init(env, 0x00010000);
}
static void init_proc_970(CPUPPCState *env)
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 6/7] target/ppc: renamed SPR registration functions
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
` (4 preceding siblings ...)
2021-04-30 19:35 ` [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration Bruno Larsen (billionai)
@ 2021-04-30 19:35 ` Bruno Larsen (billionai)
2021-05-03 4:49 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
6 siblings, 1 reply; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
Renamed all gen_spr_* and gen_* functions specifically related to
registering SPRs to register_*_sprs and register_*, to avoid future
confusion with other TCG related code.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate_init.c.inc | 860 ++++++++++++++++----------------
1 file changed, 430 insertions(+), 430 deletions(-)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b922b04f25..274bd884a1 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -168,7 +168,7 @@ static inline void _spr_register(CPUPPCState *env, int num,
}
/* Generic PowerPC SPRs */
-static void gen_spr_generic(CPUPPCState *env)
+static void register_generic_sprs(CPUPPCState *env)
{
/* Integer processing */
spr_register(env, SPR_XER, "XER",
@@ -213,7 +213,7 @@ static void gen_spr_generic(CPUPPCState *env)
}
/* SPR common to all non-embedded PowerPC, including 601 */
-static void gen_spr_ne_601(CPUPPCState *env)
+static void register_ne_601_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -232,7 +232,7 @@ static void gen_spr_ne_601(CPUPPCState *env)
}
/* Storage Description Register 1 */
-static void gen_spr_sdr1(CPUPPCState *env)
+static void register_sdr1_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
if (env->has_hv_mode) {
@@ -255,7 +255,7 @@ static void gen_spr_sdr1(CPUPPCState *env)
}
/* BATs 0-3 */
-static void gen_low_BATs(CPUPPCState *env)
+static void register_low_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U",
@@ -327,7 +327,7 @@ static void gen_low_BATs(CPUPPCState *env)
}
/* BATs 4-7 */
-static void gen_high_BATs(CPUPPCState *env)
+static void register_high_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT4U, "IBAT4U",
@@ -399,7 +399,7 @@ static void gen_high_BATs(CPUPPCState *env)
}
/* Generic PowerPC time base */
-static void gen_tbl(CPUPPCState *env)
+static void register_tbl(CPUPPCState *env)
{
spr_register(env, SPR_VTBL, "TBL",
&spr_read_tbl, SPR_NOACCESS,
@@ -420,7 +420,7 @@ static void gen_tbl(CPUPPCState *env)
}
/* Softare table search registers */
-static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
@@ -459,7 +459,7 @@ static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
}
/* SPR common to MPC755 and G2 */
-static void gen_spr_G2_755(CPUPPCState *env)
+static void register_G2_755_sprs(CPUPPCState *env)
{
/* SGPRs */
spr_register(env, SPR_SPRG4, "SPRG4",
@@ -481,7 +481,7 @@ static void gen_spr_G2_755(CPUPPCState *env)
}
/* SPR common to all 7xx PowerPC implementations */
-static void gen_spr_7xx(CPUPPCState *env)
+static void register_7xx_sprs(CPUPPCState *env)
{
/* Breakpoints */
/* XXX : not implemented */
@@ -581,7 +581,7 @@ static void gen_spr_7xx(CPUPPCState *env)
#ifdef TARGET_PPC64
-static void gen_spr_amr(CPUPPCState *env)
+static void register_amr_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
/*
@@ -613,7 +613,7 @@ static void gen_spr_amr(CPUPPCState *env)
#endif /* !CONFIG_USER_ONLY */
}
-static void gen_spr_iamr(CPUPPCState *env)
+static void register_iamr_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
@@ -625,7 +625,7 @@ static void gen_spr_iamr(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-static void gen_spr_thrm(CPUPPCState *env)
+static void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
/* XXX : not implemented */
@@ -646,7 +646,7 @@ static void gen_spr_thrm(CPUPPCState *env)
}
/* SPR specific to PowerPC 604 implementation */
-static void gen_spr_604(CPUPPCState *env)
+static void register_604_sprs(CPUPPCState *env)
{
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
@@ -699,7 +699,7 @@ static void gen_spr_604(CPUPPCState *env)
}
/* SPR specific to PowerPC 603 implementation */
-static void gen_spr_603(CPUPPCState *env)
+static void register_603_sprs(CPUPPCState *env)
{
/* External access control */
/* XXX : not implemented */
@@ -717,7 +717,7 @@ static void gen_spr_603(CPUPPCState *env)
}
/* SPR specific to PowerPC G2 implementation */
-static void gen_spr_G2(CPUPPCState *env)
+static void register_G2_sprs(CPUPPCState *env)
{
/* Memory base address */
/* MBAR */
@@ -769,7 +769,7 @@ static void gen_spr_G2(CPUPPCState *env)
}
/* SPR specific to PowerPC 602 implementation */
-static void gen_spr_602(CPUPPCState *env)
+static void register_602_sprs(CPUPPCState *env)
{
/* ESA registers */
/* XXX : not implemented */
@@ -817,7 +817,7 @@ static void gen_spr_602(CPUPPCState *env)
}
/* SPR specific to PowerPC 601 implementation */
-static void gen_spr_601(CPUPPCState *env)
+static void register_601_sprs(CPUPPCState *env)
{
/* Multiplication/division register */
/* MQ */
@@ -893,7 +893,7 @@ static void gen_spr_601(CPUPPCState *env)
#endif
}
-static void gen_spr_74xx(CPUPPCState *env)
+static void register_74xx_sprs(CPUPPCState *env)
{
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
@@ -943,7 +943,7 @@ static void gen_spr_74xx(CPUPPCState *env)
0x00000000);
}
-static void gen_l3_ctrl(CPUPPCState *env)
+static void register_l3_ctrl(CPUPPCState *env)
{
/* L3CR */
/* XXX : not implemented */
@@ -965,7 +965,7 @@ static void gen_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
@@ -990,7 +990,7 @@ static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
#endif
}
-static void gen_spr_usprg3(CPUPPCState *env)
+static void register_usprg3_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG3, "USPRG3",
&spr_read_ureg, SPR_NOACCESS,
@@ -998,7 +998,7 @@ static void gen_spr_usprg3(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_usprgh(CPUPPCState *env)
+static void register_usprgh_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
&spr_read_ureg, SPR_NOACCESS,
@@ -1019,7 +1019,7 @@ static void gen_spr_usprgh(CPUPPCState *env)
}
/* PowerPC BookE SPR */
-static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
+static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
{
const char *ivor_names[64] = {
"IVOR0", "IVOR1", "IVOR2", "IVOR3",
@@ -1195,7 +1195,7 @@ static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
0x00000000);
}
-static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
+static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
uint32_t maxsize, uint32_t flags,
uint32_t nentries)
{
@@ -1206,7 +1206,7 @@ static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
}
/* BookE 2.06 storage control registers */
-static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
+static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
uint32_t *tlbncfg, uint32_t mmucfg)
{
#if !defined(CONFIG_USER_ONLY)
@@ -1294,11 +1294,11 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
}
#endif
- gen_spr_usprgh(env);
+ register_usprgh_sprs(env);
}
/* SPR specific to PowerPC 440 implementation */
-static void gen_spr_440(CPUPPCState *env)
+static void register_440_sprs(CPUPPCState *env)
{
/* Cache control */
/* XXX : not implemented */
@@ -1439,7 +1439,7 @@ static void gen_spr_440(CPUPPCState *env)
}
/* SPR shared between PowerPC 40x implementations */
-static void gen_spr_40x(CPUPPCState *env)
+static void register_40x_sprs(CPUPPCState *env)
{
/* Cache */
/* not emulated, as QEMU do not emulate caches */
@@ -1494,7 +1494,7 @@ static void gen_spr_40x(CPUPPCState *env)
}
/* SPR specific to PowerPC 405 implementation */
-static void gen_spr_405(CPUPPCState *env)
+static void register_405_sprs(CPUPPCState *env)
{
/* MMU */
spr_register(env, SPR_40x_PID, "PID",
@@ -1596,11 +1596,11 @@ static void gen_spr_405(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
- gen_spr_usprgh(env);
+ register_usprgh_sprs(env);
}
/* SPR shared between PowerPC 401 & 403 implementations */
-static void gen_spr_401_403(CPUPPCState *env)
+static void register_401_403_sprs(CPUPPCState *env)
{
/* Time base */
spr_register(env, SPR_403_VTBL, "TBL",
@@ -1628,7 +1628,7 @@ static void gen_spr_401_403(CPUPPCState *env)
}
/* SPR specific to PowerPC 401 implementation */
-static void gen_spr_401(CPUPPCState *env)
+static void register_401_sprs(CPUPPCState *env)
{
/* Debug interface */
/* XXX : not implemented */
@@ -1670,9 +1670,9 @@ static void gen_spr_401(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_401x2(CPUPPCState *env)
+static void register_401x2_sprs(CPUPPCState *env)
{
- gen_spr_401(env);
+ register_401_sprs(env);
spr_register(env, SPR_40x_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1684,7 +1684,7 @@ static void gen_spr_401x2(CPUPPCState *env)
}
/* SPR specific to PowerPC 403 implementation */
-static void gen_spr_403(CPUPPCState *env)
+static void register_403_sprs(CPUPPCState *env)
{
/* Debug interface */
/* XXX : not implemented */
@@ -1720,7 +1720,7 @@ static void gen_spr_403(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_403_real(CPUPPCState *env)
+static void register_403_real_sprs(CPUPPCState *env)
{
spr_register(env, SPR_403_PBL1, "PBL1",
SPR_NOACCESS, SPR_NOACCESS,
@@ -1740,7 +1740,7 @@ static void gen_spr_403_real(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_403_mmu(CPUPPCState *env)
+static void register_403_mmu_sprs(CPUPPCState *env)
{
/* MMU */
spr_register(env, SPR_40x_PID, "PID",
@@ -1754,7 +1754,7 @@ static void gen_spr_403_mmu(CPUPPCState *env)
}
/* SPR specific to PowerPC compression coprocessor extension */
-static void gen_spr_compress(CPUPPCState *env)
+static void register_compress_sprs(CPUPPCState *env)
{
/* XXX : not implemented */
spr_register(env, SPR_401_SKR, "SKR",
@@ -1763,7 +1763,7 @@ static void gen_spr_compress(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_5xx_8xx(CPUPPCState *env)
+static void register_5xx_8xx_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -1881,7 +1881,7 @@ static void gen_spr_5xx_8xx(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_5xx(CPUPPCState *env)
+static void register_5xx_sprs(CPUPPCState *env)
{
/* XXX : not implemented */
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
@@ -1990,7 +1990,7 @@ static void gen_spr_5xx(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_8xx(CPUPPCState *env)
+static void register_8xx_sprs(CPUPPCState *env)
{
/* XXX : not implemented */
spr_register(env, SPR_MPC_IC_CST, "IC_CST",
@@ -2725,9 +2725,9 @@ static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
static void init_proc_401(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401_sprs(env);
init_excp_4xx_real(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2771,10 +2771,10 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
static void init_proc_401x2(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401x2_sprs(env);
+ register_compress_sprs(env);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -2829,11 +2829,11 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
static void init_proc_401x3(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401_sprs(env);
+ register_401x2_sprs(env);
+ register_compress_sprs(env);
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2882,10 +2882,10 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
static void init_proc_IOP480(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401x2_sprs(env);
+ register_compress_sprs(env);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -2940,10 +2940,10 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
static void init_proc_403(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_403(env);
- gen_spr_403_real(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_403_sprs(env);
+ register_403_real_sprs(env);
init_excp_4xx_real(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2987,11 +2987,11 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
static void init_proc_403GCX(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_403(env);
- gen_spr_403_real(env);
- gen_spr_403_mmu(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_403_sprs(env);
+ register_403_real_sprs(env);
+ register_403_mmu_sprs(env);
/* Bus access control */
/* not emulated, as QEMU never does speculative access */
spr_register(env, SPR_40x_SGR, "SGR",
@@ -3055,9 +3055,9 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
static void init_proc_405(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_40x(env);
- gen_spr_405(env);
+ register_tbl(env);
+ register_40x_sprs(env);
+ register_405_sprs(env);
/* Bus access control */
/* not emulated, as QEMU never does speculative access */
spr_register(env, SPR_40x_SGR, "SGR",
@@ -3121,10 +3121,10 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
static void init_proc_440EP(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3263,10 +3263,10 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
static void init_proc_440GP(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3346,10 +3346,10 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
static void init_proc_440x4(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3429,10 +3429,10 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
static void init_proc_440x5(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3568,9 +3568,9 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
static void init_proc_MPC5xx(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_5xx_8xx(env);
- gen_spr_5xx(env);
+ register_tbl(env);
+ register_5xx_8xx_sprs(env);
+ register_5xx_sprs(env);
init_excp_MPC5xx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3612,9 +3612,9 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
static void init_proc_MPC8xx(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_5xx_8xx(env);
- gen_spr_8xx(env);
+ register_tbl(env);
+ register_5xx_8xx_sprs(env);
+ register_8xx_sprs(env);
init_excp_MPC8xx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3656,12 +3656,12 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
static void init_proc_G2(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_G2_755_sprs(env);
+ register_G2_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* External access control */
/* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
@@ -3685,9 +3685,9 @@ static void init_proc_G2(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_G2(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3735,12 +3735,12 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
static void init_proc_G2LE(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_G2_755_sprs(env);
+ register_G2_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* External access control */
/* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
@@ -3765,9 +3765,9 @@ static void init_proc_G2LE(CPUPPCState *env)
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_G2(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3818,15 +3818,15 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
static void init_proc_e200(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000070000FFFFULL);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000070000FFFFULL);
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
&spr_read_spefscr, &spr_write_spefscr,
&spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
- gen_spr_BookE206(env, 0x0000005D, NULL, 0);
+ register_BookE206_sprs(env, 0x0000005D, NULL, 0);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3972,11 +3972,11 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
static void init_proc_e300(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_603_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4020,9 +4020,9 @@ static void init_proc_e300(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4093,11 +4093,11 @@ static void init_proc_e500(CPUPPCState *env, int version)
#endif
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/*
* XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
* complain when accessing them.
- * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
*/
switch (version) {
case fsl_e500v1:
@@ -4113,8 +4113,8 @@ static void init_proc_e500(CPUPPCState *env, int version)
ivor_mask = 0x000003FF0000FFFFULL;
break;
}
- gen_spr_BookE(env, ivor_mask);
- gen_spr_usprg3(env);
+ register_BookE_sprs(env, ivor_mask);
+ register_usprg3_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4132,17 +4132,17 @@ static void init_proc_e500(CPUPPCState *env, int version)
env->id_tlbs = 0;
switch (version) {
case fsl_e500v1:
- tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
- tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
+ tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
break;
case fsl_e500v2:
- tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
- tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
break;
case fsl_e500mc:
case fsl_e5500:
- tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
- tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
+ tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
break;
case fsl_e6500:
mmucfg = 0x6510B45;
@@ -4179,7 +4179,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
env->spr[SPR_PVR]);
}
- gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
+ register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4537,9 +4537,9 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
static void init_proc_601(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_601(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_601_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4653,11 +4653,11 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
static void init_proc_602(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_602(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_602_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4670,8 +4670,8 @@ static void init_proc_602(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_602(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4723,11 +4723,11 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
static void init_proc_603(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_603_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4740,8 +4740,8 @@ static void init_proc_603(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4790,11 +4790,11 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
static void init_proc_603E(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_603_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4807,8 +4807,8 @@ static void init_proc_603E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4857,11 +4857,11 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
static void init_proc_604(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_604(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_604_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4869,7 +4869,7 @@ static void init_proc_604(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_604(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4921,9 +4921,9 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
static void init_proc_604E(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_604(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_604_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4940,7 +4940,7 @@ static void init_proc_604E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4953,7 +4953,7 @@ static void init_proc_604E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_604(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5005,13 +5005,13 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
static void init_proc_740(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5024,7 +5024,7 @@ static void init_proc_740(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_7x0(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5076,18 +5076,18 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
static void init_proc_750(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5100,7 +5100,7 @@ static void init_proc_750(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/*
* XXX: high BATs are also present but are known to be bugged on
* die version 1.x
@@ -5156,16 +5156,16 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
static void init_proc_750cl(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
/* Those registers are fake on 750CL */
spr_register(env, SPR_THRM1, "THRM1",
@@ -5266,9 +5266,9 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750cl has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_750cl(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5359,18 +5359,18 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
static void init_proc_750cx(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* This register is not implemented but is present for compatibility */
spr_register(env, SPR_SDA, "SDA",
SPR_NOACCESS, SPR_NOACCESS,
@@ -5388,9 +5388,9 @@ static void init_proc_750cx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750cx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_750cx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5442,18 +5442,18 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
static void init_proc_750fx(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
@@ -5476,9 +5476,9 @@ static void init_proc_750fx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_7x0(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5530,18 +5530,18 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
static void init_proc_750gx(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented (XXX: different from 750fx) */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
@@ -5564,9 +5564,9 @@ static void init_proc_750gx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_7x0(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5618,14 +5618,14 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
static void init_proc_745(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- gen_spr_G2_755(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
+ register_G2_755_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5643,9 +5643,9 @@ static void init_proc_745(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_7x5(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5694,12 +5694,12 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
static void init_proc_755(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- gen_spr_G2_755(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
+ register_G2_755_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* L2 cache control */
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
@@ -5712,7 +5712,7 @@ static void init_proc_755(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5730,9 +5730,9 @@ static void init_proc_755(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_7x5(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5781,13 +5781,13 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
static void init_proc_7400(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -5801,9 +5801,9 @@ static void init_proc_7400(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_7400(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5861,13 +5861,13 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
static void init_proc_7410(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -5875,7 +5875,7 @@ static void init_proc_7410(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* L2PMCR */
/* XXX : not implemented */
spr_register(env, SPR_L2PMCR, "L2PMCR",
@@ -5889,7 +5889,7 @@ static void init_proc_7410(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_7400(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5947,13 +5947,13 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
static void init_proc_7440(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -6000,8 +6000,8 @@ static void init_proc_7440(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6056,16 +6056,16 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
static void init_proc_7450(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
- gen_l3_ctrl(env);
+ register_l3_ctrl(env);
/* L3ITCR1 */
/* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
@@ -6135,8 +6135,8 @@ static void init_proc_7450(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6191,13 +6191,13 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
static void init_proc_7445(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* LDSTCR */
/* XXX : not implemented */
@@ -6272,9 +6272,9 @@ static void init_proc_7445(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6329,16 +6329,16 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
static void init_proc_7455(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
- gen_l3_ctrl(env);
+ register_l3_ctrl(env);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
@@ -6412,9 +6412,9 @@ static void init_proc_7455(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6469,16 +6469,16 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
static void init_proc_7457(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
- gen_l3_ctrl(env);
+ register_l3_ctrl(env);
/* L3ITCR1 */
/* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
@@ -6576,9 +6576,9 @@ static void init_proc_7457(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6633,13 +6633,13 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
static void init_proc_e600(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -6715,9 +6715,9 @@ static void init_proc_e600(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6790,7 +6790,7 @@ static int check_pow_970(CPUPPCState *env)
return 0;
}
-static void gen_spr_970_hid(CPUPPCState *env)
+static void register_970_hid_sprs(CPUPPCState *env)
{
/* Hardware implementation registers */
/* XXX : not implemented */
@@ -6808,7 +6808,7 @@ static void gen_spr_970_hid(CPUPPCState *env)
POWERPC970_HID5_INIT);
}
-static void gen_spr_970_hior(CPUPPCState *env)
+static void register_970_hior_sprs(CPUPPCState *env)
{
spr_register(env, SPR_HIOR, "SPR_HIOR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6816,7 +6816,7 @@ static void gen_spr_970_hior(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_ctrl(CPUPPCState *env)
+static void register_book3s_ctrl_sprs(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6828,7 +6828,7 @@ static void gen_spr_book3s_ctrl(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_altivec(CPUPPCState *env)
+static void register_book3s_altivec_sprs(CPUPPCState *env)
{
if (!(env->insns_flags & PPC_ALTIVEC)) {
return;
@@ -6841,7 +6841,7 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
}
-static void gen_spr_book3s_dbg(CPUPPCState *env)
+static void register_book3s_dbg_sprs(CPUPPCState *env)
{
/*
* TODO: different specs define different scopes for these,
@@ -6860,7 +6860,7 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
KVM_REG_PPC_DABRX, 0x00000000);
}
-static void gen_spr_book3s_207_dbg(CPUPPCState *env)
+static void register_book3s_207_dbg_sprs(CPUPPCState *env)
{
spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6879,7 +6879,7 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
KVM_REG_PPC_CIABR, 0x00000000);
}
-static void gen_spr_970_dbg(CPUPPCState *env)
+static void register_970_dbg_sprs(CPUPPCState *env)
{
/* Breakpoints */
spr_register(env, SPR_IABR, "IABR",
@@ -6888,7 +6888,7 @@ static void gen_spr_970_dbg(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
+static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6936,7 +6936,7 @@ static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
KVM_REG_PPC_SDAR, 0x00000000);
}
-static void gen_spr_book3s_pmu_user(CPUPPCState *env)
+static void register_book3s_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
&spr_read_ureg, SPR_NOACCESS,
@@ -6984,7 +6984,7 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_970_pmu_sup(CPUPPCState *env)
+static void register_970_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_970_PMC7, "PMC7",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6996,7 +6996,7 @@ static void gen_spr_970_pmu_sup(CPUPPCState *env)
KVM_REG_PPC_PMC8, 0x00000000);
}
-static void gen_spr_970_pmu_user(CPUPPCState *env)
+static void register_970_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_970_UPMC7, "UPMC7",
&spr_read_ureg, SPR_NOACCESS,
@@ -7008,7 +7008,7 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power8_pmu_sup(CPUPPCState *env)
+static void register_power8_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7044,7 +7044,7 @@ static void gen_spr_power8_pmu_sup(CPUPPCState *env)
KVM_REG_PPC_CSIGR, 0x00000000);
}
-static void gen_spr_power8_pmu_user(CPUPPCState *env)
+static void register_power8_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
&spr_read_ureg, SPR_NOACCESS,
@@ -7056,7 +7056,7 @@ static void gen_spr_power8_pmu_user(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power5p_ear(CPUPPCState *env)
+static void register_power5p_ear_sprs(CPUPPCState *env)
{
/* External access control */
spr_register(env, SPR_EAR, "EAR",
@@ -7065,7 +7065,7 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power5p_tb(CPUPPCState *env)
+static void register_power5p_tb_sprs(CPUPPCState *env)
{
/* TBU40 (High 40 bits of the Timebase register */
spr_register_hv(env, SPR_TBU40, "TBU40",
@@ -7075,7 +7075,7 @@ static void gen_spr_power5p_tb(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_970_lpar(CPUPPCState *env)
+static void register_970_lpar_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/*
@@ -7092,7 +7092,7 @@ static void gen_spr_970_lpar(CPUPPCState *env)
#endif
}
-static void gen_spr_power5p_lpar(CPUPPCState *env)
+static void register_power5p_lpar_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* Logical partitionning */
@@ -7108,7 +7108,7 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
#endif
}
-static void gen_spr_book3s_ids(CPUPPCState *env)
+static void register_book3s_ids_sprs(CPUPPCState *env)
{
/* FIXME: Will need to deal with thread vs core only SPRs */
@@ -7200,7 +7200,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_rmor(CPUPPCState *env)
+static void register_rmor_sprs(CPUPPCState *env)
{
spr_register_hv(env, SPR_RMOR, "RMOR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7209,7 +7209,7 @@ static void gen_spr_rmor(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power8_ids(CPUPPCState *env)
+static void register_power8_ids_sprs(CPUPPCState *env)
{
/* Thread identification */
spr_register(env, SPR_TIR, "TIR",
@@ -7218,7 +7218,7 @@ static void gen_spr_power8_ids(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_purr(CPUPPCState *env)
+static void register_book3s_purr_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
@@ -7235,7 +7235,7 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
#endif
}
-static void gen_spr_power6_dbg(CPUPPCState *env)
+static void register_power6_dbg_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_CFAR, "SPR_CFAR",
@@ -7245,7 +7245,7 @@ static void gen_spr_power6_dbg(CPUPPCState *env)
#endif
}
-static void gen_spr_power5p_common(CPUPPCState *env)
+static void register_power5p_common_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_PPR, "PPR",
&spr_read_generic, &spr_write_generic,
@@ -7253,7 +7253,7 @@ static void gen_spr_power5p_common(CPUPPCState *env)
KVM_REG_PPC_PPR, 0x00000000);
}
-static void gen_spr_power6_common(CPUPPCState *env)
+static void register_power6_common_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
@@ -7272,7 +7272,7 @@ static void gen_spr_power6_common(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power8_tce_address_control(CPUPPCState *env)
+static void register_power8_tce_address_control_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TAR, "TAR",
&spr_read_tar, &spr_write_tar,
@@ -7280,7 +7280,7 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
KVM_REG_PPC_TAR, 0x00000000);
}
-static void gen_spr_power8_tm(CPUPPCState *env)
+static void register_power8_tm_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TFHAR, "TFHAR",
&spr_read_tm, &spr_write_tm,
@@ -7300,7 +7300,7 @@ static void gen_spr_power8_tm(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power8_ebb(CPUPPCState *env)
+static void register_power8_ebb_sprs(CPUPPCState *env)
{
spr_register(env, SPR_BESCRS, "BESCRS",
&spr_read_ebb, &spr_write_ebb,
@@ -7333,7 +7333,7 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
}
/* Virtual Time Base */
-static void gen_spr_vtb(CPUPPCState *env)
+static void register_vtb_sprs(CPUPPCState *env)
{
spr_register_kvm_hv(env, SPR_VTB, "VTB",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7342,7 +7342,7 @@ static void gen_spr_vtb(CPUPPCState *env)
KVM_REG_PPC_VTB, 0x00000000);
}
-static void gen_spr_power8_fscr(CPUPPCState *env)
+static void register_power8_fscr_sprs(CPUPPCState *env)
{
#if defined(CONFIG_USER_ONLY)
target_ulong initval = 1ULL << FSCR_TAR;
@@ -7355,7 +7355,7 @@ static void gen_spr_power8_fscr(CPUPPCState *env)
KVM_REG_PPC_FSCR, initval);
}
-static void gen_spr_power8_pspb(CPUPPCState *env)
+static void register_power8_pspb_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_PSPB, "PSPB",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7363,7 +7363,7 @@ static void gen_spr_power8_pspb(CPUPPCState *env)
KVM_REG_PPC_PSPB, 0);
}
-static void gen_spr_power8_dpdes(CPUPPCState *env)
+static void register_power8_dpdes_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* Directed Privileged Door-bell Exception State, used for IPI */
@@ -7375,7 +7375,7 @@ static void gen_spr_power8_dpdes(CPUPPCState *env)
#endif
}
-static void gen_spr_power8_ic(CPUPPCState *env)
+static void register_power8_ic_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register_hv(env, SPR_IC, "IC",
@@ -7386,7 +7386,7 @@ static void gen_spr_power8_ic(CPUPPCState *env)
#endif
}
-static void gen_spr_power8_book4(CPUPPCState *env)
+static void register_power8_book4_sprs(CPUPPCState *env)
{
/* Add a number of P8 book4 registers */
#if !defined(CONFIG_USER_ONLY)
@@ -7405,7 +7405,7 @@ static void gen_spr_power8_book4(CPUPPCState *env)
#endif
}
-static void gen_spr_power7_book4(CPUPPCState *env)
+static void register_power7_book4_sprs(CPUPPCState *env)
{
/* Add a number of P7 book4 registers */
#if !defined(CONFIG_USER_ONLY)
@@ -7420,7 +7420,7 @@ static void gen_spr_power7_book4(CPUPPCState *env)
#endif
}
-static void gen_spr_power8_rpr(CPUPPCState *env)
+static void register_power8_rpr_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register_hv(env, SPR_RPR, "RPR",
@@ -7431,7 +7431,7 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
#endif
}
-static void gen_spr_power9_mmu(CPUPPCState *env)
+static void register_power9_mmu_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* Partition Table Control */
@@ -7451,13 +7451,13 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_tbl(env);
- gen_spr_usprg3(env);
- gen_spr_book3s_altivec(env);
- gen_spr_book3s_pmu_sup(env);
- gen_spr_book3s_pmu_user(env);
- gen_spr_book3s_ctrl(env);
+ register_ne_601_sprs(env);
+ register_tbl(env);
+ register_usprg3_sprs(env);
+ register_book3s_altivec_sprs(env);
+ register_book3s_pmu_sup_sprs(env);
+ register_book3s_pmu_user_sprs(env);
+ register_book3s_ctrl_sprs(env);
/*
* Can't find information on what this should be on reset. This
* value is the one used by 74xx processors.
@@ -7469,17 +7469,17 @@ static void init_proc_970(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_dbg_sprs(env);
/* 970 Specific Registers */
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
- gen_spr_970_pmu_sup(env);
- gen_spr_970_pmu_user(env);
- gen_spr_970_lpar(env);
- gen_spr_970_dbg(env);
+ register_970_hid_sprs(env);
+ register_970_hior_sprs(env);
+ register_low_BATs(env);
+ register_970_pmu_sup_sprs(env);
+ register_970_pmu_user_sprs(env);
+ register_970_lpar_sprs(env);
+ register_970_dbg_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -7542,19 +7542,19 @@ static void init_proc_power5plus(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_dbg_sprs(env);
/* POWER5+ Specific Registers */
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
- gen_spr_970_pmu_sup(env);
- gen_spr_970_pmu_user(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
+ register_970_hid_sprs(env);
+ register_970_hior_sprs(env);
+ register_low_BATs(env);
+ register_970_pmu_sup_sprs(env);
+ register_970_pmu_user_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -7621,21 +7621,21 @@ static void init_proc_POWER7(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_dbg_sprs(env);
/* POWER7 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_rmor(env);
- gen_spr_amr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power7_book4(env);
+ register_book3s_ids_sprs(env);
+ register_rmor_sprs(env);
+ register_amr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power7_book4_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -7767,34 +7767,34 @@ static void init_proc_POWER8(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_207_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_207_dbg_sprs(env);
/* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_rmor(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_power8_dpdes(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
+ register_book3s_ids_sprs(env);
+ register_rmor_sprs(env);
+ register_amr_sprs(env);
+ register_iamr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power8_tce_address_control_sprs(env);
+ register_power8_ids_sprs(env);
+ register_power8_ebb_sprs(env);
+ register_power8_fscr_sprs(env);
+ register_power8_pmu_sup_sprs(env);
+ register_power8_pmu_user_sprs(env);
+ register_power8_tm_sprs(env);
+ register_power8_pspb_sprs(env);
+ register_power8_dpdes_sprs(env);
+ register_vtb_sprs(env);
+ register_power8_ic_sprs(env);
+ register_power8_book4_sprs(env);
+ register_power8_rpr_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -7964,33 +7964,33 @@ static void init_proc_POWER9(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_book3s_207_dbg(env);
+ register_book3s_207_dbg_sprs(env);
/* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_power8_dpdes(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
- gen_spr_power9_mmu(env);
+ register_book3s_ids_sprs(env);
+ register_amr_sprs(env);
+ register_iamr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power8_tce_address_control_sprs(env);
+ register_power8_ids_sprs(env);
+ register_power8_ebb_sprs(env);
+ register_power8_fscr_sprs(env);
+ register_power8_pmu_sup_sprs(env);
+ register_power8_pmu_user_sprs(env);
+ register_power8_tm_sprs(env);
+ register_power8_pspb_sprs(env);
+ register_power8_dpdes_sprs(env);
+ register_vtb_sprs(env);
+ register_power8_ic_sprs(env);
+ register_power8_book4_sprs(env);
+ register_power8_rpr_sprs(env);
+ register_power9_mmu_sprs(env);
/* POWER9 Specific registers */
spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
@@ -8182,31 +8182,31 @@ static void init_proc_POWER10(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_book3s_207_dbg(env);
+ register_book3s_207_dbg_sprs(env);
/* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
- gen_spr_power9_mmu(env);
+ register_book3s_ids_sprs(env);
+ register_amr_sprs(env);
+ register_iamr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power8_tce_address_control_sprs(env);
+ register_power8_ids_sprs(env);
+ register_power8_ebb_sprs(env);
+ register_power8_fscr_sprs(env);
+ register_power8_pmu_sup_sprs(env);
+ register_power8_pmu_user_sprs(env);
+ register_power8_tm_sprs(env);
+ register_power8_pspb_sprs(env);
+ register_vtb_sprs(env);
+ register_power8_ic_sprs(env);
+ register_power8_book4_sprs(env);
+ register_power8_rpr_sprs(env);
+ register_power9_mmu_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
@@ -8411,7 +8411,7 @@ static void init_ppc_proc(PowerPCCPU *cpu)
env->tlb_type = TLB_NONE;
#endif
/* Register SPR common to all PowerPC implementations */
- gen_spr_generic(env);
+ register_generic_sprs(env);
spr_register(env, SPR_PVR, "PVR",
/* Linux permits userspace to read PVR */
#if defined(CONFIG_LINUX_USER)
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
` (5 preceding siblings ...)
2021-04-30 19:35 ` [PATCH v3 6/7] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
@ 2021-04-30 19:35 ` Bruno Larsen (billionai)
2021-05-01 1:11 ` Richard Henderson
6 siblings, 1 reply; 25+ messages in thread
From: Bruno Larsen (billionai) @ 2021-04-30 19:35 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
finished isolation of CPU initialization logic from
translation logic. CPU initialization now only has common code
and may or may not call accelerator-specific code, as the
build options require.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/{translate_init.c.inc => cpu_init.c} | 4 ++++
target/ppc/meson.build | 1 +
target/ppc/translate.c | 3 ++-
3 files changed, 7 insertions(+), 1 deletion(-)
rename target/ppc/{translate_init.c.inc => cpu_init.c} (99%)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/cpu_init.c
similarity index 99%
rename from target/ppc/translate_init.c.inc
rename to target/ppc/cpu_init.c
index 274bd884a1..beb4a11841 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/cpu_init.c
@@ -18,6 +18,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "disas/dis-asm.h"
#include "exec/gdbstub.h"
#include "kvm_ppc.h"
@@ -42,7 +43,10 @@
#include "fpu/softfloat.h"
#include "qapi/qapi-commands-machine-target.h"
+#include "helper_regs.h"
+#include "internal.h"
#include "spr_tcg.h"
+
/* #define PPC_DEBUG_SPR */
/* #define USE_APPLE_GDB */
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index bbfef90e08..ad53629298 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -2,6 +2,7 @@ ppc_ss = ss.source_set()
ppc_ss.add(files(
'cpu-models.c',
'cpu.c',
+ 'cpu_init.c',
'dfp_helper.c',
'excp_helper.c',
'fpu_helper.c',
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index dba112087e..8774ad798b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -37,6 +37,8 @@
#include "exec/log.h"
#include "qemu/atomic128.h"
+#include "qemu/qemu-print.h"
+#include "qapi/error.h"
#define CPU_SINGLE_STEP 0x1
#define CPU_BRANCH_STEP 0x2
@@ -7594,7 +7596,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
#include "helper_regs.h"
#include "spr_tcg.c.inc"
-#include "translate_init.c.inc"
/*****************************************************************************/
/* Misc PowerPC helpers */
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro
2021-04-30 19:35 ` [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro Bruno Larsen (billionai)
@ 2021-05-01 0:27 ` Richard Henderson
2021-05-03 4:37 ` David Gibson
0 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2021-05-01 0:27 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
[-- Attachment #1: Type: text/plain, Size: 3485 bytes --]
On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> moved RW callback parameters of _spr_register into an ifdef, to support
> building without TCG in the future, and added definitions for
> spr_register and spr_register_kvm, to keep the same call regardless of
> build options
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> ---
> target/ppc/translate_init.c.inc | 26 +++++++++++++++++++++-----
> 1 file changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index 6235eb7536..22b23793fd 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -720,6 +720,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> helper_mtvscr(env, val);
> }
>
> +#ifdef CONFIG_TCG
> #ifdef CONFIG_USER_ONLY
> #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, one_reg_id, initial_value) \
> @@ -728,7 +729,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> oea_read, oea_write, hea_read, hea_write, \
> one_reg_id, initial_value) \
> _spr_register(env, num, name, uea_read, uea_write, initial_value)
> -#else
> +#else /* CONFIG_USER_ONLY */
> #if !defined(CONFIG_KVM)
> #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, one_reg_id, initial_value) \
> @@ -739,7 +740,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> one_reg_id, initial_value) \
> _spr_register(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, hea_read, hea_write, initial_value)
> -#else
> +#else /* CONFIG_KVM */
> #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, one_reg_id, initial_value) \
> _spr_register(env, num, name, uea_read, uea_write, \
> @@ -751,8 +752,21 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> _spr_register(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, hea_read, hea_write, \
> one_reg_id, initial_value)
> -#endif
> -#endif
> +#endif /* CONFIG_KVM */
> +#endif /* CONFIG_USER_ONLY */
> +#else /* CONFIG_TCG */
> +#ifdef CONFIG_KVM /* sanity check. should always enter this */
> +#define spr_register_kvm(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, one_reg_id, initial_value) \
> + _spr_register(env, num, name, one_reg_id, initial_value)
> +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, hea_read, hea_write, \
> + one_reg_id, initial_value) \
> + _spr_register(env, num, name, one_reg_id, initial_value)
> +#else /* CONFIG_KVM */
> +#error "Either TCG or KVM should be configured"
> +#endif /* CONFIG_KVM */
> +#endif /* CONFIG_TCG */
I think this ifdef tree, and the repetition, is unnecessarily confusing. How
about something like this?
r~
[-- Attachment #2: patch.txt --]
[-- Type: text/plain, Size: 4120 bytes --]
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 22b23793fd..1e1539f929 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -721,52 +721,34 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
}
#ifdef CONFIG_TCG
-#ifdef CONFIG_USER_ONLY
+# define U(X) X,
+# ifndef CONFIG_USER_ONLY
+# define S(X) X,
+# else
+# define S(X)
+# endif
+#else
+# define U(X)
+# define S(X)
+#endif
+#ifdef CONFIG_KVM
+# define K(X) X,
+#else
+# define K(X)
+#endif
+
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, initial_value)
+ _spr_register(env, num, name, U(uea_read) U(uea_write) \
+ S(oea_read) S(oea_write) S(oea_read) S(oea_write) \
+ K(one_reg_id) initial_value)
+
#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
oea_read, oea_write, hea_read, hea_write, \
one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, initial_value)
-#else /* CONFIG_USER_ONLY */
-#if !defined(CONFIG_KVM)
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, oea_read, oea_write, initial_value)
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, initial_value)
-#else /* CONFIG_KVM */
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, oea_read, oea_write, \
- one_reg_id, initial_value)
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value)
-#endif /* CONFIG_KVM */
-#endif /* CONFIG_USER_ONLY */
-#else /* CONFIG_TCG */
-#ifdef CONFIG_KVM /* sanity check. should always enter this */
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
- _spr_register(env, num, name, one_reg_id, initial_value)
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, one_reg_id, initial_value)
-#else /* CONFIG_KVM */
-#error "Either TCG or KVM should be configured"
-#endif /* CONFIG_KVM */
-#endif /* CONFIG_TCG */
+ _spr_register(env, num, name, U(uea_read) U(uea_write) \
+ S(oea_read) S(oea_write) S(hea_read) S(hea_write) \
+ K(one_reg_id) initial_value)
#define spr_register(env, num, name, uea_read, uea_write, \
oea_read, oea_write, initial_value) \
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks
2021-04-30 19:35 ` [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks Bruno Larsen (billionai)
@ 2021-05-01 0:55 ` Richard Henderson
2021-05-03 20:07 ` Bruno Piazera Larsen
2021-05-03 4:54 ` David Gibson
1 sibling, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2021-05-01 0:55 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> Moved all SPR read/write callback, and some related functions, to a
> new file specific for it. These callbacks are TCG only, so separating
> them is required to support the build flag disable-tcg.
>
> Making the spr_noaccess function not static, and moving the define to
> internal.h is required, otherwise the project doesn't build
Why is that? You're moving the code to a different file, but then including
that file back into the same translation unit. There should be no change in
which symbols appear in which object file.
I think that the spr_noaccess move might be required by patch 7, but that's
something different.
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions
2021-04-30 19:35 ` [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions Bruno Larsen (billionai)
@ 2021-05-01 0:58 ` Richard Henderson
2021-05-03 4:39 ` David Gibson
0 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2021-05-01 0:58 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> Removed functions gen_read_xer and gen_write_xer, moving their logic
> directly into spr_read_xer and spr_write_xer, respectively.
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> ---
"Unnecessary" makes me believe that the code isn't used at all.
A better description for this patch is
---
target/ppc: Fold gen_{read,write}_xer into spr_{read,write}_xer
Fold these functions into their single caller.
---
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static
2021-04-30 19:35 ` [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
@ 2021-05-01 1:05 ` Richard Henderson
2021-05-03 11:28 ` Bruno Piazera Larsen
0 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2021-05-01 1:05 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> +++ b/target/ppc/spr_tcg.c.inc
> @@ -17,6 +17,8 @@
> * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> */
>
> +#include "spr_tcg.h"
...
> +++ b/target/ppc/translate_init.c.inc
> @@ -42,6 +42,7 @@
> #include "fpu/softfloat.h"
> #include "qapi/qapi-commands-machine-target.h"
>
> +#include "spr_tcg.h"
> /* #define PPC_DEBUG_SPR */
> /* #define USE_APPLE_GDB */
Including this header twice, in files that are themselves both included in
translate.c, is sketchy. You really shouldn't add the one to
translate_init.c.inc until patch 7, when it becomes the standalone cpu_init.c.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Note for future cleanup: Make spr_tcg.c be standalone as well. Just need to
move a few declarations to a translate.h.
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration
2021-04-30 19:35 ` [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration Bruno Larsen (billionai)
@ 2021-05-01 1:06 ` Richard Henderson
2021-05-03 4:47 ` David Gibson
1 sibling, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2021-05-01 1:06 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> Since vscr is not an spr, its initialization was removed from the
> spr registration functions, and moved to the relevant init_procs.
>
> We may look into adding vscr to the reset path instead of the init
> path (as suggested by David Gibson), but this looked like a good
> enough solution for now.
>
> Signed-off-by: Bruno Larsen (billionai)<bruno.larsen@eldorado.org.br>
> ---
> target/ppc/translate_init.c.inc | 20 +++++++++++++-------
> 1 file changed, 13 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic
2021-04-30 19:35 ` [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
@ 2021-05-01 1:11 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2021-05-01 1:11 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> +++ b/target/ppc/cpu_init.c
> @@ -18,6 +18,7 @@
> * License along with this library; if not, see<http://www.gnu.org/licenses/>.
> */
>
> +#include "qemu/osdep.h"
> #include "disas/dis-asm.h"
> #include "exec/gdbstub.h"
> #include "kvm_ppc.h"
> @@ -42,7 +43,10 @@
> #include "fpu/softfloat.h"
> #include "qapi/qapi-commands-machine-target.h"
>
> +#include "helper_regs.h"
> +#include "internal.h"
> #include "spr_tcg.h"
You need "exec/helper-proto.h" until you deal with helper_mtvscr().
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro
2021-05-01 0:27 ` Richard Henderson
@ 2021-05-03 4:37 ` David Gibson
0 siblings, 0 replies; 25+ messages in thread
From: David Gibson @ 2021-05-03 4:37 UTC (permalink / raw)
To: Richard Henderson
Cc: farosas, qemu-devel, lucas.araujo, fernando.valle, qemu-ppc,
Bruno Larsen (billionai),
matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 4041 bytes --]
On Fri, Apr 30, 2021 at 05:27:13PM -0700, Richard Henderson wrote:
> On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> > moved RW callback parameters of _spr_register into an ifdef, to support
> > building without TCG in the future, and added definitions for
> > spr_register and spr_register_kvm, to keep the same call regardless of
> > build options
> >
> > Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> > ---
> > target/ppc/translate_init.c.inc | 26 +++++++++++++++++++++-----
> > 1 file changed, 21 insertions(+), 5 deletions(-)
> >
> > diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> > index 6235eb7536..22b23793fd 100644
> > --- a/target/ppc/translate_init.c.inc
> > +++ b/target/ppc/translate_init.c.inc
> > @@ -720,6 +720,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> > helper_mtvscr(env, val);
> > }
> > +#ifdef CONFIG_TCG
> > #ifdef CONFIG_USER_ONLY
> > #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> > oea_read, oea_write, one_reg_id, initial_value) \
> > @@ -728,7 +729,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> > oea_read, oea_write, hea_read, hea_write, \
> > one_reg_id, initial_value) \
> > _spr_register(env, num, name, uea_read, uea_write, initial_value)
> > -#else
> > +#else /* CONFIG_USER_ONLY */
> > #if !defined(CONFIG_KVM)
> > #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> > oea_read, oea_write, one_reg_id, initial_value) \
> > @@ -739,7 +740,7 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> > one_reg_id, initial_value) \
> > _spr_register(env, num, name, uea_read, uea_write, \
> > oea_read, oea_write, hea_read, hea_write, initial_value)
> > -#else
> > +#else /* CONFIG_KVM */
> > #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> > oea_read, oea_write, one_reg_id, initial_value) \
> > _spr_register(env, num, name, uea_read, uea_write, \
> > @@ -751,8 +752,21 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
> > _spr_register(env, num, name, uea_read, uea_write, \
> > oea_read, oea_write, hea_read, hea_write, \
> > one_reg_id, initial_value)
> > -#endif
> > -#endif
> > +#endif /* CONFIG_KVM */
> > +#endif /* CONFIG_USER_ONLY */
> > +#else /* CONFIG_TCG */
> > +#ifdef CONFIG_KVM /* sanity check. should always enter this */
> > +#define spr_register_kvm(env, num, name, uea_read, uea_write, \
> > + oea_read, oea_write, one_reg_id, initial_value) \
> > + _spr_register(env, num, name, one_reg_id, initial_value)
> > +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
> > + oea_read, oea_write, hea_read, hea_write, \
> > + one_reg_id, initial_value) \
> > + _spr_register(env, num, name, one_reg_id, initial_value)
> > +#else /* CONFIG_KVM */
> > +#error "Either TCG or KVM should be configured"
> > +#endif /* CONFIG_KVM */
> > +#endif /* CONFIG_TCG */
>
> I think this ifdef tree, and the repetition, is unnecessarily confusing.
> How about something like this?
I've applied Richard's version of this to my tree now, so you might
need to rebase the rest of the series.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions
2021-05-01 0:58 ` Richard Henderson
@ 2021-05-03 4:39 ` David Gibson
0 siblings, 0 replies; 25+ messages in thread
From: David Gibson @ 2021-05-03 4:39 UTC (permalink / raw)
To: Richard Henderson
Cc: farosas, qemu-devel, lucas.araujo, fernando.valle, qemu-ppc,
Bruno Larsen (billionai),
matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 1158 bytes --]
On Fri, Apr 30, 2021 at 05:58:46PM -0700, Richard Henderson wrote:
> On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> > Removed functions gen_read_xer and gen_write_xer, moving their logic
> > directly into spr_read_xer and spr_write_xer, respectively.
> >
> > Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> > ---
>
> "Unnecessary" makes me believe that the code isn't used at all.
> A better description for this patch is
>
> ---
> target/ppc: Fold gen_{read,write}_xer into spr_{read,write}_xer
>
> Fold these functions into their single caller.
> ---
Agreed.
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This one looks good to me now, whereas I still need to think about the
rest of the code motion here. So, could you move this earlier in the
series, before the creation of spr_tcg.inc.c, so I can go ahead and
apply it while we continue discussing the rest.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration
2021-04-30 19:35 ` [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration Bruno Larsen (billionai)
2021-05-01 1:06 ` Richard Henderson
@ 2021-05-03 4:47 ` David Gibson
1 sibling, 0 replies; 25+ messages in thread
From: David Gibson @ 2021-05-03 4:47 UTC (permalink / raw)
To: Bruno Larsen (billionai)
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
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On Fri, Apr 30, 2021 at 04:35:31PM -0300, Bruno Larsen (billionai) wrote:
> Since vscr is not an spr, its initialization was removed from the
> spr registration functions, and moved to the relevant init_procs.
>
> We may look into adding vscr to the reset path instead of the init
> path (as suggested by David Gibson), but this looked like a good
> enough solution for now.
>
> Signed-off-by: Bruno Larsen (billionai)
> <bruno.larsen@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate_init.c.inc | 20 +++++++++++++-------
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index 67529e8648..b922b04f25 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -941,8 +941,6 @@ static void gen_spr_74xx(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> - /* Not strictly an SPR */
> - vscr_init(env, 0x00010000);
> }
>
> static void gen_l3_ctrl(CPUPPCState *env)
> @@ -5790,6 +5788,7 @@ static void init_proc_7400(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -5869,6 +5868,7 @@ static void init_proc_7410(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -5954,6 +5954,7 @@ static void init_proc_7440(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -6062,6 +6063,7 @@ static void init_proc_7450(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> gen_l3_ctrl(env);
> /* L3ITCR1 */
> @@ -6196,6 +6198,7 @@ static void init_proc_7445(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* LDSTCR */
> /* XXX : not implemented */
> spr_register(env, SPR_LDSTCR, "LDSTCR",
> @@ -6333,6 +6336,7 @@ static void init_proc_7455(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> gen_l3_ctrl(env);
> /* LDSTCR */
> @@ -6472,6 +6476,7 @@ static void init_proc_7457(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> gen_l3_ctrl(env);
> /* L3ITCR1 */
> @@ -6635,6 +6640,7 @@ static void init_proc_e600(CPUPPCState *env)
> gen_tbl(env);
> /* 74xx specific SPR */
> gen_spr_74xx(env);
> + vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -6833,11 +6839,6 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_VRSAVE, 0x00000000);
>
> - /*
> - * Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors.
> - */
> - vscr_init(env, 0x00010000);
> }
>
> static void gen_spr_book3s_dbg(CPUPPCState *env)
> @@ -7457,6 +7458,11 @@ static void init_proc_book3s_common(CPUPPCState *env)
> gen_spr_book3s_pmu_sup(env);
> gen_spr_book3s_pmu_user(env);
> gen_spr_book3s_ctrl(env);
> + /*
> + * Can't find information on what this should be on reset. This
> + * value is the one used by 74xx processors.
> + */
> + vscr_init(env, 0x00010000);
> }
>
> static void init_proc_970(CPUPPCState *env)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 6/7] target/ppc: renamed SPR registration functions
2021-04-30 19:35 ` [PATCH v3 6/7] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
@ 2021-05-03 4:49 ` David Gibson
0 siblings, 0 replies; 25+ messages in thread
From: David Gibson @ 2021-05-03 4:49 UTC (permalink / raw)
To: Bruno Larsen (billionai)
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 73673 bytes --]
On Fri, Apr 30, 2021 at 04:35:32PM -0300, Bruno Larsen (billionai) wrote:
> Renamed all gen_spr_* and gen_* functions specifically related to
> registering SPRs to register_*_sprs and register_*, to avoid future
> confusion with other TCG related code.
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This one also makes sense to be regardless of the rest. Can you move
this before the creation of spr_tcg.inc.c, so we can get it merged.
> ---
> target/ppc/translate_init.c.inc | 860 ++++++++++++++++----------------
> 1 file changed, 430 insertions(+), 430 deletions(-)
>
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index b922b04f25..274bd884a1 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -168,7 +168,7 @@ static inline void _spr_register(CPUPPCState *env, int num,
> }
>
> /* Generic PowerPC SPRs */
> -static void gen_spr_generic(CPUPPCState *env)
> +static void register_generic_sprs(CPUPPCState *env)
> {
> /* Integer processing */
> spr_register(env, SPR_XER, "XER",
> @@ -213,7 +213,7 @@ static void gen_spr_generic(CPUPPCState *env)
> }
>
> /* SPR common to all non-embedded PowerPC, including 601 */
> -static void gen_spr_ne_601(CPUPPCState *env)
> +static void register_ne_601_sprs(CPUPPCState *env)
> {
> /* Exception processing */
> spr_register_kvm(env, SPR_DSISR, "DSISR",
> @@ -232,7 +232,7 @@ static void gen_spr_ne_601(CPUPPCState *env)
> }
>
> /* Storage Description Register 1 */
> -static void gen_spr_sdr1(CPUPPCState *env)
> +static void register_sdr1_sprs(CPUPPCState *env)
> {
> #ifndef CONFIG_USER_ONLY
> if (env->has_hv_mode) {
> @@ -255,7 +255,7 @@ static void gen_spr_sdr1(CPUPPCState *env)
> }
>
> /* BATs 0-3 */
> -static void gen_low_BATs(CPUPPCState *env)
> +static void register_low_BATs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register(env, SPR_IBAT0U, "IBAT0U",
> @@ -327,7 +327,7 @@ static void gen_low_BATs(CPUPPCState *env)
> }
>
> /* BATs 4-7 */
> -static void gen_high_BATs(CPUPPCState *env)
> +static void register_high_BATs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register(env, SPR_IBAT4U, "IBAT4U",
> @@ -399,7 +399,7 @@ static void gen_high_BATs(CPUPPCState *env)
> }
>
> /* Generic PowerPC time base */
> -static void gen_tbl(CPUPPCState *env)
> +static void register_tbl(CPUPPCState *env)
> {
> spr_register(env, SPR_VTBL, "TBL",
> &spr_read_tbl, SPR_NOACCESS,
> @@ -420,7 +420,7 @@ static void gen_tbl(CPUPPCState *env)
> }
>
> /* Softare table search registers */
> -static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> +static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> {
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = nb_tlbs;
> @@ -459,7 +459,7 @@ static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> }
>
> /* SPR common to MPC755 and G2 */
> -static void gen_spr_G2_755(CPUPPCState *env)
> +static void register_G2_755_sprs(CPUPPCState *env)
> {
> /* SGPRs */
> spr_register(env, SPR_SPRG4, "SPRG4",
> @@ -481,7 +481,7 @@ static void gen_spr_G2_755(CPUPPCState *env)
> }
>
> /* SPR common to all 7xx PowerPC implementations */
> -static void gen_spr_7xx(CPUPPCState *env)
> +static void register_7xx_sprs(CPUPPCState *env)
> {
> /* Breakpoints */
> /* XXX : not implemented */
> @@ -581,7 +581,7 @@ static void gen_spr_7xx(CPUPPCState *env)
>
> #ifdef TARGET_PPC64
>
> -static void gen_spr_amr(CPUPPCState *env)
> +static void register_amr_sprs(CPUPPCState *env)
> {
> #ifndef CONFIG_USER_ONLY
> /*
> @@ -613,7 +613,7 @@ static void gen_spr_amr(CPUPPCState *env)
> #endif /* !CONFIG_USER_ONLY */
> }
>
> -static void gen_spr_iamr(CPUPPCState *env)
> +static void register_iamr_sprs(CPUPPCState *env)
> {
> #ifndef CONFIG_USER_ONLY
> spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
> @@ -625,7 +625,7 @@ static void gen_spr_iamr(CPUPPCState *env)
> }
> #endif /* TARGET_PPC64 */
>
> -static void gen_spr_thrm(CPUPPCState *env)
> +static void register_thrm_sprs(CPUPPCState *env)
> {
> /* Thermal management */
> /* XXX : not implemented */
> @@ -646,7 +646,7 @@ static void gen_spr_thrm(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 604 implementation */
> -static void gen_spr_604(CPUPPCState *env)
> +static void register_604_sprs(CPUPPCState *env)
> {
> /* Processor identification */
> spr_register(env, SPR_PIR, "PIR",
> @@ -699,7 +699,7 @@ static void gen_spr_604(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 603 implementation */
> -static void gen_spr_603(CPUPPCState *env)
> +static void register_603_sprs(CPUPPCState *env)
> {
> /* External access control */
> /* XXX : not implemented */
> @@ -717,7 +717,7 @@ static void gen_spr_603(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC G2 implementation */
> -static void gen_spr_G2(CPUPPCState *env)
> +static void register_G2_sprs(CPUPPCState *env)
> {
> /* Memory base address */
> /* MBAR */
> @@ -769,7 +769,7 @@ static void gen_spr_G2(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 602 implementation */
> -static void gen_spr_602(CPUPPCState *env)
> +static void register_602_sprs(CPUPPCState *env)
> {
> /* ESA registers */
> /* XXX : not implemented */
> @@ -817,7 +817,7 @@ static void gen_spr_602(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 601 implementation */
> -static void gen_spr_601(CPUPPCState *env)
> +static void register_601_sprs(CPUPPCState *env)
> {
> /* Multiplication/division register */
> /* MQ */
> @@ -893,7 +893,7 @@ static void gen_spr_601(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_74xx(CPUPPCState *env)
> +static void register_74xx_sprs(CPUPPCState *env)
> {
> /* Processor identification */
> spr_register(env, SPR_PIR, "PIR",
> @@ -943,7 +943,7 @@ static void gen_spr_74xx(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_l3_ctrl(CPUPPCState *env)
> +static void register_l3_ctrl(CPUPPCState *env)
> {
> /* L3CR */
> /* XXX : not implemented */
> @@ -965,7 +965,7 @@ static void gen_l3_ctrl(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> +static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> {
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = nb_tlbs;
> @@ -990,7 +990,7 @@ static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> #endif
> }
>
> -static void gen_spr_usprg3(CPUPPCState *env)
> +static void register_usprg3_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_USPRG3, "USPRG3",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -998,7 +998,7 @@ static void gen_spr_usprg3(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_usprgh(CPUPPCState *env)
> +static void register_usprgh_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_USPRG4, "USPRG4",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -1019,7 +1019,7 @@ static void gen_spr_usprgh(CPUPPCState *env)
> }
>
> /* PowerPC BookE SPR */
> -static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
> +static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
> {
> const char *ivor_names[64] = {
> "IVOR0", "IVOR1", "IVOR2", "IVOR3",
> @@ -1195,7 +1195,7 @@ static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
> 0x00000000);
> }
>
> -static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
> +static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
> uint32_t maxsize, uint32_t flags,
> uint32_t nentries)
> {
> @@ -1206,7 +1206,7 @@ static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
> }
>
> /* BookE 2.06 storage control registers */
> -static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
> +static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
> uint32_t *tlbncfg, uint32_t mmucfg)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -1294,11 +1294,11 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
> }
> #endif
>
> - gen_spr_usprgh(env);
> + register_usprgh_sprs(env);
> }
>
> /* SPR specific to PowerPC 440 implementation */
> -static void gen_spr_440(CPUPPCState *env)
> +static void register_440_sprs(CPUPPCState *env)
> {
> /* Cache control */
> /* XXX : not implemented */
> @@ -1439,7 +1439,7 @@ static void gen_spr_440(CPUPPCState *env)
> }
>
> /* SPR shared between PowerPC 40x implementations */
> -static void gen_spr_40x(CPUPPCState *env)
> +static void register_40x_sprs(CPUPPCState *env)
> {
> /* Cache */
> /* not emulated, as QEMU do not emulate caches */
> @@ -1494,7 +1494,7 @@ static void gen_spr_40x(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 405 implementation */
> -static void gen_spr_405(CPUPPCState *env)
> +static void register_405_sprs(CPUPPCState *env)
> {
> /* MMU */
> spr_register(env, SPR_40x_PID, "PID",
> @@ -1596,11 +1596,11 @@ static void gen_spr_405(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> spr_read_generic, &spr_write_generic,
> 0x00000000);
> - gen_spr_usprgh(env);
> + register_usprgh_sprs(env);
> }
>
> /* SPR shared between PowerPC 401 & 403 implementations */
> -static void gen_spr_401_403(CPUPPCState *env)
> +static void register_401_403_sprs(CPUPPCState *env)
> {
> /* Time base */
> spr_register(env, SPR_403_VTBL, "TBL",
> @@ -1628,7 +1628,7 @@ static void gen_spr_401_403(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 401 implementation */
> -static void gen_spr_401(CPUPPCState *env)
> +static void register_401_sprs(CPUPPCState *env)
> {
> /* Debug interface */
> /* XXX : not implemented */
> @@ -1670,9 +1670,9 @@ static void gen_spr_401(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_401x2(CPUPPCState *env)
> +static void register_401x2_sprs(CPUPPCState *env)
> {
> - gen_spr_401(env);
> + register_401_sprs(env);
> spr_register(env, SPR_40x_PID, "PID",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> @@ -1684,7 +1684,7 @@ static void gen_spr_401x2(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 403 implementation */
> -static void gen_spr_403(CPUPPCState *env)
> +static void register_403_sprs(CPUPPCState *env)
> {
> /* Debug interface */
> /* XXX : not implemented */
> @@ -1720,7 +1720,7 @@ static void gen_spr_403(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_403_real(CPUPPCState *env)
> +static void register_403_real_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_403_PBL1, "PBL1",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -1740,7 +1740,7 @@ static void gen_spr_403_real(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_403_mmu(CPUPPCState *env)
> +static void register_403_mmu_sprs(CPUPPCState *env)
> {
> /* MMU */
> spr_register(env, SPR_40x_PID, "PID",
> @@ -1754,7 +1754,7 @@ static void gen_spr_403_mmu(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC compression coprocessor extension */
> -static void gen_spr_compress(CPUPPCState *env)
> +static void register_compress_sprs(CPUPPCState *env)
> {
> /* XXX : not implemented */
> spr_register(env, SPR_401_SKR, "SKR",
> @@ -1763,7 +1763,7 @@ static void gen_spr_compress(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_5xx_8xx(CPUPPCState *env)
> +static void register_5xx_8xx_sprs(CPUPPCState *env)
> {
> /* Exception processing */
> spr_register_kvm(env, SPR_DSISR, "DSISR",
> @@ -1881,7 +1881,7 @@ static void gen_spr_5xx_8xx(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_5xx(CPUPPCState *env)
> +static void register_5xx_sprs(CPUPPCState *env)
> {
> /* XXX : not implemented */
> spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
> @@ -1990,7 +1990,7 @@ static void gen_spr_5xx(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_8xx(CPUPPCState *env)
> +static void register_8xx_sprs(CPUPPCState *env)
> {
> /* XXX : not implemented */
> spr_register(env, SPR_MPC_IC_CST, "IC_CST",
> @@ -2725,9 +2725,9 @@ static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
>
> static void init_proc_401(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401_sprs(env);
> init_excp_4xx_real(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -2771,10 +2771,10 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
>
> static void init_proc_401x2(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401x2(env);
> - gen_spr_compress(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401x2_sprs(env);
> + register_compress_sprs(env);
> /* Memory management */
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> @@ -2829,11 +2829,11 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
>
> static void init_proc_401x3(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401(env);
> - gen_spr_401x2(env);
> - gen_spr_compress(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401_sprs(env);
> + register_401x2_sprs(env);
> + register_compress_sprs(env);
> init_excp_4xx_softmmu(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -2882,10 +2882,10 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
>
> static void init_proc_IOP480(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401x2(env);
> - gen_spr_compress(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401x2_sprs(env);
> + register_compress_sprs(env);
> /* Memory management */
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> @@ -2940,10 +2940,10 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
>
> static void init_proc_403(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_403(env);
> - gen_spr_403_real(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_403_sprs(env);
> + register_403_real_sprs(env);
> init_excp_4xx_real(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -2987,11 +2987,11 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
>
> static void init_proc_403GCX(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_403(env);
> - gen_spr_403_real(env);
> - gen_spr_403_mmu(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_403_sprs(env);
> + register_403_real_sprs(env);
> + register_403_mmu_sprs(env);
> /* Bus access control */
> /* not emulated, as QEMU never does speculative access */
> spr_register(env, SPR_40x_SGR, "SGR",
> @@ -3055,9 +3055,9 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
> static void init_proc_405(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_40x(env);
> - gen_spr_405(env);
> + register_tbl(env);
> + register_40x_sprs(env);
> + register_405_sprs(env);
> /* Bus access control */
> /* not emulated, as QEMU never does speculative access */
> spr_register(env, SPR_40x_SGR, "SGR",
> @@ -3121,10 +3121,10 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> static void init_proc_440EP(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3263,10 +3263,10 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
> static void init_proc_440GP(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3346,10 +3346,10 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
> static void init_proc_440x4(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3429,10 +3429,10 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
> static void init_proc_440x5(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3568,9 +3568,9 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
> static void init_proc_MPC5xx(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_5xx_8xx(env);
> - gen_spr_5xx(env);
> + register_tbl(env);
> + register_5xx_8xx_sprs(env);
> + register_5xx_sprs(env);
> init_excp_MPC5xx(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -3612,9 +3612,9 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
> static void init_proc_MPC8xx(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_5xx_8xx(env);
> - gen_spr_8xx(env);
> + register_tbl(env);
> + register_5xx_8xx_sprs(env);
> + register_8xx_sprs(env);
> init_excp_MPC8xx(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -3656,12 +3656,12 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
>
> static void init_proc_G2(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_G2_755(env);
> - gen_spr_G2(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_G2_755_sprs(env);
> + register_G2_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* External access control */
> /* XXX : not implemented */
> spr_register(env, SPR_EAR, "EAR",
> @@ -3685,9 +3685,9 @@ static void init_proc_G2(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_G2(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -3735,12 +3735,12 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
>
> static void init_proc_G2LE(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_G2_755(env);
> - gen_spr_G2(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_G2_755_sprs(env);
> + register_G2_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* External access control */
> /* XXX : not implemented */
> spr_register(env, SPR_EAR, "EAR",
> @@ -3765,9 +3765,9 @@ static void init_proc_G2LE(CPUPPCState *env)
> 0x00000000);
>
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_G2(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -3818,15 +3818,15 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
> static void init_proc_e200(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000070000FFFFULL);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000070000FFFFULL);
> /* XXX : not implemented */
> spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
> &spr_read_spefscr, &spr_write_spefscr,
> &spr_read_spefscr, &spr_write_spefscr,
> 0x00000000);
> /* Memory management */
> - gen_spr_BookE206(env, 0x0000005D, NULL, 0);
> + register_BookE206_sprs(env, 0x0000005D, NULL, 0);
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3972,11 +3972,11 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
>
> static void init_proc_e300(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_603(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_603_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4020,9 +4020,9 @@ static void init_proc_e300(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_603(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4093,11 +4093,11 @@ static void init_proc_e500(CPUPPCState *env, int version)
> #endif
>
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /*
> * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
> * complain when accessing them.
> - * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
> + * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
> */
> switch (version) {
> case fsl_e500v1:
> @@ -4113,8 +4113,8 @@ static void init_proc_e500(CPUPPCState *env, int version)
> ivor_mask = 0x000003FF0000FFFFULL;
> break;
> }
> - gen_spr_BookE(env, ivor_mask);
> - gen_spr_usprg3(env);
> + register_BookE_sprs(env, ivor_mask);
> + register_usprg3_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4132,17 +4132,17 @@ static void init_proc_e500(CPUPPCState *env, int version)
> env->id_tlbs = 0;
> switch (version) {
> case fsl_e500v1:
> - tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
> - tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> + tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
> + tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> break;
> case fsl_e500v2:
> - tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
> - tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> + tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
> + tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> break;
> case fsl_e500mc:
> case fsl_e5500:
> - tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
> - tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
> + tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
> + tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
> break;
> case fsl_e6500:
> mmucfg = 0x6510B45;
> @@ -4179,7 +4179,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
> cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> }
> - gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
> + register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4537,9 +4537,9 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
>
> static void init_proc_601(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_601(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_601_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4653,11 +4653,11 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
>
> static void init_proc_602(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_602(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_602_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4670,8 +4670,8 @@ static void init_proc_602(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_602(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4723,11 +4723,11 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
>
> static void init_proc_603(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_603(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_603_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4740,8 +4740,8 @@ static void init_proc_603(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_603(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4790,11 +4790,11 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
>
> static void init_proc_603E(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_603(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_603_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4807,8 +4807,8 @@ static void init_proc_603E(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_603(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4857,11 +4857,11 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
>
> static void init_proc_604(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_604(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_604_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4869,7 +4869,7 @@ static void init_proc_604(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_604(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4921,9 +4921,9 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
>
> static void init_proc_604E(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_604(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_604_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_7XX_MMCR1, "MMCR1",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4940,7 +4940,7 @@ static void init_proc_604E(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4953,7 +4953,7 @@ static void init_proc_604E(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_604(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5005,13 +5005,13 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
>
> static void init_proc_740(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5024,7 +5024,7 @@ static void init_proc_740(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_7x0(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5076,18 +5076,18 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
>
> static void init_proc_750(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5100,7 +5100,7 @@ static void init_proc_750(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /*
> * XXX: high BATs are also present but are known to be bugged on
> * die version 1.x
> @@ -5156,16 +5156,16 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
>
> static void init_proc_750cl(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> /* Those registers are fake on 750CL */
> spr_register(env, SPR_THRM1, "THRM1",
> @@ -5266,9 +5266,9 @@ static void init_proc_750cl(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750cl has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_750cl(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5359,18 +5359,18 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
>
> static void init_proc_750cx(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* This register is not implemented but is present for compatibility */
> spr_register(env, SPR_SDA, "SDA",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -5388,9 +5388,9 @@ static void init_proc_750cx(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750cx has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_750cx(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5442,18 +5442,18 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
>
> static void init_proc_750fx(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_750_THRM4, "THRM4",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -5476,9 +5476,9 @@ static void init_proc_750fx(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_7x0(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5530,18 +5530,18 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
>
> static void init_proc_750gx(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented (XXX: different from 750fx) */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_750_THRM4, "THRM4",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -5564,9 +5564,9 @@ static void init_proc_750gx(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_7x0(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5618,14 +5618,14 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
>
> static void init_proc_745(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> - gen_spr_G2_755(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> + register_G2_755_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5643,9 +5643,9 @@ static void init_proc_745(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_7x5(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5694,12 +5694,12 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
>
> static void init_proc_755(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> - gen_spr_G2_755(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> + register_G2_755_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* L2 cache control */
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> @@ -5712,7 +5712,7 @@ static void init_proc_755(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5730,9 +5730,9 @@ static void init_proc_755(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_7x5(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5781,13 +5781,13 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
>
> static void init_proc_7400(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -5801,9 +5801,9 @@ static void init_proc_7400(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_7400(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5861,13 +5861,13 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
>
> static void init_proc_7410(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -5875,7 +5875,7 @@ static void init_proc_7410(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* L2PMCR */
> /* XXX : not implemented */
> spr_register(env, SPR_L2PMCR, "L2PMCR",
> @@ -5889,7 +5889,7 @@ static void init_proc_7410(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_7400(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5947,13 +5947,13 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
>
> static void init_proc_7440(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -6000,8 +6000,8 @@ static void init_proc_7440(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6056,16 +6056,16 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
>
> static void init_proc_7450(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> - gen_l3_ctrl(env);
> + register_l3_ctrl(env);
> /* L3ITCR1 */
> /* XXX : not implemented */
> spr_register(env, SPR_L3ITCR1, "L3ITCR1",
> @@ -6135,8 +6135,8 @@ static void init_proc_7450(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6191,13 +6191,13 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
>
> static void init_proc_7445(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* LDSTCR */
> /* XXX : not implemented */
> @@ -6272,9 +6272,9 @@ static void init_proc_7445(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6329,16 +6329,16 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
>
> static void init_proc_7455(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> - gen_l3_ctrl(env);
> + register_l3_ctrl(env);
> /* LDSTCR */
> /* XXX : not implemented */
> spr_register(env, SPR_LDSTCR, "LDSTCR",
> @@ -6412,9 +6412,9 @@ static void init_proc_7455(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6469,16 +6469,16 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
>
> static void init_proc_7457(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> - gen_l3_ctrl(env);
> + register_l3_ctrl(env);
> /* L3ITCR1 */
> /* XXX : not implemented */
> spr_register(env, SPR_L3ITCR1, "L3ITCR1",
> @@ -6576,9 +6576,9 @@ static void init_proc_7457(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6633,13 +6633,13 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
>
> static void init_proc_e600(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -6715,9 +6715,9 @@ static void init_proc_e600(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6790,7 +6790,7 @@ static int check_pow_970(CPUPPCState *env)
> return 0;
> }
>
> -static void gen_spr_970_hid(CPUPPCState *env)
> +static void register_970_hid_sprs(CPUPPCState *env)
> {
> /* Hardware implementation registers */
> /* XXX : not implemented */
> @@ -6808,7 +6808,7 @@ static void gen_spr_970_hid(CPUPPCState *env)
> POWERPC970_HID5_INIT);
> }
>
> -static void gen_spr_970_hior(CPUPPCState *env)
> +static void register_970_hior_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_HIOR, "SPR_HIOR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6816,7 +6816,7 @@ static void gen_spr_970_hior(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_ctrl(CPUPPCState *env)
> +static void register_book3s_ctrl_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_CTRL, "SPR_CTRL",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6828,7 +6828,7 @@ static void gen_spr_book3s_ctrl(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_altivec(CPUPPCState *env)
> +static void register_book3s_altivec_sprs(CPUPPCState *env)
> {
> if (!(env->insns_flags & PPC_ALTIVEC)) {
> return;
> @@ -6841,7 +6841,7 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
>
> }
>
> -static void gen_spr_book3s_dbg(CPUPPCState *env)
> +static void register_book3s_dbg_sprs(CPUPPCState *env)
> {
> /*
> * TODO: different specs define different scopes for these,
> @@ -6860,7 +6860,7 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
> KVM_REG_PPC_DABRX, 0x00000000);
> }
>
> -static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> +static void register_book3s_207_dbg_sprs(CPUPPCState *env)
> {
> spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6879,7 +6879,7 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> KVM_REG_PPC_CIABR, 0x00000000);
> }
>
> -static void gen_spr_970_dbg(CPUPPCState *env)
> +static void register_970_dbg_sprs(CPUPPCState *env)
> {
> /* Breakpoints */
> spr_register(env, SPR_IABR, "IABR",
> @@ -6888,7 +6888,7 @@ static void gen_spr_970_dbg(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
> +static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6936,7 +6936,7 @@ static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
> KVM_REG_PPC_SDAR, 0x00000000);
> }
>
> -static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> +static void register_book3s_pmu_user_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -6984,7 +6984,7 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_970_pmu_sup(CPUPPCState *env)
> +static void register_970_pmu_sup_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_970_PMC7, "PMC7",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6996,7 +6996,7 @@ static void gen_spr_970_pmu_sup(CPUPPCState *env)
> KVM_REG_PPC_PMC8, 0x00000000);
> }
>
> -static void gen_spr_970_pmu_user(CPUPPCState *env)
> +static void register_970_pmu_user_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_970_UPMC7, "UPMC7",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -7008,7 +7008,7 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power8_pmu_sup(CPUPPCState *env)
> +static void register_power8_pmu_sup_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7044,7 +7044,7 @@ static void gen_spr_power8_pmu_sup(CPUPPCState *env)
> KVM_REG_PPC_CSIGR, 0x00000000);
> }
>
> -static void gen_spr_power8_pmu_user(CPUPPCState *env)
> +static void register_power8_pmu_user_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -7056,7 +7056,7 @@ static void gen_spr_power8_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power5p_ear(CPUPPCState *env)
> +static void register_power5p_ear_sprs(CPUPPCState *env)
> {
> /* External access control */
> spr_register(env, SPR_EAR, "EAR",
> @@ -7065,7 +7065,7 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power5p_tb(CPUPPCState *env)
> +static void register_power5p_tb_sprs(CPUPPCState *env)
> {
> /* TBU40 (High 40 bits of the Timebase register */
> spr_register_hv(env, SPR_TBU40, "TBU40",
> @@ -7075,7 +7075,7 @@ static void gen_spr_power5p_tb(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_970_lpar(CPUPPCState *env)
> +static void register_970_lpar_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /*
> @@ -7092,7 +7092,7 @@ static void gen_spr_970_lpar(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power5p_lpar(CPUPPCState *env)
> +static void register_power5p_lpar_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* Logical partitionning */
> @@ -7108,7 +7108,7 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_book3s_ids(CPUPPCState *env)
> +static void register_book3s_ids_sprs(CPUPPCState *env)
> {
> /* FIXME: Will need to deal with thread vs core only SPRs */
>
> @@ -7200,7 +7200,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_rmor(CPUPPCState *env)
> +static void register_rmor_sprs(CPUPPCState *env)
> {
> spr_register_hv(env, SPR_RMOR, "RMOR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7209,7 +7209,7 @@ static void gen_spr_rmor(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power8_ids(CPUPPCState *env)
> +static void register_power8_ids_sprs(CPUPPCState *env)
> {
> /* Thread identification */
> spr_register(env, SPR_TIR, "TIR",
> @@ -7218,7 +7218,7 @@ static void gen_spr_power8_ids(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_purr(CPUPPCState *env)
> +static void register_book3s_purr_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
> @@ -7235,7 +7235,7 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power6_dbg(CPUPPCState *env)
> +static void register_power6_dbg_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register(env, SPR_CFAR, "SPR_CFAR",
> @@ -7245,7 +7245,7 @@ static void gen_spr_power6_dbg(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power5p_common(CPUPPCState *env)
> +static void register_power5p_common_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_PPR, "PPR",
> &spr_read_generic, &spr_write_generic,
> @@ -7253,7 +7253,7 @@ static void gen_spr_power5p_common(CPUPPCState *env)
> KVM_REG_PPC_PPR, 0x00000000);
> }
>
> -static void gen_spr_power6_common(CPUPPCState *env)
> +static void register_power6_common_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
> @@ -7272,7 +7272,7 @@ static void gen_spr_power6_common(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> +static void register_power8_tce_address_control_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TAR, "TAR",
> &spr_read_tar, &spr_write_tar,
> @@ -7280,7 +7280,7 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> KVM_REG_PPC_TAR, 0x00000000);
> }
>
> -static void gen_spr_power8_tm(CPUPPCState *env)
> +static void register_power8_tm_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TFHAR, "TFHAR",
> &spr_read_tm, &spr_write_tm,
> @@ -7300,7 +7300,7 @@ static void gen_spr_power8_tm(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power8_ebb(CPUPPCState *env)
> +static void register_power8_ebb_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_BESCRS, "BESCRS",
> &spr_read_ebb, &spr_write_ebb,
> @@ -7333,7 +7333,7 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
> }
>
> /* Virtual Time Base */
> -static void gen_spr_vtb(CPUPPCState *env)
> +static void register_vtb_sprs(CPUPPCState *env)
> {
> spr_register_kvm_hv(env, SPR_VTB, "VTB",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7342,7 +7342,7 @@ static void gen_spr_vtb(CPUPPCState *env)
> KVM_REG_PPC_VTB, 0x00000000);
> }
>
> -static void gen_spr_power8_fscr(CPUPPCState *env)
> +static void register_power8_fscr_sprs(CPUPPCState *env)
> {
> #if defined(CONFIG_USER_ONLY)
> target_ulong initval = 1ULL << FSCR_TAR;
> @@ -7355,7 +7355,7 @@ static void gen_spr_power8_fscr(CPUPPCState *env)
> KVM_REG_PPC_FSCR, initval);
> }
>
> -static void gen_spr_power8_pspb(CPUPPCState *env)
> +static void register_power8_pspb_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_PSPB, "PSPB",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7363,7 +7363,7 @@ static void gen_spr_power8_pspb(CPUPPCState *env)
> KVM_REG_PPC_PSPB, 0);
> }
>
> -static void gen_spr_power8_dpdes(CPUPPCState *env)
> +static void register_power8_dpdes_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* Directed Privileged Door-bell Exception State, used for IPI */
> @@ -7375,7 +7375,7 @@ static void gen_spr_power8_dpdes(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power8_ic(CPUPPCState *env)
> +static void register_power8_ic_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register_hv(env, SPR_IC, "IC",
> @@ -7386,7 +7386,7 @@ static void gen_spr_power8_ic(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power8_book4(CPUPPCState *env)
> +static void register_power8_book4_sprs(CPUPPCState *env)
> {
> /* Add a number of P8 book4 registers */
> #if !defined(CONFIG_USER_ONLY)
> @@ -7405,7 +7405,7 @@ static void gen_spr_power8_book4(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power7_book4(CPUPPCState *env)
> +static void register_power7_book4_sprs(CPUPPCState *env)
> {
> /* Add a number of P7 book4 registers */
> #if !defined(CONFIG_USER_ONLY)
> @@ -7420,7 +7420,7 @@ static void gen_spr_power7_book4(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power8_rpr(CPUPPCState *env)
> +static void register_power8_rpr_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register_hv(env, SPR_RPR, "RPR",
> @@ -7431,7 +7431,7 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power9_mmu(CPUPPCState *env)
> +static void register_power9_mmu_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* Partition Table Control */
> @@ -7451,13 +7451,13 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
>
> static void init_proc_book3s_common(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_tbl(env);
> - gen_spr_usprg3(env);
> - gen_spr_book3s_altivec(env);
> - gen_spr_book3s_pmu_sup(env);
> - gen_spr_book3s_pmu_user(env);
> - gen_spr_book3s_ctrl(env);
> + register_ne_601_sprs(env);
> + register_tbl(env);
> + register_usprg3_sprs(env);
> + register_book3s_altivec_sprs(env);
> + register_book3s_pmu_sup_sprs(env);
> + register_book3s_pmu_user_sprs(env);
> + register_book3s_ctrl_sprs(env);
> /*
> * Can't find information on what this should be on reset. This
> * value is the one used by 74xx processors.
> @@ -7469,17 +7469,17 @@ static void init_proc_970(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_dbg_sprs(env);
>
> /* 970 Specific Registers */
> - gen_spr_970_hid(env);
> - gen_spr_970_hior(env);
> - gen_low_BATs(env);
> - gen_spr_970_pmu_sup(env);
> - gen_spr_970_pmu_user(env);
> - gen_spr_970_lpar(env);
> - gen_spr_970_dbg(env);
> + register_970_hid_sprs(env);
> + register_970_hior_sprs(env);
> + register_low_BATs(env);
> + register_970_pmu_sup_sprs(env);
> + register_970_pmu_user_sprs(env);
> + register_970_lpar_sprs(env);
> + register_970_dbg_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -7542,19 +7542,19 @@ static void init_proc_power5plus(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_dbg_sprs(env);
>
> /* POWER5+ Specific Registers */
> - gen_spr_970_hid(env);
> - gen_spr_970_hior(env);
> - gen_low_BATs(env);
> - gen_spr_970_pmu_sup(env);
> - gen_spr_970_pmu_user(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> + register_970_hid_sprs(env);
> + register_970_hior_sprs(env);
> + register_low_BATs(env);
> + register_970_pmu_sup_sprs(env);
> + register_970_pmu_user_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -7621,21 +7621,21 @@ static void init_proc_POWER7(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_dbg_sprs(env);
>
> /* POWER7 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_rmor(env);
> - gen_spr_amr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power7_book4(env);
> + register_book3s_ids_sprs(env);
> + register_rmor_sprs(env);
> + register_amr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power7_book4_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -7767,34 +7767,34 @@ static void init_proc_POWER8(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_207_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_207_dbg_sprs(env);
>
> /* POWER8 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_rmor(env);
> - gen_spr_amr(env);
> - gen_spr_iamr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power8_tce_address_control(env);
> - gen_spr_power8_ids(env);
> - gen_spr_power8_ebb(env);
> - gen_spr_power8_fscr(env);
> - gen_spr_power8_pmu_sup(env);
> - gen_spr_power8_pmu_user(env);
> - gen_spr_power8_tm(env);
> - gen_spr_power8_pspb(env);
> - gen_spr_power8_dpdes(env);
> - gen_spr_vtb(env);
> - gen_spr_power8_ic(env);
> - gen_spr_power8_book4(env);
> - gen_spr_power8_rpr(env);
> + register_book3s_ids_sprs(env);
> + register_rmor_sprs(env);
> + register_amr_sprs(env);
> + register_iamr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power8_tce_address_control_sprs(env);
> + register_power8_ids_sprs(env);
> + register_power8_ebb_sprs(env);
> + register_power8_fscr_sprs(env);
> + register_power8_pmu_sup_sprs(env);
> + register_power8_pmu_user_sprs(env);
> + register_power8_tm_sprs(env);
> + register_power8_pspb_sprs(env);
> + register_power8_dpdes_sprs(env);
> + register_vtb_sprs(env);
> + register_power8_ic_sprs(env);
> + register_power8_book4_sprs(env);
> + register_power8_rpr_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -7964,33 +7964,33 @@ static void init_proc_POWER9(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_book3s_207_dbg(env);
> + register_book3s_207_dbg_sprs(env);
>
> /* POWER8 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_amr(env);
> - gen_spr_iamr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power8_tce_address_control(env);
> - gen_spr_power8_ids(env);
> - gen_spr_power8_ebb(env);
> - gen_spr_power8_fscr(env);
> - gen_spr_power8_pmu_sup(env);
> - gen_spr_power8_pmu_user(env);
> - gen_spr_power8_tm(env);
> - gen_spr_power8_pspb(env);
> - gen_spr_power8_dpdes(env);
> - gen_spr_vtb(env);
> - gen_spr_power8_ic(env);
> - gen_spr_power8_book4(env);
> - gen_spr_power8_rpr(env);
> - gen_spr_power9_mmu(env);
> + register_book3s_ids_sprs(env);
> + register_amr_sprs(env);
> + register_iamr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power8_tce_address_control_sprs(env);
> + register_power8_ids_sprs(env);
> + register_power8_ebb_sprs(env);
> + register_power8_fscr_sprs(env);
> + register_power8_pmu_sup_sprs(env);
> + register_power8_pmu_user_sprs(env);
> + register_power8_tm_sprs(env);
> + register_power8_pspb_sprs(env);
> + register_power8_dpdes_sprs(env);
> + register_vtb_sprs(env);
> + register_power8_ic_sprs(env);
> + register_power8_book4_sprs(env);
> + register_power8_rpr_sprs(env);
> + register_power9_mmu_sprs(env);
>
> /* POWER9 Specific registers */
> spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
> @@ -8182,31 +8182,31 @@ static void init_proc_POWER10(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_book3s_207_dbg(env);
> + register_book3s_207_dbg_sprs(env);
>
> /* POWER8 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_amr(env);
> - gen_spr_iamr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power8_tce_address_control(env);
> - gen_spr_power8_ids(env);
> - gen_spr_power8_ebb(env);
> - gen_spr_power8_fscr(env);
> - gen_spr_power8_pmu_sup(env);
> - gen_spr_power8_pmu_user(env);
> - gen_spr_power8_tm(env);
> - gen_spr_power8_pspb(env);
> - gen_spr_vtb(env);
> - gen_spr_power8_ic(env);
> - gen_spr_power8_book4(env);
> - gen_spr_power8_rpr(env);
> - gen_spr_power9_mmu(env);
> + register_book3s_ids_sprs(env);
> + register_amr_sprs(env);
> + register_iamr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power8_tce_address_control_sprs(env);
> + register_power8_ids_sprs(env);
> + register_power8_ebb_sprs(env);
> + register_power8_fscr_sprs(env);
> + register_power8_pmu_sup_sprs(env);
> + register_power8_pmu_user_sprs(env);
> + register_power8_tm_sprs(env);
> + register_power8_pspb_sprs(env);
> + register_vtb_sprs(env);
> + register_power8_ic_sprs(env);
> + register_power8_book4_sprs(env);
> + register_power8_rpr_sprs(env);
> + register_power9_mmu_sprs(env);
>
> /* FIXME: Filter fields properly based on privilege level */
> spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
> @@ -8411,7 +8411,7 @@ static void init_ppc_proc(PowerPCCPU *cpu)
> env->tlb_type = TLB_NONE;
> #endif
> /* Register SPR common to all PowerPC implementations */
> - gen_spr_generic(env);
> + register_generic_sprs(env);
> spr_register(env, SPR_PVR, "PVR",
> /* Linux permits userspace to read PVR */
> #if defined(CONFIG_LINUX_USER)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks
2021-04-30 19:35 ` [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks Bruno Larsen (billionai)
2021-05-01 0:55 ` Richard Henderson
@ 2021-05-03 4:54 ` David Gibson
2021-05-03 20:15 ` Bruno Piazera Larsen
1 sibling, 1 reply; 25+ messages in thread
From: David Gibson @ 2021-05-03 4:54 UTC (permalink / raw)
To: Bruno Larsen (billionai)
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 70562 bytes --]
On Fri, Apr 30, 2021 at 04:35:28PM -0300, Bruno Larsen (billionai) wrote:
> Moved all SPR read/write callback, and some related functions, to a
> new file specific for it. These callbacks are TCG only, so separating
> them is required to support the build flag disable-tcg.
>
> Making the spr_noaccess function not static, and moving the define to
> internal.h is required, otherwise the project doesn't build
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> ---
> target/ppc/internal.h | 3 +
> target/ppc/spr_tcg.c.inc | 1052 +++++++++++++++++++++++++++++++
> target/ppc/translate.c | 47 +-
> target/ppc/translate_init.c.inc | 981 ----------------------------
> 4 files changed, 1056 insertions(+), 1027 deletions(-)
> create mode 100644 target/ppc/spr_tcg.c.inc
Hmm. So, I'm still pretty ambivalent about the creation of
spr_tcg.c.inc. The separation between it and translate.c just seems
rather arbitrary to me.
Yes, translate.c is overly huge, but I'm not sure going from
overly-huge to overly-huger really makes anything worse, and would
avoid some of the dancing around to handle the new file.
So for now, I'm inclined to suggest just moving the spr callbacks from
translate_init.c.inc to translate.c. And some day, I hope someone has
time to split up translate.c based on CPU family, which I think is a
more useful way to make it less huge.
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 184ba6d6b3..1de15acfbd 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -228,4 +228,7 @@ void destroy_ppc_opcodes(PowerPCCPU *cpu);
> void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *ppc);
> gchar *ppc_gdb_arch_name(CPUState *cs);
>
> +void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
> +#define SPR_NOACCESS (&spr_noaccess)
> +
> #endif /* PPC_INTERNAL_H */
> diff --git a/target/ppc/spr_tcg.c.inc b/target/ppc/spr_tcg.c.inc
> new file mode 100644
> index 0000000000..8d033dae6f
> --- /dev/null
> +++ b/target/ppc/spr_tcg.c.inc
> @@ -0,0 +1,1052 @@
> +/*
> + * PowerPC emulation for qemu: read/write callbacks for SPRs
> + *
> + * Copyright (C) 2021 Instituto de Pesquisas Eldorado
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/*****************************************************************************/
> +/* Reader and writer functions for SPRs */
> +
> +static void gen_read_xer(DisasContext *ctx, TCGv dst)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> + tcg_gen_mov_tl(dst, cpu_xer);
> + tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> + tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> + tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> + tcg_gen_or_tl(t0, t0, t1);
> + tcg_gen_or_tl(dst, dst, t2);
> + tcg_gen_or_tl(dst, dst, t0);
> + if (is_isa300(ctx)) {
> + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> + tcg_gen_or_tl(dst, dst, t0);
> + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> + tcg_gen_or_tl(dst, dst, t0);
> + }
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +
> +static void gen_write_xer(TCGv src)
> +{
> + /* Write all flags, while reading back check for isa300 */
> + tcg_gen_andi_tl(cpu_xer, src,
> + ~((1u << XER_SO) |
> + (1u << XER_OV) | (1u << XER_OV32) |
> + (1u << XER_CA) | (1u << XER_CA32)));
> + tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> + tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> + tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> + tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> + tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> +}
> +
> +void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
> +{
> +#if 0
> + sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
> + printf("ERROR: try to access SPR %d !\n", sprn);
> +#endif
> +}
> +
> +/* #define PPC_DUMP_SPR_ACCESSES */
> +
> +/*
> + * Generic callbacks:
> + * do nothing but store/retrieve spr value
> + */
> +static void spr_load_dump_spr(int sprn)
> +{
> +#ifdef PPC_DUMP_SPR_ACCESSES
> + TCGv_i32 t0 = tcg_const_i32(sprn);
> + gen_helper_load_dump_spr(cpu_env, t0);
> + tcg_temp_free_i32(t0);
> +#endif
> +}
> +
> +static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_load_spr(cpu_gpr[gprn], sprn);
> + spr_load_dump_spr(sprn);
> +}
> +
> +static void spr_store_dump_spr(int sprn)
> +{
> +#ifdef PPC_DUMP_SPR_ACCESSES
> + TCGv_i32 t0 = tcg_const_i32(sprn);
> + gen_helper_store_dump_spr(cpu_env, t0);
> + tcg_temp_free_i32(t0);
> +#endif
> +}
> +
> +static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_store_spr(sprn, cpu_gpr[gprn]);
> + spr_store_dump_spr(sprn);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
> +{
> +#ifdef TARGET_PPC64
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> + spr_store_dump_spr(sprn);
> +#else
> + spr_write_generic(ctx, sprn, gprn);
> +#endif
> +}
> +
> +static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + gen_load_spr(t0, sprn);
> + tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
> + tcg_gen_and_tl(t0, t0, t1);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> +}
> +
> +static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
> +{
> +}
> +
> +#endif
> +
> +/* SPR common to all PowerPC */
> +/* XER */
> +static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_read_xer(ctx, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_write_xer(cpu_gpr[gprn]);
> +}
> +
> +/* LR */
> +static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
> +}
> +
> +static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
> +{
> + tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
> +}
> +
> +/* CFAR */
> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> +static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> +}
> +
> +static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
> +{
> + tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> +}
> +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
> +
> +/* CTR */
> +static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
> +}
> +
> +static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
> +{
> + tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
> +}
> +
> +/* User read access to SPR */
> +/* USPRx */
> +/* UMMCRx */
> +/* UPMCx */
> +/* USIA */
> +/* UDECR */
> +static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
> +}
> +
> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> +static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
> +}
> +#endif
> +
> +/* SPR common to all non-embedded PowerPC */
> +/* DECR */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +#endif
> +
> +/* SPR common to all non-embedded PowerPC, except 601 */
> +/* Time base */
> +static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +#if defined(TARGET_PPC64)
> +ATTRIBUTE_UNUSED
> +static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +/* HDECR */
> +static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +#endif
> +#endif
> +
> +#if !defined(CONFIG_USER_ONLY)
> +/* IBAT0U...IBAT0U */
> +/* IBAT0L...IBAT7L */
> +static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> +}
> +
> +static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
> +}
> +
> +static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
> + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
> + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
> + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +/* DBAT0U...DBAT7U */
> +/* DBAT0L...DBAT7L */
> +static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
> +}
> +
> +static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
> +}
> +
> +static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
> + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
> + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
> + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
> + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +/* SDR1 */
> +static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +#if defined(TARGET_PPC64)
> +/* 64 bits PowerPC specific SPRs */
> +/* PIDR */
> +static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
> +}
> +
> +static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
> + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +/* DPDES */
> +static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
> +}
> +
> +static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
> +}
> +#endif
> +#endif
> +
> +/* PowerPC 601 specific registers */
> +/* RTC */
> +static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
> +}
> +
> +static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
> + /* Must stop the translation as endianness may have changed */
> + gen_stop_exception(ctx);
> +}
> +#endif
> +
> +/* Unified bats */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> +}
> +
> +static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> + gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> + gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +#endif
> +
> +/* PowerPC 40x specific registers */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_store_spr(sprn, cpu_gpr[gprn]);
> + gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> + /* We must stop translation as we may have rebooted */
> + gen_stop_exception(ctx);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +#endif
> +
> +/* PowerPC 403 specific registers */
> +/* PBL1 / PBU1 / PBL2 / PBU2 */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
> +}
> +
> +static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
> + gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
> + gen_store_spr(SPR_PIR, t0);
> + tcg_temp_free(t0);
> +}
> +#endif
> +
> +/* SPE specific registers */
> +static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> + tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
> + tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> + tcg_temp_free_i32(t0);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +
> +/* Callback used to write the exception vector base */
> +static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
> + tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
> +{
> + int sprn_offs;
> +
> + if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
> + sprn_offs = sprn - SPR_BOOKE_IVOR0;
> + } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
> + sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
> + } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
> + sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
> + } else {
> + printf("Trying to write an unknown exception vector %d %03x\n",
> + sprn, sprn);
> + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
> + return;
> + }
> +
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
> + tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +#endif
> +
> +#ifdef TARGET_PPC64
> +#ifndef CONFIG_USER_ONLY
> +static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /*
> + * Note, the HV=1 PR=0 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + if (ctx->pr) {
> + gen_load_spr(t1, SPR_UAMOR);
> + } else {
> + gen_load_spr(t1, SPR_AMOR);
> + }
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_AMR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_AMR, t0);
> + spr_store_dump_spr(SPR_AMR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +
> +static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /*
> + * Note, the HV=1 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + gen_load_spr(t1, SPR_AMOR);
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_UAMOR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_UAMOR, t0);
> + spr_store_dump_spr(SPR_UAMOR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +
> +static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /*
> + * Note, the HV=1 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + gen_load_spr(t1, SPR_AMOR);
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_IAMR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_IAMR, t0);
> + spr_store_dump_spr(SPR_IAMR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +#endif /* CONFIG_USER_ONLY */
> +#endif /* TARGET_PPC64 */
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_fixup_thrm(cpu_env);
> + gen_load_spr(cpu_gpr[gprn], sprn);
> + spr_load_dump_spr(sprn);
> +}
> +
> +static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> +
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> +
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> +
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn],
> + ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(sprn);
> + gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv val = tcg_temp_new();
> + tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
> + gen_store_spr(SPR_BOOKE_MAS3, val);
> + tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
> + gen_store_spr(SPR_BOOKE_MAS7, val);
> + tcg_temp_free(val);
> +}
> +
> +static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv mas7 = tcg_temp_new();
> + TCGv mas3 = tcg_temp_new();
> + gen_load_spr(mas7, SPR_BOOKE_MAS7);
> + tcg_gen_shli_tl(mas7, mas7, 32);
> + gen_load_spr(mas3, SPR_BOOKE_MAS3);
> + tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
> + tcg_temp_free(mas3);
> + tcg_temp_free(mas7);
> +}
> +
> +#endif /* !defined(CONFIG_USER_ONLY) */
> +
> +#ifdef TARGET_PPC64
> +static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> + int bit, int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> +static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
> + int bit, int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> +static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv spr_up = tcg_temp_new();
> + TCGv spr = tcg_temp_new();
> +
> + gen_load_spr(spr, sprn - 1);
> + tcg_gen_shri_tl(spr_up, spr, 32);
> + tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
> +
> + tcg_temp_free(spr);
> + tcg_temp_free(spr_up);
> +}
> +
> +static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv spr = tcg_temp_new();
> +
> + gen_load_spr(spr, sprn - 1);
> + tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
> + gen_store_spr(sprn - 1, spr);
> +
> + tcg_temp_free(spr);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv hmer = tcg_temp_new();
> +
> + gen_load_spr(hmer, sprn);
> + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
> + gen_store_spr(sprn, hmer);
> + spr_store_dump_spr(sprn);
> + tcg_temp_free(hmer);
> +}
> +
> +static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
> +}
> +#endif
> +
> +static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_read_generic(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_write_generic(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_read_generic(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_write_generic(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_read_prev_upper32(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_write_prev_upper32(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_read_generic(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_write_generic(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_read_prev_upper32(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_write_prev_upper32(ctx, sprn, gprn);
> +}
> +#endif
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index b319d409c6..dba112087e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4175,43 +4175,6 @@ static void gen_tdi(DisasContext *ctx)
>
> /*** Processor control ***/
>
> -static void gen_read_xer(DisasContext *ctx, TCGv dst)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> - tcg_gen_mov_tl(dst, cpu_xer);
> - tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> - tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> - tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> - tcg_gen_or_tl(t0, t0, t1);
> - tcg_gen_or_tl(dst, dst, t2);
> - tcg_gen_or_tl(dst, dst, t0);
> - if (is_isa300(ctx)) {
> - tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> - tcg_gen_or_tl(dst, dst, t0);
> - tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> - tcg_gen_or_tl(dst, dst, t0);
> - }
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void gen_write_xer(TCGv src)
> -{
> - /* Write all flags, while reading back check for isa300 */
> - tcg_gen_andi_tl(cpu_xer, src,
> - ~((1u << XER_SO) |
> - (1u << XER_OV) | (1u << XER_OV32) |
> - (1u << XER_CA) | (1u << XER_CA32)));
> - tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> - tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> - tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> - tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> - tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> -}
> -
> /* mcrxr */
> static void gen_mcrxr(DisasContext *ctx)
> {
> @@ -4299,15 +4262,6 @@ static void gen_mfmsr(DisasContext *ctx)
> tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
> }
>
> -static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
> -{
> -#if 0
> - sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
> - printf("ERROR: try to access SPR %d !\n", sprn);
> -#endif
> -}
> -#define SPR_NOACCESS (&spr_noaccess)
> -
> /* mfspr */
> static inline void gen_op_mfspr(DisasContext *ctx)
> {
> @@ -7639,6 +7593,7 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
> };
>
> #include "helper_regs.h"
> +#include "spr_tcg.c.inc"
> #include "translate_init.c.inc"
>
> /*****************************************************************************/
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index 22b23793fd..13ad58863e 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -43,676 +43,8 @@
> #include "qapi/qapi-commands-machine-target.h"
>
> /* #define PPC_DEBUG_SPR */
> -/* #define PPC_DUMP_SPR_ACCESSES */
> /* #define USE_APPLE_GDB */
>
> -/*
> - * Generic callbacks:
> - * do nothing but store/retrieve spr value
> - */
> -static void spr_load_dump_spr(int sprn)
> -{
> -#ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> - gen_helper_load_dump_spr(cpu_env, t0);
> - tcg_temp_free_i32(t0);
> -#endif
> -}
> -
> -static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_load_spr(cpu_gpr[gprn], sprn);
> - spr_load_dump_spr(sprn);
> -}
> -
> -static void spr_store_dump_spr(int sprn)
> -{
> -#ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> - gen_helper_store_dump_spr(cpu_env, t0);
> - tcg_temp_free_i32(t0);
> -#endif
> -}
> -
> -static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_store_spr(sprn, cpu_gpr[gprn]);
> - spr_store_dump_spr(sprn);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
> -{
> -#ifdef TARGET_PPC64
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> - spr_store_dump_spr(sprn);
> -#else
> - spr_write_generic(ctx, sprn, gprn);
> -#endif
> -}
> -
> -static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - gen_load_spr(t0, sprn);
> - tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
> - tcg_gen_and_tl(t0, t0, t1);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> -}
> -
> -static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
> -{
> -}
> -
> -#endif
> -
> -/* SPR common to all PowerPC */
> -/* XER */
> -static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_read_xer(ctx, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_write_xer(cpu_gpr[gprn]);
> -}
> -
> -/* LR */
> -static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
> -}
> -
> -static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
> -{
> - tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
> -}
> -
> -/* CFAR */
> -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> -static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> -}
> -
> -static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
> -{
> - tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> -}
> -#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
> -
> -/* CTR */
> -static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
> -}
> -
> -static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
> -{
> - tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
> -}
> -
> -/* User read access to SPR */
> -/* USPRx */
> -/* UMMCRx */
> -/* UPMCx */
> -/* USIA */
> -/* UDECR */
> -static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
> -}
> -
> -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> -static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
> -}
> -#endif
> -
> -/* SPR common to all non-embedded PowerPC */
> -/* DECR */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -#endif
> -
> -/* SPR common to all non-embedded PowerPC, except 601 */
> -/* Time base */
> -static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -#if defined(TARGET_PPC64)
> -ATTRIBUTE_UNUSED
> -static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -/* HDECR */
> -static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -#endif
> -#endif
> -
> -#if !defined(CONFIG_USER_ONLY)
> -/* IBAT0U...IBAT0U */
> -/* IBAT0L...IBAT7L */
> -static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> -}
> -
> -static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
> -}
> -
> -static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
> - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
> - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
> - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -/* DBAT0U...DBAT7U */
> -/* DBAT0L...DBAT7L */
> -static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
> -}
> -
> -static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
> -}
> -
> -static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
> - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
> - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
> - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
> - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -/* SDR1 */
> -static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -#if defined(TARGET_PPC64)
> -/* 64 bits PowerPC specific SPRs */
> -/* PIDR */
> -static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
> -}
> -
> -static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
> - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> - tcg_temp_free(t0);
> -}
> -static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -/* DPDES */
> -static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
> -}
> -
> -static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
> -}
> -#endif
> -#endif
> -
> -/* PowerPC 601 specific registers */
> -/* RTC */
> -static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
> -}
> -
> -static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
> - /* Must stop the translation as endianness may have changed */
> - gen_stop_exception(ctx);
> -}
> -#endif
> -
> -/* Unified bats */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> -}
> -
> -static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> - gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> - gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -#endif
> -
> -/* PowerPC 40x specific registers */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_store_spr(sprn, cpu_gpr[gprn]);
> - gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> - /* We must stop translation as we may have rebooted */
> - gen_stop_exception(ctx);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -#endif
> -
> -/* PowerPC 403 specific registers */
> -/* PBL1 / PBU1 / PBL2 / PBU2 */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
> -}
> -
> -static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
> - gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
> - gen_store_spr(SPR_PIR, t0);
> - tcg_temp_free(t0);
> -}
> -#endif
> -
> -/* SPE specific registers */
> -static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
> -{
> - TCGv_i32 t0 = tcg_temp_new_i32();
> - tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> - tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_temp_new_i32();
> - tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
> - tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> - tcg_temp_free_i32(t0);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -/* Callback used to write the exception vector base */
> -static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
> - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
> -{
> - int sprn_offs;
> -
> - if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
> - sprn_offs = sprn - SPR_BOOKE_IVOR0;
> - } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
> - sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
> - } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
> - sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
> - } else {
> - printf("Trying to write an unknown exception vector %d %03x\n",
> - sprn, sprn);
> - gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
> - return;
> - }
> -
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
> - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -#endif
> -
> static inline void vscr_init(CPUPPCState *env, uint32_t val)
> {
> /* Altivec always uses round-to-nearest */
> @@ -1247,104 +579,6 @@ static void gen_spr_7xx(CPUPPCState *env)
> }
>
> #ifdef TARGET_PPC64
> -#ifndef CONFIG_USER_ONLY
> -static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> -
> - /*
> - * Note, the HV=1 PR=0 case is handled earlier by simply using
> - * spr_write_generic for HV mode in the SPR table
> - */
> -
> - /* Build insertion mask into t1 based on context */
> - if (ctx->pr) {
> - gen_load_spr(t1, SPR_UAMOR);
> - } else {
> - gen_load_spr(t1, SPR_AMOR);
> - }
> -
> - /* Mask new bits into t2 */
> - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> -
> - /* Load AMR and clear new bits in t0 */
> - gen_load_spr(t0, SPR_AMR);
> - tcg_gen_andc_tl(t0, t0, t1);
> -
> - /* Or'in new bits and write it out */
> - tcg_gen_or_tl(t0, t0, t2);
> - gen_store_spr(SPR_AMR, t0);
> - spr_store_dump_spr(SPR_AMR);
> -
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> -
> - /*
> - * Note, the HV=1 case is handled earlier by simply using
> - * spr_write_generic for HV mode in the SPR table
> - */
> -
> - /* Build insertion mask into t1 based on context */
> - gen_load_spr(t1, SPR_AMOR);
> -
> - /* Mask new bits into t2 */
> - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> -
> - /* Load AMR and clear new bits in t0 */
> - gen_load_spr(t0, SPR_UAMOR);
> - tcg_gen_andc_tl(t0, t0, t1);
> -
> - /* Or'in new bits and write it out */
> - tcg_gen_or_tl(t0, t0, t2);
> - gen_store_spr(SPR_UAMOR, t0);
> - spr_store_dump_spr(SPR_UAMOR);
> -
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> -
> - /*
> - * Note, the HV=1 case is handled earlier by simply using
> - * spr_write_generic for HV mode in the SPR table
> - */
> -
> - /* Build insertion mask into t1 based on context */
> - gen_load_spr(t1, SPR_AMOR);
> -
> - /* Mask new bits into t2 */
> - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> -
> - /* Load AMR and clear new bits in t0 */
> - gen_load_spr(t0, SPR_IAMR);
> - tcg_gen_andc_tl(t0, t0, t1);
> -
> - /* Or'in new bits and write it out */
> - tcg_gen_or_tl(t0, t0, t2);
> - gen_store_spr(SPR_IAMR, t0);
> - spr_store_dump_spr(SPR_IAMR);
> -
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -#endif /* CONFIG_USER_ONLY */
>
> static void gen_spr_amr(CPUPPCState *env)
> {
> @@ -1390,15 +624,6 @@ static void gen_spr_iamr(CPUPPCState *env)
> }
> #endif /* TARGET_PPC64 */
>
> -#ifndef CONFIG_USER_ONLY
> -static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_fixup_thrm(cpu_env);
> - gen_load_spr(cpu_gpr[gprn], sprn);
> - spr_load_dump_spr(sprn);
> -}
> -#endif /* !CONFIG_USER_ONLY */
> -
> static void gen_spr_thrm(CPUPPCState *env)
> {
> /* Thermal management */
> @@ -1766,57 +991,6 @@ static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> #endif
> }
>
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> -
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> -
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> -
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn],
> - ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> - gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
> -}
> -static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -#endif
> -
> static void gen_spr_usprg3(CPUPPCState *env)
> {
> spr_register(env, SPR_USPRG3, "USPRG3",
> @@ -4897,31 +4071,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
> POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
> }
>
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv val = tcg_temp_new();
> - tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
> - gen_store_spr(SPR_BOOKE_MAS3, val);
> - tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
> - gen_store_spr(SPR_BOOKE_MAS7, val);
> - tcg_temp_free(val);
> -}
> -
> -static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
> -{
> - TCGv mas7 = tcg_temp_new();
> - TCGv mas3 = tcg_temp_new();
> - gen_load_spr(mas7, SPR_BOOKE_MAS7);
> - tcg_gen_shli_tl(mas7, mas7, 32);
> - gen_load_spr(mas3, SPR_BOOKE_MAS3);
> - tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
> - tcg_temp_free(mas3);
> - tcg_temp_free(mas7);
> -}
> -
> -#endif
> -
> enum fsl_e500_version {
> fsl_e500v1,
> fsl_e500v2,
> @@ -7625,58 +6774,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
> #define POWERPC970_HID5_INIT 0x00000000
> #endif
>
> -static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> - int bit, int sprn, int cause)
> -{
> - TCGv_i32 t1 = tcg_const_i32(bit);
> - TCGv_i32 t2 = tcg_const_i32(sprn);
> - TCGv_i32 t3 = tcg_const_i32(cause);
> -
> - gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
> -
> - tcg_temp_free_i32(t3);
> - tcg_temp_free_i32(t2);
> - tcg_temp_free_i32(t1);
> -}
> -
> -static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
> - int bit, int sprn, int cause)
> -{
> - TCGv_i32 t1 = tcg_const_i32(bit);
> - TCGv_i32 t2 = tcg_const_i32(sprn);
> - TCGv_i32 t3 = tcg_const_i32(cause);
> -
> - gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
> -
> - tcg_temp_free_i32(t3);
> - tcg_temp_free_i32(t2);
> - tcg_temp_free_i32(t1);
> -}
> -
> -static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
> -{
> - TCGv spr_up = tcg_temp_new();
> - TCGv spr = tcg_temp_new();
> -
> - gen_load_spr(spr, sprn - 1);
> - tcg_gen_shri_tl(spr_up, spr, 32);
> - tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
> -
> - tcg_temp_free(spr);
> - tcg_temp_free(spr_up);
> -}
> -
> -static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv spr = tcg_temp_new();
> -
> - gen_load_spr(spr, sprn - 1);
> - tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
> - gen_store_spr(sprn - 1, spr);
> -
> - tcg_temp_free(spr);
> -}
> -
> static int check_pow_970(CPUPPCState *env)
> {
> if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
> @@ -7976,24 +7073,6 @@ static void gen_spr_power5p_tb(CPUPPCState *env)
> 0x00000000);
> }
>
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv hmer = tcg_temp_new();
> -
> - gen_load_spr(hmer, sprn);
> - tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
> - gen_store_spr(sprn, hmer);
> - spr_store_dump_spr(sprn);
> - tcg_temp_free(hmer);
> -}
> -
> -static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
> -}
> -#endif /* !defined(CONFIG_USER_ONLY) */
> -
> static void gen_spr_970_lpar(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -8191,18 +7270,6 @@ static void gen_spr_power6_common(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> - spr_read_generic(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> - spr_write_generic(ctx, sprn, gprn);
> -}
> -
> static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TAR, "TAR",
> @@ -8211,30 +7278,6 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> KVM_REG_PPC_TAR, 0x00000000);
> }
>
> -static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_read_generic(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_write_generic(ctx, sprn, gprn);
> -}
> -
> -static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_read_prev_upper32(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_write_prev_upper32(ctx, sprn, gprn);
> -}
> -
> static void gen_spr_power8_tm(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TFHAR, "TFHAR",
> @@ -8255,30 +7298,6 @@ static void gen_spr_power8_tm(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_read_generic(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_write_generic(ctx, sprn, gprn);
> -}
> -
> -static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_read_prev_upper32(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_write_prev_upper32(ctx, sprn, gprn);
> -}
> -
> static void gen_spr_power8_ebb(CPUPPCState *env)
> {
> spr_register(env, SPR_BESCRS, "BESCRS",
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static
2021-05-01 1:05 ` Richard Henderson
@ 2021-05-03 11:28 ` Bruno Piazera Larsen
2021-05-03 15:25 ` Richard Henderson
0 siblings, 1 reply; 25+ messages in thread
From: Bruno Piazera Larsen @ 2021-05-03 11:28 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
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On 30/04/2021 22:05, Richard Henderson wrote:
> On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
>> +++ b/target/ppc/spr_tcg.c.inc
>> @@ -17,6 +17,8 @@
>> * License along with this library; if not, see
>> <http://www.gnu.org/licenses/>.
>> */
>> +#include "spr_tcg.h"
>
> ...
>
>> +++ b/target/ppc/translate_init.c.inc
>> @@ -42,6 +42,7 @@
>> #include "fpu/softfloat.h"
>> #include "qapi/qapi-commands-machine-target.h"
>> +#include "spr_tcg.h"
>> /* #define PPC_DEBUG_SPR */
>> /* #define USE_APPLE_GDB */
>
> Including this header twice, in files that are themselves both
> included in translate.c, is sketchy. You really shouldn't add the one
> to translate_init.c.inc until patch 7, when it becomes the standalone
> cpu_init.c.
Good point, it might be a better idea if we end up going with spr_tcg.c.inc.
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Note for future cleanup: Make spr_tcg.c be standalone as well. Just
> need to move a few declarations to a translate.h.
it's not that easy, unfortunately. The readers and writers use a lot of
global variables declared in translate.c, so we'd need to create getters
and setters, or some better solution, before doing that.
>
>
> r~
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static
2021-05-03 11:28 ` Bruno Piazera Larsen
@ 2021-05-03 15:25 ` Richard Henderson
2021-05-03 20:08 ` Bruno Piazera Larsen
0 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2021-05-03 15:25 UTC (permalink / raw)
To: Bruno Piazera Larsen, qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 5/3/21 4:28 AM, Bruno Piazera Larsen wrote:
>> Note for future cleanup: Make spr_tcg.c be standalone as well. Just need to
>> move a few declarations to a translate.h.
> it's not that easy, unfortunately. The readers and writers use a lot of global
> variables declared in translate.c, so we'd need to create getters and setters,
> or some better solution, before doing that.
No need for getters, and certainly not for setters (all of the globals are
write-once at startup). Just move the declarations into a shared translate.h.
That's what we've done for target/arm/.
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks
2021-05-01 0:55 ` Richard Henderson
@ 2021-05-03 20:07 ` Bruno Piazera Larsen
0 siblings, 0 replies; 25+ messages in thread
From: Bruno Piazera Larsen @ 2021-05-03 20:07 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
[-- Attachment #1: Type: text/plain, Size: 1514 bytes --]
On 30/04/2021 21:55, Richard Henderson wrote:
> On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
>> Moved all SPR read/write callback, and some related functions, to a
>> new file specific for it. These callbacks are TCG only, so separating
>> them is required to support the build flag disable-tcg.
>>
>> Making the spr_noaccess function not static, and moving the define to
>> internal.h is required, otherwise the project doesn't build
>
> Why is that? You're moving the code to a different file, but then
> including that file back into the same translation unit. There should
> be no change in which symbols appear in which object file.
>
> I think that the spr_noaccess move might be required by patch 7, but
> that's something different.
>
ah, yes, forgot to specify why. gen_op_mfspr uses SPR_NOACCESS on line
4284. At some point I thought I tried to include spr_tcg.c.inc before
that function and the compilation failed, so I decided to include it
where translate_init.c.inc was included. I think it was another function
that was declared later, but can't remember which
Testing now I verified that I can include it there, so I will do it and
delay the move to patch 7, no problem
>
> r~
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static
2021-05-03 15:25 ` Richard Henderson
@ 2021-05-03 20:08 ` Bruno Piazera Larsen
0 siblings, 0 replies; 25+ messages in thread
From: Bruno Piazera Larsen @ 2021-05-03 20:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
[-- Attachment #1: Type: text/plain, Size: 1118 bytes --]
On 03/05/2021 12:25, Richard Henderson wrote:
> On 5/3/21 4:28 AM, Bruno Piazera Larsen wrote:
>>> Note for future cleanup: Make spr_tcg.c be standalone as well. Just
>>> need to move a few declarations to a translate.h.
>> it's not that easy, unfortunately. The readers and writers use a lot
>> of global variables declared in translate.c, so we'd need to create
>> getters and setters, or some better solution, before doing that.
>
> No need for getters, and certainly not for setters (all of the globals
> are write-once at startup). Just move the declarations into a shared
> translate.h. That's what we've done for target/arm/.
Ah, I can take a look later, but this would be pretty low priority
compared to what is being requested of us right now. And that's if we
separate it like that anyway
>
>
> r~
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks
2021-05-03 4:54 ` David Gibson
@ 2021-05-03 20:15 ` Bruno Piazera Larsen
2021-05-04 0:28 ` David Gibson
0 siblings, 1 reply; 25+ messages in thread
From: Bruno Piazera Larsen @ 2021-05-03 20:15 UTC (permalink / raw)
To: David Gibson
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
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On 03/05/2021 01:54, David Gibson wrote:
> On Fri, Apr 30, 2021 at 04:35:28PM -0300, Bruno Larsen (billionai) wrote:
>> Moved all SPR read/write callback, and some related functions, to a
>> new file specific for it. These callbacks are TCG only, so separating
>> them is required to support the build flag disable-tcg.
>>
>> Making the spr_noaccess function not static, and moving the define to
>> internal.h is required, otherwise the project doesn't build
>>
>> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
>> ---
>> target/ppc/internal.h | 3 +
>> target/ppc/spr_tcg.c.inc | 1052 +++++++++++++++++++++++++++++++
>> target/ppc/translate.c | 47 +-
>> target/ppc/translate_init.c.inc | 981 ----------------------------
>> 4 files changed, 1056 insertions(+), 1027 deletions(-)
>> create mode 100644 target/ppc/spr_tcg.c.inc
> Hmm. So, I'm still pretty ambivalent about the creation of
> spr_tcg.c.inc. The separation between it and translate.c just seems
> rather arbitrary to me.
>
> Yes, translate.c is overly huge, but I'm not sure going from
> overly-huge to overly-huger really makes anything worse, and would
> avoid some of the dancing around to handle the new file.
>
> So for now, I'm inclined to suggest just moving the spr callbacks from
> translate_init.c.inc to translate.c. And some day, I hope someone has
> time to split up translate.c based on CPU family, which I think is a
> more useful way to make it less huge.
Ok. I agree that the improved is pretty minor, I was just thinking it
was probably better than nothing... I'll work on that tomorrow and will
have a new version.
When I do, should I put the many e-mail IDs that hold required patches
as "Based-on" tags, or should I just say ppc-for-6.1? I'm still a bit
lost when dealing with patchew and these things...
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks
2021-05-03 20:15 ` Bruno Piazera Larsen
@ 2021-05-04 0:28 ` David Gibson
0 siblings, 0 replies; 25+ messages in thread
From: David Gibson @ 2021-05-04 0:28 UTC (permalink / raw)
To: Bruno Piazera Larsen
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 2447 bytes --]
On Mon, May 03, 2021 at 05:15:38PM -0300, Bruno Piazera Larsen wrote:
>
> On 03/05/2021 01:54, David Gibson wrote:
> > On Fri, Apr 30, 2021 at 04:35:28PM -0300, Bruno Larsen (billionai) wrote:
> > > Moved all SPR read/write callback, and some related functions, to a
> > > new file specific for it. These callbacks are TCG only, so separating
> > > them is required to support the build flag disable-tcg.
> > >
> > > Making the spr_noaccess function not static, and moving the define to
> > > internal.h is required, otherwise the project doesn't build
> > >
> > > Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> > > ---
> > > target/ppc/internal.h | 3 +
> > > target/ppc/spr_tcg.c.inc | 1052 +++++++++++++++++++++++++++++++
> > > target/ppc/translate.c | 47 +-
> > > target/ppc/translate_init.c.inc | 981 ----------------------------
> > > 4 files changed, 1056 insertions(+), 1027 deletions(-)
> > > create mode 100644 target/ppc/spr_tcg.c.inc
> > Hmm. So, I'm still pretty ambivalent about the creation of
> > spr_tcg.c.inc. The separation between it and translate.c just seems
> > rather arbitrary to me.
> >
> > Yes, translate.c is overly huge, but I'm not sure going from
> > overly-huge to overly-huger really makes anything worse, and would
> > avoid some of the dancing around to handle the new file.
> >
> > So for now, I'm inclined to suggest just moving the spr callbacks from
> > translate_init.c.inc to translate.c. And some day, I hope someone has
> > time to split up translate.c based on CPU family, which I think is a
> > more useful way to make it less huge.
>
> Ok. I agree that the improved is pretty minor, I was just thinking it was
> probably better than nothing... I'll work on that tomorrow and will have a
> new version.
>
> When I do, should I put the many e-mail IDs that hold required patches as
> "Based-on" tags, or should I just say ppc-for-6.1? I'm still a bit lost when
> dealing with patchew and these things...
You can just say it's against ppc-for-6.1 in the cover letter. Since
it's an explicitly ppc specific patchset, and the main audience is me
there's no need to get too complicated.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2021-05-04 0:49 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
2021-04-30 19:35 ` [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro Bruno Larsen (billionai)
2021-05-01 0:27 ` Richard Henderson
2021-05-03 4:37 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks Bruno Larsen (billionai)
2021-05-01 0:55 ` Richard Henderson
2021-05-03 20:07 ` Bruno Piazera Larsen
2021-05-03 4:54 ` David Gibson
2021-05-03 20:15 ` Bruno Piazera Larsen
2021-05-04 0:28 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions Bruno Larsen (billionai)
2021-05-01 0:58 ` Richard Henderson
2021-05-03 4:39 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
2021-05-01 1:05 ` Richard Henderson
2021-05-03 11:28 ` Bruno Piazera Larsen
2021-05-03 15:25 ` Richard Henderson
2021-05-03 20:08 ` Bruno Piazera Larsen
2021-04-30 19:35 ` [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration Bruno Larsen (billionai)
2021-05-01 1:06 ` Richard Henderson
2021-05-03 4:47 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 6/7] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
2021-05-03 4:49 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
2021-05-01 1:11 ` Richard Henderson
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