From: David Gibson <david@gibson.dropbear.id.au>
To: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Cc: farosas@linux.ibm.com, richard.henderson@linaro.org,
qemu-devel@nongnu.org, lucas.araujo@eldorado.org.br,
fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org,
matheus.ferst@eldorado.org.br, luis.pires@eldorado.org.br
Subject: Re: [PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers
Date: Wed, 5 May 2021 14:10:45 +1000 [thread overview]
Message-ID: <YJIaxQJhhfFLOhb9@yekko> (raw)
In-Reply-To: <20210504140157.76066-2-bruno.larsen@eldorado.org.br>
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On Tue, May 04, 2021 at 11:01:53AM -0300, Bruno Larsen (billionai) wrote:
> folded gen_{read,write}_xer into their only callers, spr_{read,write}_xer
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Good cleanup on its own. Applied to ppc-for-6.1.
> ---
> target/ppc/translate.c | 37 ---------------------------------
> target/ppc/translate_init.c.inc | 33 +++++++++++++++++++++++++++--
> 2 files changed, 31 insertions(+), 39 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index b319d409c6..2f10aa2fea 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4175,43 +4175,6 @@ static void gen_tdi(DisasContext *ctx)
>
> /*** Processor control ***/
>
> -static void gen_read_xer(DisasContext *ctx, TCGv dst)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> - tcg_gen_mov_tl(dst, cpu_xer);
> - tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> - tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> - tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> - tcg_gen_or_tl(t0, t0, t1);
> - tcg_gen_or_tl(dst, dst, t2);
> - tcg_gen_or_tl(dst, dst, t0);
> - if (is_isa300(ctx)) {
> - tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> - tcg_gen_or_tl(dst, dst, t0);
> - tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> - tcg_gen_or_tl(dst, dst, t0);
> - }
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void gen_write_xer(TCGv src)
> -{
> - /* Write all flags, while reading back check for isa300 */
> - tcg_gen_andi_tl(cpu_xer, src,
> - ~((1u << XER_SO) |
> - (1u << XER_OV) | (1u << XER_OV32) |
> - (1u << XER_CA) | (1u << XER_CA32)));
> - tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> - tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> - tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> - tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> - tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> -}
> -
> /* mcrxr */
> static void gen_mcrxr(DisasContext *ctx)
> {
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index d10d7e5bf6..d5527c149f 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -116,12 +116,41 @@ static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
> /* XER */
> static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
> {
> - gen_read_xer(ctx, cpu_gpr[gprn]);
> + TCGv dst = cpu_gpr[gprn];
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> + tcg_gen_mov_tl(dst, cpu_xer);
> + tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> + tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> + tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> + tcg_gen_or_tl(t0, t0, t1);
> + tcg_gen_or_tl(dst, dst, t2);
> + tcg_gen_or_tl(dst, dst, t0);
> + if (is_isa300(ctx)) {
> + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> + tcg_gen_or_tl(dst, dst, t0);
> + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> + tcg_gen_or_tl(dst, dst, t0);
> + }
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> }
>
> static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
> {
> - gen_write_xer(cpu_gpr[gprn]);
> + TCGv src = cpu_gpr[gprn];
> + /* Write all flags, while reading back check for isa300 */
> + tcg_gen_andi_tl(cpu_xer, src,
> + ~((1u << XER_SO) |
> + (1u << XER_OV) | (1u << XER_OV32) |
> + (1u << XER_CA) | (1u << XER_CA32)));
> + tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> + tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> + tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> + tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> + tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> }
>
> /* LR */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2021-05-05 4:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-04 14:01 [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Bruno Larsen (billionai)
2021-05-04 14:01 ` [PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers Bruno Larsen (billionai)
2021-05-05 4:10 ` David Gibson [this message]
2021-05-04 14:01 ` [PATCH v4 2/5] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
2021-05-04 15:59 ` Richard Henderson
2021-05-05 4:11 ` David Gibson
2021-05-04 14:01 ` [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c Bruno Larsen (billionai)
2021-05-04 16:08 ` Richard Henderson
2021-05-05 4:14 ` David Gibson
2021-05-04 14:01 ` [PATCH v4 4/5] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
2021-05-04 16:40 ` Richard Henderson
2021-05-04 14:01 ` [PATCH v4 5/5] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
2021-05-04 20:38 ` [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Fabiano Rosas
2021-05-05 11:30 ` Bruno Piazera Larsen
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