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From: David Gibson <david@gibson.dropbear.id.au>
To: matheus.ferst@eldorado.org.br
Cc: richard.henderson@linaro.org, qemu-devel@nongnu.org,
	f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org,
	lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br
Subject: Re: [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception*
Date: Thu, 13 May 2021 14:06:23 +1000	[thread overview]
Message-ID: <YJylv/uVtiZwdfA+@yekko> (raw)
In-Reply-To: <20210512185441.3619828-4-matheus.ferst@eldorado.org.br>

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On Wed, May 12, 2021 at 03:54:13PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
> 
> There are other valid settings for is_jmp besides
> DISAS_NEXT and DISAS_NORETURN, so eliminating that
> dichotomy from ppc_tr_translate_insn is helpful.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>

Applied to ppc-for-6.1, thanks.

> ---
>  target/ppc/translate.c | 26 ++++++++++++++++++--------
>  1 file changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 3ad4c7163d..616ffc1508 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -261,7 +261,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
>      gen_helper_raise_exception_err(cpu_env, t0, t1);
>      tcg_temp_free_i32(t0);
>      tcg_temp_free_i32(t1);
> -    ctx->exception = (excp);
> +    ctx->exception = excp;
> +    ctx->base.is_jmp = DISAS_NORETURN;
>  }
>  
>  static void gen_exception(DisasContext *ctx, uint32_t excp)
> @@ -278,7 +279,8 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
>      t0 = tcg_const_i32(excp);
>      gen_helper_raise_exception(cpu_env, t0);
>      tcg_temp_free_i32(t0);
> -    ctx->exception = (excp);
> +    ctx->exception = excp;
> +    ctx->base.is_jmp = DISAS_NORETURN;
>  }
>  
>  static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> @@ -290,7 +292,8 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
>      t0 = tcg_const_i32(excp);
>      gen_helper_raise_exception(cpu_env, t0);
>      tcg_temp_free_i32(t0);
> -    ctx->exception = (excp);
> +    ctx->exception = excp;
> +    ctx->base.is_jmp = DISAS_NORETURN;
>  }
>  
>  /*
> @@ -336,6 +339,7 @@ static void gen_debug_exception(DisasContext *ctx)
>      t0 = tcg_const_i32(EXCP_DEBUG);
>      gen_helper_raise_exception(cpu_env, t0);
>      tcg_temp_free_i32(t0);
> +    ctx->base.is_jmp = DISAS_NORETURN;
>  }
>  
>  static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
> @@ -9374,7 +9378,6 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
>      DisasContext *ctx = container_of(dcbase, DisasContext, base);
>  
>      gen_debug_exception(ctx);
> -    dcbase->is_jmp = DISAS_NORETURN;
>      /*
>       * The address covered by the breakpoint must be included in
>       * [tb->pc, tb->pc + tb->size) in order to for it to be properly
> @@ -9404,18 +9407,19 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
>      ok = decode_legacy(cpu, ctx, insn);
>      if (!ok) {
>          gen_invalid(ctx);
> -        ctx->base.is_jmp = DISAS_NORETURN;
>      }
>  
>  #if defined(DO_PPC_STATISTICS)
>      handler->count++;
>  #endif
> +
>      /* Check trace mode exceptions */
>      if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
>                   (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
>                   ctx->exception != POWERPC_SYSCALL &&
>                   ctx->exception != POWERPC_EXCP_TRAP &&
> -                 ctx->exception != POWERPC_EXCP_BRANCH)) {
> +                 ctx->exception != POWERPC_EXCP_BRANCH &&
> +                 ctx->base.is_jmp != DISAS_NORETURN)) {
>          uint32_t excp = gen_prep_dbgex(ctx);
>          gen_exception_nip(ctx, excp, ctx->base.pc_next);
>      }
> @@ -9426,14 +9430,20 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
>                   opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
>      }
>  
> -    ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
> -        DISAS_NEXT : DISAS_NORETURN;
> +    if (ctx->base.is_jmp == DISAS_NEXT
> +        && ctx->exception != POWERPC_EXCP_NONE) {
> +        ctx->base.is_jmp = DISAS_TOO_MANY;
> +    }
>  }
>  
>  static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
>  {
>      DisasContext *ctx = container_of(dcbase, DisasContext, base);
>  
> +    if (ctx->base.is_jmp == DISAS_NORETURN) {
> +        return;
> +    }
> +
>      if (ctx->exception == POWERPC_EXCP_NONE) {
>          gen_goto_tb(ctx, 0, ctx->base.pc_next);
>      } else if (ctx->exception != POWERPC_EXCP_BRANCH) {

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2021-05-13  4:33 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 01/31] target/ppc: Add cia field to DisasContext matheus.ferst
2021-05-13  4:03   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 02/31] target/ppc: Split out decode_legacy matheus.ferst
2021-05-13  4:03   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception* matheus.ferst
2021-05-13  4:06   ` David Gibson [this message]
2021-05-12 18:54 ` [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL matheus.ferst
2021-05-13  4:06   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP matheus.ferst
2021-05-13  4:07   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception matheus.ferst
2021-05-13  4:08   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} matheus.ferst
2021-05-13  4:10   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
2021-05-12 19:31   ` Bruno Piazera Larsen
2021-05-13  4:11   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls matheus.ferst
2021-05-13  4:12   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-12 19:21   ` Matheus K. Ferst
2021-05-13  4:14     ` David Gibson
2021-05-12 18:54 ` [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-12 18:54 ` [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-12 18:54 ` [PATCH v4 13/31] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-12 18:54 ` [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-12 18:54 ` [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-12 18:54 ` [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-12 19:45   ` Bruno Piazera Larsen
2021-05-12 18:54 ` [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-12 18:54 ` [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-12 18:54 ` [PATCH v4 22/31] target/ppc: Implement PNOP matheus.ferst
2021-05-13 10:37   ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 23/31] TCG: add tcg_constant_tl matheus.ferst
2021-05-13 10:42   ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-12 18:54 ` [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-13 10:50   ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-12 18:54 ` [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-13 11:01   ` Richard Henderson
2021-05-13 11:43     ` Matheus K. Ferst
2021-05-12 18:54 ` [PATCH v4 29/31] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-13 11:31   ` Richard Henderson
2021-05-13 12:24     ` Matheus K. Ferst
2021-05-14  0:01       ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 30/31] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-13 11:36   ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 31/31] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-13 11:40   ` Richard Henderson
2021-05-13  4:22 ` [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions David Gibson

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