On Wed, Dec 15, 2021 at 10:35:34AM -0500, Jagannathan Raman wrote:
> +static ssize_t vfu_object_bar_rw(PCIDevice *pci_dev, hwaddr addr, size_t count,
> +                                 char * const buf, const bool is_write,
> +                                 bool is_io)
> +{
> +    AddressSpace *as = NULL;
> +    MemTxResult res;
> +
> +    if (is_io) {
> +        as = &address_space_io;
> +    } else {
> +        as = pci_device_iommu_address_space(pci_dev);

This access is not initiated by the device, it's coming from the CPU. It
shouldn't go through the IOMMU address space.