From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org, Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH] target/mips: Allow executing MSA instructions on Loongson-3A4000
Date: Mon, 7 Dec 2020 23:27:34 +0100 [thread overview]
Message-ID: <a009ebd9-fd09-0a52-94e9-1acc435888eb@amsat.org> (raw)
In-Reply-To: <20201130102228.2395100-1-f4bug@amsat.org>
On 11/30/20 11:22 AM, Philippe Mathieu-Daudé wrote:
> The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html
>
> Commit af868995e1b correctly set the 'MSA present' bit of Config3
> register, but forgot to allow the MSA instructions decoding in
> insn_flags, so executing them triggers a 'Reserved Instruction'.
>
> Fix by adding the ASE_MSA mask to insn_flags.
>
> Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Buggy since 5.1, so probably not a big deal.
> ---
> target/mips/translate_init.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Thanks, applied to mips-next.
prev parent reply other threads:[~2020-12-07 22:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-30 10:22 [PATCH] target/mips: Allow executing MSA instructions on Loongson-3A4000 Philippe Mathieu-Daudé
2020-11-30 18:22 ` Richard Henderson
2020-12-02 0:31 ` chen huacai
2020-12-07 22:27 ` Philippe Mathieu-Daudé [this message]
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