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Sun, 19 Sep 2021 10:49:28 -0700 (PDT) Received: from [192.168.1.11] ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g140sm11417202pfb.100.2021.09.19.10.49.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 19 Sep 2021 10:49:27 -0700 (PDT) Subject: Re: [PATCH v2 24/30] linux-user/openrisc: Use force_sig_fault, force_sigsegv_for_addr To: Peter Maydell References: <20210822035537.283193-1-richard.henderson@linaro.org> <20210822035537.283193-25-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Sun, 19 Sep 2021 10:49:26 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Developers , Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/24/21 10:17 AM, Peter Maydell wrote: > I think that EXCP_RANGE should for us be unreachable in user-only > mode (because it can only happen if the relevant bits in SR are > set, and SR is writeable only in supervisor mode, and its starting > value doesn't set these bits). So we could just delete the EXCP_RANGE > handling and let it hit the default g_assert_not_reached() case. If I also disable the SR case from gdbstub. > EXCP_FPE is more tricky -- this happens for FP exceptions, where > the enabling bit is in the FPCSR, which does appear to be writeable > from user mode. So either: > * our mtspr is wrong and should either be not allowing writes > to FPCSR in usermode (or at least sanitizing them) > * the Linux kernel for openrisc is wrong, because a userspace > program that sets FPCSR.FPEE can make it run into unhandled_exception() > and die(), and it should be doing something else, like delivering > a suitable SIGFPE I believe the kernel to be buggy. But it also point to the fact that no one has written fenv.h for or1k for musl, so no one has tried to use those bits. r~