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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id 84sm1035165pgg.90.2020.02.12.21.39.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2020 21:39:18 -0800 (PST) Subject: Re: [RESEND RFC PATCH v2 1/2] target/arm: Allow to inject SError interrupt To: Gavin Shan , Peter Maydell References: <20200205110541.37811-2-gshan@redhat.com> <8dce7dbe-c6c1-122a-f960-0fc29257dd1c@redhat.com> <21e4051a-4d06-03cb-6d8e-5331b5b570c4@redhat.com> From: Richard Henderson Message-ID: Date: Wed, 12 Feb 2020 21:39:15 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <21e4051a-4d06-03cb-6d8e-5331b5b570c4@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , jthierry@redhat.com, Alexey Kardashevskiy , Marc Zyngier , QEMU Developers , Eric Auger , qemu-arm , Shan Gavin , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/12/20 7:49 PM, Gavin Shan wrote: > On 2/12/20 10:34 PM, Peter Maydell wrote: >> Yeah, this is on my list to look at; Richard Henderson also could >> have a look at it. From a quick scan I suspect you may be missing >> handling for AArch32. >> > > [Thanks for copying Richard Henderson] > > Yes, the functionality is only supported on aarch64 currently by intention > because the next patch enables it on "max" and "host" CPU models and both > of them are running in aarch64 mode. We shouldn't leave the aarch32 exception entry paths unimplemented though. C.f. AArch32.TakePhysicalSErrorException() AArch32.TakeVirtualSErrorException() It really shouldn't be more than a couple of lines, just like arm_cpu_do_interrupt_aarch64. Remember both arm_cpu_do_interrupt_aarch32 and arm_cpu_do_interrupt_aarch32_hyp. > However, it seems there is a long list of aarch32 CPU models, defined > in target/arm/cpu.c::arm_cpus. so which CPU models you prefer to see with > this supported? I think we might choose one or two popular CPU models if > you agree. Even qemu-system-aarch64 -cpu max can exercise this path when EL1 is running in aarch32 mode. Admittedly it would be easier if we had the rest of the plumbing so that -cpu max,aarch64=off worked. FWIW, the rest of the patch looks good. r~