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[174.21.143.238]) by smtp.googlemail.com with ESMTPSA id m18sm2803067pjl.14.2020.06.03.09.09.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Jun 2020 09:09:52 -0700 (PDT) Subject: Re: [PATCH] tcg: Sanitize shift constants on ppc64le so that shift operations with large constants don't generate invalid instructions. To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , agrecascino123@gmail.com, qemu-devel@nongnu.org References: <20200603052308.11744-1-agrecascino123@gmail.com> <2a0fa3cb-9527-ae8b-e89b-2af08e2f54f4@amsat.org> From: Richard Henderson Autocrypt: addr=rth@twiddle.net; prefer-encrypt=mutual; keydata= mQENBFGuLC8BCADcAoWcnW9lTsDMzbO3MBU+KbiGaj5JPatEUscRDkQYM2fyNjJp2tIWDK5a n4yngeXB3eX61WbYR3QraRK8mlYLGxyAdHMEQfPipbqf3TmN043fssT2bc82ApJcs1zvLYgI rhMht7Dck7A0wNC1jo+ZjVVFig5gDTN7gOzaAdBtV8tVNUddwkLzzaGpfihhSD6U46NdqKOG Wlnn6TrkMy0QGdQ5NaXHkRlUjnnUTSW/nKfoxD+EI+A9V4sYOd8mc/TL4aJh/i/AiU57eLbo n17uQI6/VTWDUWl8USiz4x9c8vmqlywLx00tAFxxoRWqk4KVJlj+Sh0up/D/sJ+vPpgBABEB AAG0I1JpY2hhcmQgSGVuZGVyc29uIDxydGhAdHdpZGRsZS5uZXQ+iQFYBBMBAgBCAhsDBgsJ CAcDAgYVCAIJCgsEFgIDAQIeAQIXgAIZARYhBJyxjdr46EmtKvwWpK0ScMxN0CebBQJdweUY BQkP1h/pAAoJEK0ScMxN0CebqDsH/0YyfnXk+Dc++H37VCEKgRet2i1ATFzxRnifkvmdxha0 V+PVptQ2fwSe+w3KxoFecD8W75nysmUjrU/FicW9yU5YRlGONPZjruG02/KzmhA5PzWJdYO3 i/t0qRayvWIcX2qA/flsXEbmb/BbAFM05LQIdcOu74eiBFe5CBCOWBDJeneE1urIE0hSYxoh nCcG60ULrNj13ohZ4zAEluoY32qIo7/OPWmtR88cPrEbZT8k+RqgZbsotzaPT1/RlL74fL8k ofYfTgKAFH7eEy6fF2nzDp2GThVn+3sA62xtpSXUf/X1m75B40KOcq1EQbHypNTmBc1wt13e ibhPNEVX2am5AQ0EUa4sLwEIALITHfH3gciRNfQIe7awDTDvn6H3C6gDyCAnv5LiuLTLZiyK NZp3lNO3rPowyKrGT2RIDlumlqPgdeHzqEEX91YK0yk2vdFvwU04rJ4D+qRgdUPoeICLD1zo PwOv2FaY6Tf8dKYas1RHF5QU5yQNey8j7IYYoE2yGPn2PtBmvtmK4iLataUEvx0U385Zr+jf HscqwTiToryeDC8Io/9BsMvAssE5Yf5URS2nJ7LFOvc4njsQJPF1i9egBXaIloqv7p2hVCKJ Hl5UWIxitQ9QQIl6iU4LCpz8mVYTXwv48IAVpbUf7+ak9V9Kk3jCeQnlxCJBUHjUhoIzinbS JHPHtkkAEQEAAYkBPAQYAQIAJgIbDBYhBJyxjdr46EmtKvwWpK0ScMxN0CebBQJdweVIBQkP 1iAZAAoJEK0ScMxN0CebGHUH/RtouOlWl6To97tQsTJUq/2YwmRpFOsvV0/zCX4fKBGAbeZi VaELSt2+3UEErA+n8HwbQmjJ6IrdhA9GustOpOyCcbLVSMwql/OlAwBtDzCcC8dTU4zcuY2a rGG2A8i5krU85G9r1wowVcWZBsdmW7/dKiNoadLQiig4bHNiSaV4ograas5efyEjqTxiY+yG hzPw5DK2kbp2co8iDF1vW0LWPeLFBinCgItcI9LvgHWaB3rwjOfvNpMn5m64SoQYHB8wbnid erAjOzkBzmqnfS1tAUr8mtESStEwrEmNv0ZoA6S0Wt+c9pyTr+BpG4OFlhj7ZI+Eh7zOrr33 q9OBIdA= Message-ID: Date: Wed, 3 Jun 2020 09:09:49 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <2a0fa3cb-9527-ae8b-e89b-2af08e2f54f4@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=rth7680@gmail.com; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Catherine A. Frederick" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/2/20 11:43 PM, Philippe Mathieu-Daudé wrote: > > Hi Catherine, > > On 6/3/20 7:23 AM, agrecascino123@gmail.com wrote: >> From: "Catherine A. Frederick" >> >> Signed-off-by: "Catherine A. Frederick" >> --- >> tcg/ppc/tcg-target.inc.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c >> index ee1f9227c1..a5450a5e67 100644 >> --- a/tcg/ppc/tcg-target.inc.c >> +++ b/tcg/ppc/tcg-target.inc.c >> @@ -790,21 +790,25 @@ static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) >> >> static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) >> { >> + c = ((unsigned)c > 32) ? 32 : c; >> tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); >> } >> >> static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) >> { >> + c = ((unsigned)c > 64) ? 64 : c; >> tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); >> } >> >> static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) >> { >> + c = ((unsigned)c > 32) ? 32 : c; >> tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); >> } >> >> static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) >> { >> + c = ((unsigned)c > 64) ? 64 : c; >> tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); >> } > > I agree there is a bug, but I am not sure we should silently cap the > value this way. I'd rather see the caller provide a value in range, and > maybe the callee use 'tcg_debug_assert(c <= RANGE);' to catch future new > caller added missing the range check. We have done this before: see 1fd95946657. In tcg/README, we note that out-of-range shifts produce undefined results, but should not trap with illegal instruction. I would like to know more about where these out-of-range shifts are being generated, but I do know that there are innocent ways by which this can happen. For instance, one way in which we can translate a guest in which out-of-range shifts produce zero is x = (shift < 32 ? y << shift : 0) using INDEX_op_movcond_i32 for the ?: operator. Which means that we use the original (out-of-range) shift and subsequently discard the undefined result. Catherine, I think it would be more appropriate to mask C rather than bound it to another out-of-range value: c &= 31 or c &= 64, with a comment about avoiding an illegal instruction, just as in the tcg/sparc patch I reference above. r~