From: David Hildenbrand <david@redhat.com>
To: Cornelia Huck <cohuck@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>,
Janosch Frank <frankja@linux.ibm.com>,
qemu-devel@nongnu.org, Halil Pasic <pasic@linux.ibm.com>,
Christian Borntraeger <borntraeger@de.ibm.com>,
qemu-s390x@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH-for-4.2 v2 2/6] s390x/tcg: Rework MMU selection for instruction fetches
Date: Thu, 15 Aug 2019 18:52:00 +0200 [thread overview]
Message-ID: <a5041477-68a1-e5cb-97aa-fa65f2b5c9c8@redhat.com> (raw)
In-Reply-To: <20190815174330.3d66bd2c.cohuck@redhat.com>
On 15.08.19 17:43, Cornelia Huck wrote:
> On Wed, 14 Aug 2019 09:23:51 +0200
> David Hildenbrand <david@redhat.com> wrote:
>
>> Instructions are always fetched from primary address space, except when
>> in home address mode. Perform the selection directly in cpu_mmu_index().
>>
>> get_mem_index() is only used to perform data access, instructions are
>> fetched via cpu_lduw_code(), which translates to cpu_mmu_index(env, true).
>>
>> We don't care about restricting the access permissions of the TLB
>> entries anymore, as we no longer enter PRIMARY entries into the
>> SECONDARY MMU. Cleanup related code a bit.
>>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>> target/s390x/cpu.h | 7 +++++++
>> target/s390x/mmu_helper.c | 38 +++++++++++++++-----------------------
>> 2 files changed, 22 insertions(+), 23 deletions(-)
>>
>
> (...)
>
>> diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
>> index 6e9c4d6151..c34e8d2021 100644
>> --- a/target/s390x/mmu_helper.c
>> +++ b/target/s390x/mmu_helper.c
>> @@ -349,8 +349,9 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
>> {
>> static S390SKeysState *ss;
>> static S390SKeysClass *skeyclass;
>> - int r = -1;
>> + uint64_t asce;
>> uint8_t key;
>> + int r;
>>
>> if (unlikely(!ss)) {
>> ss = s390_get_skeys_device();
>> @@ -380,36 +381,21 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
>>
>> if (!(env->psw.mask & PSW_MASK_DAT)) {
>> *raddr = vaddr;
>> - r = 0;
>> - goto out;
>> + goto nodat;
>> }
>>
>> switch (asc) {
>> case PSW_ASC_PRIMARY:
>> PTE_DPRINTF("%s: asc=primary\n", __func__);
>> - r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
>> - rw, exc);
>> + asce = env->cregs[1];
>> break;
>> case PSW_ASC_HOME:
>> PTE_DPRINTF("%s: asc=home\n", __func__);
>> - r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
>> - rw, exc);
>> + asce = env->cregs[13];
>> break;
>> case PSW_ASC_SECONDARY:
>> PTE_DPRINTF("%s: asc=secondary\n", __func__);
>> - /*
>> - * Instruction: Primary
>> - * Data: Secondary
>> - */
>> - if (rw == MMU_INST_FETCH) {
>> - r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
>> - raddr, flags, rw, exc);
>> - *flags &= ~(PAGE_READ | PAGE_WRITE);
>> - } else {
>> - r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
>> - raddr, flags, rw, exc);
>> - *flags &= ~(PAGE_EXEC);
>> - }
>> + asce = env->cregs[7];
>> break;
>> case PSW_ASC_ACCREG:
>> default:
>> @@ -417,11 +403,17 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
>> break;
>> }
>>
>> - out:
>> + /* perform the DAT translation */
>> + r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw, exc);
>> + if (r) {
>> + return r;
>> + }
>> +
>> +nodat:
>> /* Convert real address -> absolute address */
>> *raddr = mmu_real2abs(env, *raddr);
>>
>> - if (r == 0 && *raddr < ram_size) {
>> + if (*raddr < ram_size) {
>> if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
>> trace_get_skeys_nonzero(r);
>
> I think you might up here with an uninitialized r before patch 4?
Right, will reshuffle. Thanks!
--
Thanks,
David / dhildenb
next prev parent reply other threads:[~2019-08-15 17:06 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-14 7:23 [Qemu-devel] [PATCH-for-4.2 v2 0/6] s390x/mmu: Storage key reference and change bit handling David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 1/6] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug() David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 2/6] s390x/tcg: Rework MMU selection for instruction fetches David Hildenbrand
2019-08-14 17:44 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-15 15:43 ` [Qemu-devel] " Cornelia Huck
2019-08-15 16:52 ` David Hildenbrand [this message]
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE David Hildenbrand
2019-08-14 10:06 ` Alex Bennée
2019-08-14 10:21 ` David Hildenbrand
2019-08-14 10:44 ` Alex Bennée
2019-08-14 10:51 ` David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 4/6] s390x/mmu: Trace the right value if setting/getting the storage key fails David Hildenbrand
2019-08-14 17:50 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-15 15:39 ` Cornelia Huck
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 5/6] s390x/mmu: Better storage key reference and change bit handling David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling David Hildenbrand
2019-08-14 18:01 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-14 18:18 ` David Hildenbrand
2019-08-19 16:36 ` [Qemu-devel] [PATCH-for-4.2 v2 0/6] s390x/mmu: Storage key reference and change bit handling Cornelia Huck
2019-08-19 16:37 ` Cornelia Huck
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a5041477-68a1-e5cb-97aa-fa65f2b5c9c8@redhat.com \
--to=david@redhat.com \
--cc=borntraeger@de.ibm.com \
--cc=cohuck@redhat.com \
--cc=frankja@linux.ibm.com \
--cc=pasic@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=rth@twiddle.net \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).