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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id p24sm16893088pff.69.2020.01.27.16.04.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Jan 2020 16:04:49 -0800 (PST) Subject: Re: [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime To: Peter Maydell References: <20191203022937.1474-1-richard.henderson@linaro.org> <20191203022937.1474-30-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 27 Jan 2020 16:04:46 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/6/19 9:05 AM, Peter Maydell wrote: > On Tue, 3 Dec 2019 at 02:30, Richard Henderson > wrote: >> >> Since we only support a single ASID, flush the tlb when it changes. >> >> Signed-off-by: Richard Henderson >> --- >> target/arm/helper.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 9df55a8d6b..2a4d4c2c0d 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -3740,6 +3740,15 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, >> static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, >> uint64_t value) >> { >> + /* >> + * If we are running with E2&0 regime, then the ASID is active. >> + * Flush if that changes. >> + */ >> + if ((arm_hcr_el2_eff(env) & HCR_E2H) && >> + extract64(raw_read(env, ri) ^ value, 48, 16)) { >> + tlb_flush_by_mmuidx(env_cpu(env), >> + ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0); >> + } >> raw_write(env, ri, value); >> } > > For the existing EL1 setup we have separate write functions > for TTBR registers and for TCR_EL1 (vmsa_tcr_el1_write() > and vmsa_ttbr_write()), rather than a single one, and they > don't do the same thing. Why do we use a single writefn > here? It looks particularly odd because we're actually looking > at the value written here. Yes, Laurent noticed the same problem wrt patch 4. Fixed. r~