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From: "Cédric Le Goater" <clg@kaod.org>
To: Andrew Jeffery <andrew@aj.id.au>, Peter Delevoryas <pdel@fb.com>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	Joel Stanley <joel@jms.id.au>,
	Cameron Esfahani via <qemu-devel@nongnu.org>
Subject: Re: [PATCH 2/5] hw/arm/aspeed: Select console UART from machine
Date: Tue, 31 Aug 2021 15:34:35 +0200	[thread overview]
Message-ID: <a802ecb1-aa49-fd4c-5bd2-2bb19af56ac9@kaod.org> (raw)
In-Reply-To: <d3d43c7a-1f37-4489-a07b-bf561e4e36a1@www.fastmail.com>

On 8/31/21 1:23 PM, Andrew Jeffery wrote:
> Hi Cédric, Peter,
> On Tue, 31 Aug 2021, at 20:09, Cédric Le Goater wrote:
>> On 8/28/21 5:58 PM, Peter Delevoryas wrote:
>>> I think I’m a little confused on this part. What I meant by “most machines just use UART5” was that most DTS’s use “stdout-path=&uart5”, but fuji uses “stdout-path=&uart1”. I /do/ see that SCU510 includes a bit related to UART, but it’s for disabling booting from UART1 and UART5. I just care about the console aspect, not booting.
>> The UART can be switched with SCU70[29] on the AST2500, btw.
> If it helps, neither the AST2600's "Boot from UART" feature nor the 
> AST2[456]00's "Debug UART" feature are related to which UART is used as 
> the BMC console by u-boot and/or the kernel - the latter is entirely a 
> software thing.


I don't think we should initialize all 5 UARTs of SoC and let the user define 
all the expected devices on the command. Unless we want to do something like
'macs_mask' ? but at the SoC level. It might be overkill for the need.

My suggestion is have the Aspeed board tell the SoC which uart was selected 
for the console. That can be done with an extra "serial-dev" int property at 
the SoC level, defaults to ASPEED_DEV_UART5, like for the machine. 

The serial init needs a change  : 

    /* UART - attach an 8250 to the IO space as our UART5 */
    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 38400,
                   serial_hd(0), DEVICE_LITTLE_ENDIAN);

but it stays where it is currently, under the SoC.

> The "Debug UART" is a hardware backdoor, a UART-to-AHB bridge 
> implemented by the SoC. It provides a shell environment that allows you 
> to issue transactions directly on the AHB if you perform a magic knock. 
> I have a driver for it implemented here:
> https://github.com/amboar/cve-2019-6260/blob/master/src/debug.c
> SCU70[29] on the AST2500 selects whether this backdoor is exposed on 
> UART1 or UART5.
> The "Boot from UART" feature is implemented in the AST2600 ROM code as 
> a fallback for loading the SPL if fetching it from SPI-NOR or the eMMC 
> fails, or the SPL is incorrectly signed for secure-boot.
> I think Peter is on the right track with this patch?

Yes. nearly. Sorry for the confusion on how to handle this Peter. A machine 
*and* a SoC property should to the trick. 

'amc->serial_dev' is a good idea. You need a similar one under the SoC.

Thanks for the feedback Andrew,


  reply	other threads:[~2021-08-31 13:41 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-27 21:04 [PATCH 0/5] hw/arm/aspeed: Add fuji machine type pdel
2021-08-27 21:04 ` [PATCH 1/5] hw/arm/aspeed: Add get_irq to AspeedSoCClass pdel
2021-08-28  0:30   ` Peter Delevoryas
2021-08-28  8:27   ` Cédric Le Goater
2021-08-27 21:04 ` [PATCH 2/5] hw/arm/aspeed: Select console UART from machine pdel
2021-08-28  8:25   ` Cédric Le Goater
2021-08-28 15:58     ` Peter Delevoryas
2021-08-31  8:15       ` Cédric Le Goater
2021-08-31 13:51         ` Peter Delevoryas
2021-08-31 14:06           ` Cédric Le Goater
2021-08-31 10:39       ` Cédric Le Goater
2021-08-31 11:23         ` Andrew Jeffery
2021-08-31 13:34           ` Cédric Le Goater [this message]
2021-08-31 14:07             ` Peter Delevoryas
2021-08-31 15:57             ` Philippe Mathieu-Daudé
2021-08-31 16:37               ` Cédric Le Goater
2021-08-27 21:04 ` [PATCH 3/5] hw/arm/aspeed: Add fuji machine type pdel
2021-08-28  8:28   ` Cédric Le Goater
2021-08-28 16:00     ` Peter Delevoryas
2021-08-31 16:00       ` Philippe Mathieu-Daudé
2021-08-31 16:38         ` Peter Delevoryas
2021-08-27 21:04 ` [PATCH 4/5] hw/arm/aspeed: Fix AST2600_CLK_SEL3 address pdel
2021-08-28  8:15   ` Cédric Le Goater
2021-08-28 15:13     ` Peter Delevoryas
2021-08-27 21:04 ` [PATCH 5/5] hw/arm/aspeed: Initialize AST2600 clock selection registers pdel
2021-08-28  8:19   ` Cédric Le Goater

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