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[83.53.161.74]) by smtp.gmail.com with ESMTPSA id 70sm1964417wmb.41.2020.09.30.03.13.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Sep 2020 03:13:22 -0700 (PDT) Subject: Re: [PATCH 00/16] hw/mips: Set CPU frequency To: Igor Mammedov References: <20200928171539.788309-1-f4bug@amsat.org> <20200930094048.739faff1@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 30 Sep 2020 12:13:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20200930094048.739faff1@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.199, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , Eduardo Habkost , Paul Burton , qemu-devel@nongnu.org, Wainer dos Santos Moschetta , Aleksandar Markovic , =?UTF-8?Q?Herv=c3=a9_Poussineau?= , Cleber Rosa , Huacai Chen , "Edgar E . Iglesias" , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/30/20 9:40 AM, Igor Mammedov wrote: > On Mon, 28 Sep 2020 19:15:23 +0200 > Philippe Mathieu-Daudé wrote: > >> All the MIPS cores emulated by QEMU provides the Coproc#0 >> 'Count' register which can be used as a free running timer. >> >> Since it's introduction in 2005 this timer uses a fixed >> frequency of 100 MHz (for a CPU freq of 200 MHz). >> While this is not an issue with Linux guests, it makes >> some firmwares behave incorrectly. >> >> The Clock API allow propagating clocks. It is particularly >> useful when hardware dynamicly changes clock frequencies. >> >> To be able to model such MIPS hardware, we need to refactor >> the MIPS hardware code to handle clocks. >> >> This series is organized as follow: >> >> - let all CPU have an input clock, >> - MIPS CPU get an input clock >> - when the clock is changed, CP0 timer is updated >> - set correct CPU frequencies to all boards >> - do not allow MIPS CPU without input clock > > is this clock an integral part of MIPS cpus or it's an external device? CPU cores are clocked via an external clock. This clock can be on the board (from a crystal oscillator to complex PLL) or on-chip for some system-on-chip. In all the (current) QEMU MIPS machines it is external although. Regards, Phil.