From: David Woodhouse <dwmw2@infradead.org>
To: qemu-devel <qemu-devel@nongnu.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, x86 <x86@kernel.org>,
kvm <kvm@vger.kernel.org>
Subject: Re: [PATCH] target/i386: Support up to 32768 CPUs without IRQ remapping
Date: Wed, 07 Oct 2020 13:24:40 +0100 [thread overview]
Message-ID: <aced689373ab94795fe924fd1196ac060e03fec6.camel@infradead.org> (raw)
In-Reply-To: <78097f9218300e63e751e077a0a5ca029b56ba46.camel@infradead.org>
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On Mon, 2020-10-05 at 15:18 +0100, David Woodhouse wrote:
> The IOAPIC has an 'Extended Destination ID' field in its RTE, which maps
> to bits 11-4 of the MSI address. Since those address bits fall within a
> given 4KiB page they were historically non-trivial to use on real hardware.
>
> The Intel IOMMU uses the lowest bit to indicate a remappable format MSI,
> and then the remaining 7 bits are part of the index.
>
> Where the remappable format bit isn't set, we can actually use the other
> seven to allow external (IOAPIC and MSI) interrupts to reach up to 32768
> CPUs instead of just the 255 permitted on bare metal.
>
> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Corresponding kernel patch at
https://patchwork.kernel.org/patch/11820535/
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next prev parent reply other threads:[~2020-10-07 12:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-05 14:18 [PATCH] target/i386: Support up to 32768 CPUs without IRQ remapping David Woodhouse
2020-10-07 12:24 ` David Woodhouse [this message]
2020-10-08 6:56 ` Paolo Bonzini
2020-10-08 7:29 ` David Woodhouse
2020-10-08 7:53 ` Paolo Bonzini
2020-10-19 12:21 ` David Woodhouse
2020-10-19 13:55 ` Paolo Bonzini
2020-10-19 14:55 ` [PATCH] x86/kvm: Reserve KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse
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