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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id t5sm3977382pje.6.2019.12.06.10.51.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 10:51:43 -0800 (PST) Subject: Re: [PATCH v4 35/40] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE To: Peter Maydell References: <20191203022937.1474-1-richard.henderson@linaro.org> <20191203022937.1474-36-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 6 Dec 2019 10:51:41 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/6/19 8:03 AM, Peter Maydell wrote: > So I *think* what the code is doing is: > > When VHE is enabled, the exception level below EL2 is > not EL1, but EL0, and so to identify the entry vector > offset for exceptions targeting EL2 we need to look > at the width of EL0, not of EL1. > > Is that right? Correct. Much better wording, thanks. Will update. r~