* [PATCH V14 1/8] target/mips: Fix PageMask with variable page size
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
@ 2020-10-16 6:51 ` Huacai Chen
2020-10-16 15:15 ` Philippe Mathieu-Daudé
2020-10-16 6:51 ` [PATCH V14 2/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1) Huacai Chen
` (8 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Our current code assumed the target page size is always 4k
when handling PageMask and VPN2, however, variable page size
was just added to mips target and that's no longer true.
Fixes: ee3863b9d414 ("target/mips: Support variable page size")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
target/mips/cp0_helper.c | 36 +++++++++++++++++++++++++++++-------
target/mips/cpu.h | 1 +
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index de64add038..f3478d826b 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -867,13 +867,35 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
{
- uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
- if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
- (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
- mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
- mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
- env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
+ unsigned long mask;
+ int maskbits;
+
+ if (env->insn_flags & ISA_MIPS32R6) {
+ return;
+ }
+ /* Don't care MASKX as we don't support 1KB page */
+ mask = extract32((uint32_t)arg1, CP0PM_MASK, 16);
+ maskbits = find_first_zero_bit(&mask, 32);
+
+ /* Ensure no more set bit after first zero */
+ if (mask >> maskbits) {
+ goto invalid;
+ }
+ /* We don't support VTLB entry smaller than target page */
+ if ((maskbits + 12) < TARGET_PAGE_BITS) {
+ goto invalid;
}
+ env->CP0_PageMask = mask << CP0PM_MASK;
+
+ return;
+
+invalid:
+ /*
+ * When invalid, ensure the value is bigger than or equal to
+ * the minimal but smaller than or equal to the maxium.
+ */
+ maskbits = MIN(16, MAX(maskbits, TARGET_PAGE_BITS - 12));
+ env->CP0_PageMask = ((1 << (16 + 1)) - 1) << CP0PM_MASK;
}
void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
@@ -1104,7 +1126,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
target_ulong old, val, mask;
- mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
+ mask = ~((1 << 14) - 1) | env->CP0_EntryHi_ASID_mask;
if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
mask |= 1 << CP0EnHi_EHINV;
}
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7cf7f5239f..9c8bb23807 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -618,6 +618,7 @@ struct CPUMIPSState {
* CP0 Register 5
*/
int32_t CP0_PageMask;
+#define CP0PM_MASK 13
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
#define CP0PG_RIE 31
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH V14 1/8] target/mips: Fix PageMask with variable page size
2020-10-16 6:51 ` [PATCH V14 1/8] target/mips: Fix PageMask with variable page size Huacai Chen
@ 2020-10-16 15:15 ` Philippe Mathieu-Daudé
2020-10-20 1:38 ` Huacai Chen
0 siblings, 1 reply; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-16 15:15 UTC (permalink / raw)
To: Huacai Chen, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
On 10/16/20 8:51 AM, Huacai Chen wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> Our current code assumed the target page size is always 4k
> when handling PageMask and VPN2, however, variable page size
> was just added to mips target and that's no longer true.
>
> Fixes: ee3863b9d414 ("target/mips: Support variable page size")
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> target/mips/cp0_helper.c | 36 +++++++++++++++++++++++++++++-------
> target/mips/cpu.h | 1 +
> 2 files changed, 30 insertions(+), 7 deletions(-)
>
> diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
> index de64add038..f3478d826b 100644
> --- a/target/mips/cp0_helper.c
> +++ b/target/mips/cp0_helper.c
> @@ -867,13 +867,35 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
>
> void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
> {
> - uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
> - if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
> - (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
> - mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
> - mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
> - env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
> + unsigned long mask;
> + int maskbits;
> +
> + if (env->insn_flags & ISA_MIPS32R6) {
> + return;
> + }
> + /* Don't care MASKX as we don't support 1KB page */
> + mask = extract32((uint32_t)arg1, CP0PM_MASK, 16);
> + maskbits = find_first_zero_bit(&mask, 32);
> +
> + /* Ensure no more set bit after first zero */
> + if (mask >> maskbits) {
> + goto invalid;
> + }
> + /* We don't support VTLB entry smaller than target page */
> + if ((maskbits + 12) < TARGET_PAGE_BITS) {
> + goto invalid;
> }
> + env->CP0_PageMask = mask << CP0PM_MASK;
> +
> + return;
> +
> +invalid:
> + /*
> + * When invalid, ensure the value is bigger than or equal to
> + * the minimal but smaller than or equal to the maxium.
> + */
> + maskbits = MIN(16, MAX(maskbits, TARGET_PAGE_BITS - 12));
> + env->CP0_PageMask = ((1 << (16 + 1)) - 1) << CP0PM_MASK;
> }
>
> void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
> @@ -1104,7 +1126,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
> void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
> {
> target_ulong old, val, mask;
> - mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
> + mask = ~((1 << 14) - 1) | env->CP0_EntryHi_ASID_mask;
> if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
> mask |= 1 << CP0EnHi_EHINV;
> }
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 7cf7f5239f..9c8bb23807 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -618,6 +618,7 @@ struct CPUMIPSState {
> * CP0 Register 5
> */
> int32_t CP0_PageMask;
> +#define CP0PM_MASK 13
> int32_t CP0_PageGrain_rw_bitmask;
> int32_t CP0_PageGrain;
> #define CP0PG_RIE 31
>
Malta test failing:
[ 0.000000] Linux version 4.5.0-2-4kc-malta
(debian-kernel@lists.debian.org) (gcc version 5.3.1 20160519 (Debian
5.3.1-20) ) #1 Debian 4.5.5-1 (2016-05-29)
[ 0.000000] earlycon: Early serial console at I/O port 0x3f8 (options
'38400n8')
[ 0.000000] bootconsole [uart0] enabled
[ 0.000000] CPU0 revision is: 00019300 (MIPS 24Kc)
[ 0.000000] FPU revision is: 00739300
[ 0.000000] MIPS: machine is mti,malta
[...]
Freeing unused kernel memory: 412K (80979000 - 809e0000)
do_page_fault(): sending SIGSEGV to mount for invalid write access to
0018a000
epc = 77848a54 in libc-2.27.so[7782f000+177000]
ra = 779d0618 in ld-2.27.so[779bf000+24000]
do_page_fault(): sending SIGSEGV to ln for invalid write access to 0018a000
epc = 778d4a54 in libc-2.27.so[778bb000+177000]
ra = 77a5c618 in ld-2.27.so[77a4b000+24000]
do_page_fault(): sending SIGSEGV to S01logging for invalid write access
to 0018a000
epc = 77d08a54 in libc-2.27.so[77cef000+177000]
ra = 77e90618 in ld-2.27.so[77e7f000+24000]
do_page_fault(): sending SIGSEGV to S20urandom for invalid write access
to 0018a000
epc = 76ee4a54 in libc-2.27.so[76ecb000+177000]
ra = 7706c618 in ld-2.27.so[7705b000+24000]
do_page_fault(): sending SIGSEGV to ifup for invalid write access to
0018a000
epc = 77974a54 in libc-2.27.so[7795b000+177000]
ra = 77afc618 in ld-2.27.so[77aeb000+24000]
do_page_fault(): sending SIGSEGV to awk for invalid read access from
00000000
epc = 00000000 in busybox[400000+d8000]
ra = 77248110 in libc-2.27.so[770fb000+177000]
do_page_fault(): sending SIGSEGV to cat for invalid write access to 0018a000
epc = 77484a54 in libc-2.27.so[7746b000+177000]
ra = 7760c618 in ld-2.27.so[775fb000+24000]
do_page_fault(): sending SIGSEGV to run.sh for invalid write access to
0018a000
epc = 76e88a54 in libc-2.27.so[76e6f000+177000]
ra = 77010618 in ld-2.27.so[76fff000+24000]
qemu-system-mips: terminating on signal 2
Please run the QEMU tests.
The easiest way is to push your series on GitLab.
Regards,
Phil.
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH V14 1/8] target/mips: Fix PageMask with variable page size
2020-10-16 15:15 ` Philippe Mathieu-Daudé
@ 2020-10-20 1:38 ` Huacai Chen
0 siblings, 0 replies; 20+ messages in thread
From: Huacai Chen @ 2020-10-20 1:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Huacai Chen, Aleksandar Markovic, Aleksandar Rikalo,
Aurelien Jarno, QEMU Developers
Hi, Philippe,
On Fri, Oct 16, 2020 at 11:15 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/16/20 8:51 AM, Huacai Chen wrote:
> > From: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >
> > Our current code assumed the target page size is always 4k
> > when handling PageMask and VPN2, however, variable page size
> > was just added to mips target and that's no longer true.
> >
> > Fixes: ee3863b9d414 ("target/mips: Support variable page size")
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > ---
> > target/mips/cp0_helper.c | 36 +++++++++++++++++++++++++++++-------
> > target/mips/cpu.h | 1 +
> > 2 files changed, 30 insertions(+), 7 deletions(-)
> >
> > diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
> > index de64add038..f3478d826b 100644
> > --- a/target/mips/cp0_helper.c
> > +++ b/target/mips/cp0_helper.c
> > @@ -867,13 +867,35 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
> >
> > void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
> > {
> > - uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
> > - if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
> > - (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
> > - mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
> > - mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
> > - env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
> > + unsigned long mask;
> > + int maskbits;
> > +
> > + if (env->insn_flags & ISA_MIPS32R6) {
> > + return;
> > + }
> > + /* Don't care MASKX as we don't support 1KB page */
> > + mask = extract32((uint32_t)arg1, CP0PM_MASK, 16);
> > + maskbits = find_first_zero_bit(&mask, 32);
> > +
> > + /* Ensure no more set bit after first zero */
> > + if (mask >> maskbits) {
> > + goto invalid;
> > + }
> > + /* We don't support VTLB entry smaller than target page */
> > + if ((maskbits + 12) < TARGET_PAGE_BITS) {
> > + goto invalid;
> > }
> > + env->CP0_PageMask = mask << CP0PM_MASK;
> > +
> > + return;
> > +
> > +invalid:
> > + /*
> > + * When invalid, ensure the value is bigger than or equal to
> > + * the minimal but smaller than or equal to the maxium.
> > + */
> > + maskbits = MIN(16, MAX(maskbits, TARGET_PAGE_BITS - 12));
> > + env->CP0_PageMask = ((1 << (16 + 1)) - 1) << CP0PM_MASK;
> > }
> >
> > void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
> > @@ -1104,7 +1126,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
> > void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
> > {
> > target_ulong old, val, mask;
> > - mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
> > + mask = ~((1 << 14) - 1) | env->CP0_EntryHi_ASID_mask;
> > if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
> > mask |= 1 << CP0EnHi_EHINV;
> > }
> > diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> > index 7cf7f5239f..9c8bb23807 100644
> > --- a/target/mips/cpu.h
> > +++ b/target/mips/cpu.h
> > @@ -618,6 +618,7 @@ struct CPUMIPSState {
> > * CP0 Register 5
> > */
> > int32_t CP0_PageMask;
> > +#define CP0PM_MASK 13
> > int32_t CP0_PageGrain_rw_bitmask;
> > int32_t CP0_PageGrain;
> > #define CP0PG_RIE 31
> >
>
> Malta test failing:
>
> [ 0.000000] Linux version 4.5.0-2-4kc-malta
> (debian-kernel@lists.debian.org) (gcc version 5.3.1 20160519 (Debian
> 5.3.1-20) ) #1 Debian 4.5.5-1 (2016-05-29)
> [ 0.000000] earlycon: Early serial console at I/O port 0x3f8 (options
> '38400n8')
> [ 0.000000] bootconsole [uart0] enabled
> [ 0.000000] CPU0 revision is: 00019300 (MIPS 24Kc)
> [ 0.000000] FPU revision is: 00739300
> [ 0.000000] MIPS: machine is mti,malta
> [...]
> Freeing unused kernel memory: 412K (80979000 - 809e0000)
> do_page_fault(): sending SIGSEGV to mount for invalid write access to
> 0018a000
> epc = 77848a54 in libc-2.27.so[7782f000+177000]
> ra = 779d0618 in ld-2.27.so[779bf000+24000]
> do_page_fault(): sending SIGSEGV to ln for invalid write access to 0018a000
> epc = 778d4a54 in libc-2.27.so[778bb000+177000]
> ra = 77a5c618 in ld-2.27.so[77a4b000+24000]
> do_page_fault(): sending SIGSEGV to S01logging for invalid write access
> to 0018a000
> epc = 77d08a54 in libc-2.27.so[77cef000+177000]
> ra = 77e90618 in ld-2.27.so[77e7f000+24000]
> do_page_fault(): sending SIGSEGV to S20urandom for invalid write access
> to 0018a000
> epc = 76ee4a54 in libc-2.27.so[76ecb000+177000]
> ra = 7706c618 in ld-2.27.so[7705b000+24000]
> do_page_fault(): sending SIGSEGV to ifup for invalid write access to
> 0018a000
> epc = 77974a54 in libc-2.27.so[7795b000+177000]
> ra = 77afc618 in ld-2.27.so[77aeb000+24000]
> do_page_fault(): sending SIGSEGV to awk for invalid read access from
> 00000000
> epc = 00000000 in busybox[400000+d8000]
> ra = 77248110 in libc-2.27.so[770fb000+177000]
> do_page_fault(): sending SIGSEGV to cat for invalid write access to 0018a000
> epc = 77484a54 in libc-2.27.so[7746b000+177000]
> ra = 7760c618 in ld-2.27.so[775fb000+24000]
> do_page_fault(): sending SIGSEGV to run.sh for invalid write access to
> 0018a000
> epc = 76e88a54 in libc-2.27.so[76e6f000+177000]
> ra = 77010618 in ld-2.27.so[76fff000+24000]
> qemu-system-mips: terminating on signal 2
>
> Please run the QEMU tests.
OK, we are investigating.
>
> The easiest way is to push your series on GitLab.
>
> Regards,
>
> Phil.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH V14 2/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
2020-10-16 6:51 ` [PATCH V14 1/8] target/mips: Fix PageMask with variable page size Huacai Chen
@ 2020-10-16 6:51 ` Huacai Chen
2020-10-16 15:12 ` Philippe Mathieu-Daudé
2020-10-16 6:51 ` [PATCH V14 3/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 2) Huacai Chen
` (7 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FPR
gssqc1: store 16 bytes from FPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
target/mips/translate.c | 86 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf7289..20a7f36c7c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -460,6 +460,17 @@ enum {
R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
};
+/* Loongson EXT load/store quad word opcodes */
+#define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020))
+enum {
+ OPC_GSLQ = 0x0020 | OPC_LWC2,
+ OPC_GSLQC1 = 0x8020 | OPC_LWC2,
+ OPC_GSSHFL = OPC_LWC2,
+ OPC_GSSQ = 0x0020 | OPC_SWC2,
+ OPC_GSSQC1 = 0x8020 | OPC_SWC2,
+ OPC_GSSHFS = OPC_SWC2,
+};
+
/* BSHFL opcodes */
#define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -5910,6 +5921,79 @@ no_rd:
tcg_temp_free_i64(t1);
}
+static void gen_loongson_lswc2(DisasContext *ctx, int rt,
+ int rs, int rd)
+{
+ TCGv t0, t1, t2;
+ TCGv_i32 fp0;
+#if defined(TARGET_MIPS64)
+ int lsq_rt1 = ctx->opcode & 0x1f;
+ int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4;
+#endif
+
+ t0 = tcg_temp_new();
+
+ switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) {
+#if defined(TARGET_MIPS64)
+ case OPC_GSLQ:
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t1, rt);
+ gen_store_gpr(t0, lsq_rt1);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSLQC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_store_fpr64(ctx, t1, rt);
+ gen_store_fpr64(ctx, t0, lsq_rt1);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSQ:
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ gen_load_gpr(t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ gen_load_gpr(t1, lsq_rt1);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSQC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ gen_load_fpr64(ctx, t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ gen_load_fpr64(ctx, t1, lsq_rt1);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+#endif
+ default:
+ MIPS_INVAL("loongson_gslsq");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ tcg_temp_free(t0);
+}
+
/* Traps */
static void gen_trap(DisasContext *ctx, uint32_t opc,
int rs, int rt, int16_t imm)
@@ -30774,6 +30858,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_BC, OPC_BALC */
gen_compute_compact_branch(ctx, op, 0, 0,
sextract32(ctx->opcode << 2, 0, 28));
+ } else if (ctx->insn_flags & ASE_LEXT) {
+ gen_loongson_lswc2(ctx, rt, rs, rd);
} else {
/* OPC_LWC2, OPC_SWC2 */
/* COP2: Not implemented. */
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH V14 2/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
2020-10-16 6:51 ` [PATCH V14 2/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1) Huacai Chen
@ 2020-10-16 15:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-16 15:12 UTC (permalink / raw)
To: Huacai Chen, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
On 10/16/20 8:51 AM, Huacai Chen wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
> as "load/store quad word" and "shifted load/store" groups of
> instructions.
>
> This patch add implementation of these instructions:
> gslq: load 16 bytes to GPR
> gssq: store 16 bytes from GPR
> gslqc1: load 16 bytes to FPR
> gssqc1: store 16 bytes from FPR
>
> Details of Loongson-EXT is here:
> https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> target/mips/translate.c | 86 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
Build failure:
target/mips/translate.c: In function ‘gen_loongson_lswc2’:
target/mips/translate.c:5928:14: error: unused variable ‘fp0’
[-Werror=unused-variable]
5928 | TCGv_i32 fp0;
| ^~~
target/mips/translate.c:5927:18: error: unused variable ‘t2’
[-Werror=unused-variable]
5927 | TCGv t0, t1, t2;
| ^~
target/mips/translate.c:5927:14: error: unused variable ‘t1’
[-Werror=unused-variable]
5927 | TCGv t0, t1, t2;
| ^~
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH V14 3/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
2020-10-16 6:51 ` [PATCH V14 1/8] target/mips: Fix PageMask with variable page size Huacai Chen
2020-10-16 6:51 ` [PATCH V14 2/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1) Huacai Chen
@ 2020-10-16 6:51 ` Huacai Chen
2020-10-16 6:51 ` [PATCH V14 4/8] target/mips: Add loongson-ext lsdc2 group of instructions Huacai Chen
` (6 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslwlc1: similar to lwl but RT is FPR instead of GPR
gslwrc1: similar to lwr but RT is FPR instead of GPR
gsldlc1: similar to ldl but RT is FPR instead of GPR
gsldrc1: similar to ldr but RT is FPR instead of GPR
gsswlc1: similar to swl but RT is FPR instead of GPR
gsswrc1: similar to swr but RT is FPR instead of GPR
gssdlc1: similar to sdl but RT is FPR instead of GPR
gssdrc1: similar to sdr but RT is FPR instead of GPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
target/mips/translate.c | 178 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 20a7f36c7c..25321d3c17 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -471,6 +471,19 @@ enum {
OPC_GSSHFS = OPC_SWC2,
};
+/* Loongson EXT shifted load/store opcodes */
+#define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f))
+enum {
+ OPC_GSLWLC1 = 0x4 | OPC_GSSHFL,
+ OPC_GSLWRC1 = 0x5 | OPC_GSSHFL,
+ OPC_GSLDLC1 = 0x6 | OPC_GSSHFL,
+ OPC_GSLDRC1 = 0x7 | OPC_GSSHFL,
+ OPC_GSSWLC1 = 0x4 | OPC_GSSHFS,
+ OPC_GSSWRC1 = 0x5 | OPC_GSSHFS,
+ OPC_GSSDLC1 = 0x6 | OPC_GSSHFS,
+ OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
+};
+
/* BSHFL opcodes */
#define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -5930,6 +5943,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
int lsq_rt1 = ctx->opcode & 0x1f;
int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4;
#endif
+ int shf_offset = sextract32(ctx->opcode, 6, 8);
t0 = tcg_temp_new();
@@ -5986,6 +6000,170 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
tcg_temp_free(t1);
break;
#endif
+ case OPC_GSSHFL:
+ switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
+ case OPC_GSLWLC1:
+ check_cp1_enabled(ctx);
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ t1 = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ tcg_gen_andi_tl(t1, t0, 3);
+#ifndef TARGET_WORDS_BIGENDIAN
+ tcg_gen_xori_tl(t1, t1, 3);
+#endif
+ tcg_gen_shli_tl(t1, t1, 3);
+ tcg_gen_andi_tl(t0, t0, ~3);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_shl_tl(t0, t0, t1);
+ t2 = tcg_const_tl(-1);
+ tcg_gen_shl_tl(t2, t2, t1);
+ fp0 = tcg_temp_new_i32();
+ gen_load_fpr32(ctx, fp0, rt);
+ tcg_gen_ext_i32_tl(t1, fp0);
+ tcg_gen_andc_tl(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_temp_free(t1);
+#if defined(TARGET_MIPS64)
+ tcg_gen_extrl_i64_i32(fp0, t0);
+#else
+ tcg_gen_ext32s_tl(fp0, t0);
+#endif
+ gen_store_fpr32(ctx, fp0, rt);
+ tcg_temp_free_i32(fp0);
+ break;
+ case OPC_GSLWRC1:
+ check_cp1_enabled(ctx);
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ t1 = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ tcg_gen_andi_tl(t1, t0, 3);
+#ifdef TARGET_WORDS_BIGENDIAN
+ tcg_gen_xori_tl(t1, t1, 3);
+#endif
+ tcg_gen_shli_tl(t1, t1, 3);
+ tcg_gen_andi_tl(t0, t0, ~3);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_shr_tl(t0, t0, t1);
+ tcg_gen_xori_tl(t1, t1, 31);
+ t2 = tcg_const_tl(0xfffffffeull);
+ tcg_gen_shl_tl(t2, t2, t1);
+ fp0 = tcg_temp_new_i32();
+ gen_load_fpr32(ctx, fp0, rt);
+ tcg_gen_ext_i32_tl(t1, fp0);
+ tcg_gen_and_tl(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_temp_free(t1);
+#if defined(TARGET_MIPS64)
+ tcg_gen_extrl_i64_i32(fp0, t0);
+#else
+ tcg_gen_ext32s_tl(fp0, t0);
+#endif
+ gen_store_fpr32(ctx, fp0, rt);
+ tcg_temp_free_i32(fp0);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_GSLDLC1:
+ check_cp1_enabled(ctx);
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ t1 = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ tcg_gen_andi_tl(t1, t0, 7);
+#ifndef TARGET_WORDS_BIGENDIAN
+ tcg_gen_xori_tl(t1, t1, 7);
+#endif
+ tcg_gen_shli_tl(t1, t1, 3);
+ tcg_gen_andi_tl(t0, t0, ~7);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
+ tcg_gen_shl_tl(t0, t0, t1);
+ t2 = tcg_const_tl(-1);
+ tcg_gen_shl_tl(t2, t2, t1);
+ gen_load_fpr64(ctx, t1, rt);
+ tcg_gen_andc_tl(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_temp_free(t1);
+ gen_store_fpr64(ctx, t0, rt);
+ break;
+ case OPC_GSLDRC1:
+ check_cp1_enabled(ctx);
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ t1 = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
+ tcg_gen_andi_tl(t1, t0, 7);
+#ifdef TARGET_WORDS_BIGENDIAN
+ tcg_gen_xori_tl(t1, t1, 7);
+#endif
+ tcg_gen_shli_tl(t1, t1, 3);
+ tcg_gen_andi_tl(t0, t0, ~7);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
+ tcg_gen_shr_tl(t0, t0, t1);
+ tcg_gen_xori_tl(t1, t1, 63);
+ t2 = tcg_const_tl(0xfffffffffffffffeull);
+ tcg_gen_shl_tl(t2, t2, t1);
+ gen_load_fpr64(ctx, t1, rt);
+ tcg_gen_and_tl(t1, t1, t2);
+ tcg_temp_free(t2);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_temp_free(t1);
+ gen_store_fpr64(ctx, t0, rt);
+ break;
+#endif
+ default:
+ MIPS_INVAL("loongson_gsshfl");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case OPC_GSSHFS:
+ switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
+ case OPC_GSSWLC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ fp0 = tcg_temp_new_i32();
+ gen_load_fpr32(ctx, fp0, rt);
+ tcg_gen_ext_i32_tl(t1, fp0);
+ gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSWRC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ fp0 = tcg_temp_new_i32();
+ gen_load_fpr32(ctx, fp0, rt);
+ tcg_gen_ext_i32_tl(t1, fp0);
+ gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free(t1);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_GSSDLC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ gen_load_fpr64(ctx, t1, rt);
+ gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSDRC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, shf_offset);
+ gen_load_fpr64(ctx, t1, rt);
+ gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
+ tcg_temp_free(t1);
+ break;
+#endif
+ default:
+ MIPS_INVAL("loongson_gsshfs");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
default:
MIPS_INVAL("loongson_gslsq");
generate_exception_end(ctx, EXCP_RI);
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH V14 4/8] target/mips: Add loongson-ext lsdc2 group of instructions
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
` (2 preceding siblings ...)
2020-10-16 6:51 ` [PATCH V14 3/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 2) Huacai Chen
@ 2020-10-16 6:51 ` Huacai Chen
2020-10-16 14:12 ` Philippe Mathieu-Daudé
2020-10-16 6:51 ` [PATCH V14 5/8] hw/mips: Implement fw_cfg_arch_key_name() Huacai Chen
` (5 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.
This patch add implementation of these instructions:
gslbx: load 1 bytes to GPR
gslhx: load 2 bytes to GPR
gslwx: load 4 bytes to GPR
gsldx: load 8 bytes to GPR
gslwxc1: load 4 bytes to FPR
gsldxc1: load 8 bytes to FPR
gssbx: store 1 bytes from GPR
gsshx: store 2 bytes from GPR
gsswx: store 4 bytes from GPR
gssdx: store 8 bytes from GPR
gsswxc1: store 4 bytes from FPR
gssdxc1: store 8 bytes from FPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
target/mips/translate.c | 179 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 179 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 25321d3c17..b2ce323e39 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -484,6 +484,24 @@ enum {
OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
};
+/* Loongson EXT LDC2/SDC2 opcodes */
+#define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7))
+
+enum {
+ OPC_GSLBX = 0x0 | OPC_LDC2,
+ OPC_GSLHX = 0x1 | OPC_LDC2,
+ OPC_GSLWX = 0x2 | OPC_LDC2,
+ OPC_GSLDX = 0x3 | OPC_LDC2,
+ OPC_GSLWXC1 = 0x6 | OPC_LDC2,
+ OPC_GSLDXC1 = 0x7 | OPC_LDC2,
+ OPC_GSSBX = 0x0 | OPC_SDC2,
+ OPC_GSSHX = 0x1 | OPC_SDC2,
+ OPC_GSSWX = 0x2 | OPC_SDC2,
+ OPC_GSSDX = 0x3 | OPC_SDC2,
+ OPC_GSSWXC1 = 0x6 | OPC_SDC2,
+ OPC_GSSDXC1 = 0x7 | OPC_SDC2,
+};
+
/* BSHFL opcodes */
#define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -6172,6 +6190,165 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
tcg_temp_free(t0);
}
+/* Loongson EXT LDC2/SDC2 */
+static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
+ int rs, int rd)
+{
+ int offset = sextract32(ctx->opcode, 3, 8);
+ uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
+ TCGv t0, t1;
+ TCGv_i32 fp0;
+
+ /* Pre-conditions */
+ switch (opc) {
+ case OPC_GSLBX:
+ case OPC_GSLHX:
+ case OPC_GSLWX:
+ case OPC_GSLDX:
+ /* prefetch, implement as NOP */
+ if (rt == 0) {
+ return;
+ }
+ break;
+ case OPC_GSSBX:
+ case OPC_GSSHX:
+ case OPC_GSSWX:
+ case OPC_GSSDX:
+ break;
+ case OPC_GSLWXC1:
+#if defined(TARGET_MIPS64)
+ case OPC_GSLDXC1:
+#endif
+ check_cp1_enabled(ctx);
+ /* prefetch, implement as NOP */
+ if (rt == 0) {
+ return;
+ }
+ break;
+ case OPC_GSSWXC1:
+#if defined(TARGET_MIPS64)
+ case OPC_GSSDXC1:
+#endif
+ check_cp1_enabled(ctx);
+ break;
+ default:
+ MIPS_INVAL("loongson_lsdc2");
+ generate_exception_end(ctx, EXCP_RI);
+ return;
+ break;
+ }
+
+ t0 = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, t0, rs, offset);
+ gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+
+ switch (opc) {
+ case OPC_GSLBX:
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
+ gen_store_gpr(t0, rt);
+ break;
+ case OPC_GSLHX:
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t0, rt);
+ break;
+ case OPC_GSLWX:
+ gen_base_offset_addr(ctx, t0, rs, offset);
+ if (rd) {
+ gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+ }
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t0, rt);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_GSLDX:
+ gen_base_offset_addr(ctx, t0, rs, offset);
+ if (rd) {
+ gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+ }
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t0, rt);
+ break;
+#endif
+ case OPC_GSLWXC1:
+ check_cp1_enabled(ctx);
+ gen_base_offset_addr(ctx, t0, rs, offset);
+ if (rd) {
+ gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+ }
+ fp0 = tcg_temp_new_i32();
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
+ gen_store_fpr32(ctx, fp0, rt);
+ tcg_temp_free_i32(fp0);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_GSLDXC1:
+ check_cp1_enabled(ctx);
+ gen_base_offset_addr(ctx, t0, rs, offset);
+ if (rd) {
+ gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+ }
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_store_fpr64(ctx, t0, rt);
+ break;
+#endif
+ case OPC_GSSBX:
+ t1 = tcg_temp_new();
+ gen_load_gpr(t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSHX:
+ t1 = tcg_temp_new();
+ gen_load_gpr(t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSWX:
+ t1 = tcg_temp_new();
+ gen_load_gpr(t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_GSSDX:
+ t1 = tcg_temp_new();
+ gen_load_gpr(t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+#endif
+ case OPC_GSSWXC1:
+ fp0 = tcg_temp_new_i32();
+ gen_load_fpr32(ctx, fp0, rt);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free_i32(fp0);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_GSSDXC1:
+ t1 = tcg_temp_new();
+ gen_load_fpr64(ctx, t1, rt);
+ tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ tcg_temp_free(t0);
+}
+
/* Traps */
static void gen_trap(DisasContext *ctx, uint32_t opc,
int rs, int rt, int16_t imm)
@@ -31055,6 +31232,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_JIC, OPC_JIALC */
gen_compute_compact_branch(ctx, op, 0, rt, imm);
}
+ } else if (ctx->insn_flags & ASE_LEXT) {
+ gen_loongson_lsdc2(ctx, rt, rs, rd);
} else {
/* OPC_LWC2, OPC_SWC2 */
/* COP2: Not implemented. */
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH V14 4/8] target/mips: Add loongson-ext lsdc2 group of instructions
2020-10-16 6:51 ` [PATCH V14 4/8] target/mips: Add loongson-ext lsdc2 group of instructions Huacai Chen
@ 2020-10-16 14:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-16 14:12 UTC (permalink / raw)
To: Huacai Chen, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
On 10/16/20 8:51 AM, Huacai Chen wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
> group of instructions by loongson-ext ASE.
>
> This patch add implementation of these instructions:
> gslbx: load 1 bytes to GPR
> gslhx: load 2 bytes to GPR
> gslwx: load 4 bytes to GPR
> gsldx: load 8 bytes to GPR
> gslwxc1: load 4 bytes to FPR
> gsldxc1: load 8 bytes to FPR
> gssbx: store 1 bytes from GPR
> gsshx: store 2 bytes from GPR
> gsswx: store 4 bytes from GPR
> gssdx: store 8 bytes from GPR
> gsswxc1: store 4 bytes from FPR
> gssdxc1: store 8 bytes from FPR
>
> Details of Loongson-EXT is here:
> https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> target/mips/translate.c | 179 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 179 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH V14 5/8] hw/mips: Implement fw_cfg_arch_key_name()
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
` (3 preceding siblings ...)
2020-10-16 6:51 ` [PATCH V14 4/8] target/mips: Add loongson-ext lsdc2 group of instructions Huacai Chen
@ 2020-10-16 6:51 ` Huacai Chen
2020-10-16 6:51 ` [PATCH V14 6/8] hw/mips: Add Loongson-3 boot parameter helpers Huacai Chen
` (4 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
Implement fw_cfg_arch_key_name(), which returns the name of a
mips-specific key.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
hw/mips/fw_cfg.c | 35 +++++++++++++++++++++++++++++++++++
hw/mips/fw_cfg.h | 19 +++++++++++++++++++
hw/mips/meson.build | 2 +-
3 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 hw/mips/fw_cfg.c
create mode 100644 hw/mips/fw_cfg.h
diff --git a/hw/mips/fw_cfg.c b/hw/mips/fw_cfg.c
new file mode 100644
index 0000000000..67c4a74f4b
--- /dev/null
+++ b/hw/mips/fw_cfg.c
@@ -0,0 +1,35 @@
+/*
+ * QEMU fw_cfg helpers (MIPS specific)
+ *
+ * Copyright (c) 2020 Lemote, Inc.
+ *
+ * Author:
+ * Huacai Chen (chenhc@lemote.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/mips/fw_cfg.h"
+#include "hw/nvram/fw_cfg.h"
+
+const char *fw_cfg_arch_key_name(uint16_t key)
+{
+ static const struct {
+ uint16_t key;
+ const char *name;
+ } fw_cfg_arch_wellknown_keys[] = {
+ {FW_CFG_MACHINE_VERSION, "machine_version"},
+ {FW_CFG_CPU_FREQ, "cpu_frequency"},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
+ if (fw_cfg_arch_wellknown_keys[i].key == key) {
+ return fw_cfg_arch_wellknown_keys[i].name;
+ }
+ }
+ return NULL;
+}
diff --git a/hw/mips/fw_cfg.h b/hw/mips/fw_cfg.h
new file mode 100644
index 0000000000..e317d5b9a3
--- /dev/null
+++ b/hw/mips/fw_cfg.h
@@ -0,0 +1,19 @@
+/*
+ * QEMU fw_cfg helpers (MIPS specific)
+ *
+ * Copyright (c) 2020 Huacai Chen
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef HW_MIPS_FW_CFG_H
+#define HW_MIPS_FW_CFG_H
+
+#include "hw/boards.h"
+#include "hw/nvram/fw_cfg.h"
+
+/* Data for BIOS to identify machine */
+#define FW_CFG_MACHINE_VERSION (FW_CFG_ARCH_LOCAL + 0)
+#define FW_CFG_CPU_FREQ (FW_CFG_ARCH_LOCAL + 1)
+
+#endif
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index 46294b7382..c98391ce99 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,5 +1,5 @@
mips_ss = ss.source_set()
-mips_ss.add(files('addr.c', 'mips_int.c'))
+mips_ss.add(files('addr.c', 'mips_int.c', 'fw_cfg.c'))
mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH V14 6/8] hw/mips: Add Loongson-3 boot parameter helpers
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
` (4 preceding siblings ...)
2020-10-16 6:51 ` [PATCH V14 5/8] hw/mips: Implement fw_cfg_arch_key_name() Huacai Chen
@ 2020-10-16 6:51 ` Huacai Chen
2020-10-16 14:24 ` Philippe Mathieu-Daudé
2020-10-16 6:51 ` [PATCH V14 7/8] hw/mips: Add Loongson-3 machine support Huacai Chen
` (3 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
hw/mips/loongson3_bootp.c | 162 +++++++++++++++++++++++++++
hw/mips/loongson3_bootp.h | 225 ++++++++++++++++++++++++++++++++++++++
hw/mips/meson.build | 1 +
3 files changed, 388 insertions(+)
create mode 100644 hw/mips/loongson3_bootp.c
create mode 100644 hw/mips/loongson3_bootp.h
diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
new file mode 100644
index 0000000000..eab6f51a01
--- /dev/null
+++ b/hw/mips/loongson3_bootp.c
@@ -0,0 +1,162 @@
+/*
+ * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) helpers
+ *
+ * Copyright (c) 2017-2020 Huacai Chen (chenhc@lemote.com)
+ * Copyright (c) 2017-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "cpu.h"
+#include "hw/boards.h"
+#include "hw/mips/loongson3_bootp.h"
+
+static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq)
+{
+ struct efi_cpuinfo_loongson *c = g_cpuinfo;
+
+ stl_le_p(&c->cputype, Loongson_3A);
+ stl_le_p(&c->processor_id, MIPS_CPU(first_cpu)->env.CP0_PRid);
+ if (cpu_freq > UINT_MAX) {
+ stl_le_p(&c->cpu_clock_freq, UINT_MAX);
+ } else {
+ stl_le_p(&c->cpu_clock_freq, cpu_freq);
+ }
+
+ stw_le_p(&c->cpu_startup_core_id, 0);
+ stl_le_p(&c->nr_cpus, current_machine->smp.cpus);
+ stl_le_p(&c->total_node, (current_machine->smp.cpus + 3) / 4);
+
+ return c;
+}
+
+static struct efi_memory_map_loongson *init_memory_map(void *g_map, uint64_t ram_size)
+{
+ struct efi_memory_map_loongson *emap = g_map;
+
+ stl_le_p(&emap->nr_map, 2);
+ stl_le_p(&emap->mem_freq, 300000000);
+
+ stl_le_p(&emap->map[0].node_id, 0);
+ stl_le_p(&emap->map[0].mem_type, 1);
+ stq_le_p(&emap->map[0].mem_start, 0x0);
+ stl_le_p(&emap->map[0].mem_size, 240);
+
+ stl_le_p(&emap->map[1].node_id, 0);
+ stl_le_p(&emap->map[1].mem_type, 2);
+ stq_le_p(&emap->map[1].mem_start, 0x90000000);
+ stl_le_p(&emap->map[1].mem_size, (ram_size / MiB) - 256);
+
+ return emap;
+}
+
+static struct system_loongson *init_system_loongson(void *g_system)
+{
+ struct system_loongson *s = g_system;
+
+ stl_le_p(&s->ccnuma_smp, 0);
+ stl_le_p(&s->sing_double_channel, 1);
+ stl_le_p(&s->nr_uarts, 1);
+ stl_le_p(&s->uarts[0].iotype, 2);
+ stl_le_p(&s->uarts[0].int_offset, 2);
+ stl_le_p(&s->uarts[0].uartclk, 25000000); /* Random value */
+ stq_le_p(&s->uarts[0].uart_base, virt_memmap[VIRT_UART].base);
+
+ return s;
+}
+
+static struct irq_source_routing_table *init_irq_source(void *g_irq_source)
+{
+ struct irq_source_routing_table *irq_info = g_irq_source;
+
+ stl_le_p(&irq_info->node_id, 0);
+ stl_le_p(&irq_info->PIC_type, 0);
+ stw_le_p(&irq_info->dma_mask_bits, 64);
+ stq_le_p(&irq_info->pci_mem_start_addr, virt_memmap[VIRT_PCIE_MMIO].base);
+ stq_le_p(&irq_info->pci_mem_end_addr, virt_memmap[VIRT_PCIE_MMIO].base +
+ virt_memmap[VIRT_PCIE_MMIO].size - 1);
+ stq_le_p(&irq_info->pci_io_start_addr, virt_memmap[VIRT_PCIE_PIO].base);
+
+ return irq_info;
+}
+
+static struct interface_info *init_interface_info(void *g_interface)
+{
+ struct interface_info *interface = g_interface;
+
+ stw_le_p(&interface->vers, 0x01);
+ strpadcpy(interface->description, 64, "UEFI_Version_v1.0", '\0');
+
+ return interface;
+}
+
+static struct board_devices *board_devices_info(void *g_board)
+{
+ struct board_devices *bd = g_board;
+
+ strpadcpy(bd->name, 64, "Loongson-3A-VIRT-1w-V1.00-demo", '\0');
+
+ return bd;
+}
+
+static struct loongson_special_attribute *init_special_info(void *g_special)
+{
+ struct loongson_special_attribute *special = g_special;
+
+ strpadcpy(special->special_name, 64, "2017-10-12", '\0');
+
+ return special;
+}
+
+void init_loongson_params(struct loongson_params *lp, void *p,
+ uint64_t cpu_freq, uint64_t ram_size)
+{
+ stq_le_p(&lp->cpu_offset,
+ (uintptr_t)init_cpu_info(p, cpu_freq) - (uintptr_t)lp);
+ p += ROUND_UP(sizeof(struct efi_cpuinfo_loongson), 64);
+
+ stq_le_p(&lp->memory_offset,
+ (uintptr_t)init_memory_map(p, ram_size) - (uintptr_t)lp);
+ p += ROUND_UP(sizeof(struct efi_memory_map_loongson), 64);
+
+ stq_le_p(&lp->system_offset,
+ (uintptr_t)init_system_loongson(p) - (uintptr_t)lp);
+ p += ROUND_UP(sizeof(struct system_loongson), 64);
+
+ stq_le_p(&lp->irq_offset,
+ (uintptr_t)init_irq_source(p) - (uintptr_t)lp);
+ p += ROUND_UP(sizeof(struct irq_source_routing_table), 64);
+
+ stq_le_p(&lp->interface_offset,
+ (uintptr_t)init_interface_info(p) - (uintptr_t)lp);
+ p += ROUND_UP(sizeof(struct interface_info), 64);
+
+ stq_le_p(&lp->boarddev_table_offset,
+ (uintptr_t)board_devices_info(p) - (uintptr_t)lp);
+ p += ROUND_UP(sizeof(struct board_devices), 64);
+
+ stq_le_p(&lp->special_offset,
+ (uintptr_t)init_special_info(p) - (uintptr_t)lp);
+ p += ROUND_UP(sizeof(struct loongson_special_attribute), 64);
+}
+
+void init_reset_system(struct efi_reset_system_t *reset)
+{
+ stq_le_p(&reset->Shutdown, 0xffffffffbfc000a8);
+ stq_le_p(&reset->ResetCold, 0xffffffffbfc00080);
+ stq_le_p(&reset->ResetWarm, 0xffffffffbfc00080);
+}
diff --git a/hw/mips/loongson3_bootp.h b/hw/mips/loongson3_bootp.h
new file mode 100644
index 0000000000..1edd736b6a
--- /dev/null
+++ b/hw/mips/loongson3_bootp.h
@@ -0,0 +1,225 @@
+/*
+ * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structrues
+ * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux kernel
+ */
+
+#ifndef HW_MIPS_LOONGSON3_BOOTP_H
+#define HW_MIPS_LOONGSON3_BOOTP_H
+
+struct efi_memory_map_loongson {
+ uint16_t vers; /* version of efi_memory_map */
+ uint32_t nr_map; /* number of memory_maps */
+ uint32_t mem_freq; /* memory frequence */
+ struct mem_map {
+ uint32_t node_id; /* node_id which memory attached to */
+ uint32_t mem_type; /* system memory, pci memory, pci io, etc. */
+ uint64_t mem_start; /* memory map start address */
+ uint32_t mem_size; /* each memory_map size, not the total size */
+ } map[128];
+} QEMU_PACKED;
+
+enum loongson_cpu_type {
+ Legacy_2E = 0x0,
+ Legacy_2F = 0x1,
+ Legacy_3A = 0x2,
+ Legacy_3B = 0x3,
+ Legacy_1A = 0x4,
+ Legacy_1B = 0x5,
+ Legacy_2G = 0x6,
+ Legacy_2H = 0x7,
+ Loongson_1A = 0x100,
+ Loongson_1B = 0x101,
+ Loongson_2E = 0x200,
+ Loongson_2F = 0x201,
+ Loongson_2G = 0x202,
+ Loongson_2H = 0x203,
+ Loongson_3A = 0x300,
+ Loongson_3B = 0x301
+};
+
+/*
+ * Capability and feature descriptor structure for MIPS CPU
+ */
+struct efi_cpuinfo_loongson {
+ uint16_t vers; /* version of efi_cpuinfo_loongson */
+ uint32_t processor_id; /* PRID, e.g. 6305, 6306 */
+ uint32_t cputype; /* Loongson_3A/3B, etc. */
+ uint32_t total_node; /* num of total numa nodes */
+ uint16_t cpu_startup_core_id; /* Boot core id */
+ uint16_t reserved_cores_mask;
+ uint32_t cpu_clock_freq; /* cpu_clock */
+ uint32_t nr_cpus;
+ char cpuname[64];
+} QEMU_PACKED;
+
+#define MAX_UARTS 64
+struct uart_device {
+ uint32_t iotype;
+ uint32_t uartclk;
+ uint32_t int_offset;
+ uint64_t uart_base;
+} QEMU_PACKED;
+
+#define MAX_SENSORS 64
+#define SENSOR_TEMPER 0x00000001
+#define SENSOR_VOLTAGE 0x00000002
+#define SENSOR_FAN 0x00000004
+struct sensor_device {
+ char name[32]; /* a formal name */
+ char label[64]; /* a flexible description */
+ uint32_t type; /* SENSOR_* */
+ uint32_t id; /* instance id of a sensor-class */
+ uint32_t fan_policy; /* step speed or constant speed */
+ uint32_t fan_percent;/* only for constant speed policy */
+ uint64_t base_addr; /* base address of device registers */
+} QEMU_PACKED;
+
+struct system_loongson {
+ uint16_t vers; /* version of system_loongson */
+ uint32_t ccnuma_smp; /* 0: no numa; 1: has numa */
+ uint32_t sing_double_channel;/* 1: single; 2: double */
+ uint32_t nr_uarts;
+ struct uart_device uarts[MAX_UARTS];
+ uint32_t nr_sensors;
+ struct sensor_device sensors[MAX_SENSORS];
+ char has_ec;
+ char ec_name[32];
+ uint64_t ec_base_addr;
+ char has_tcm;
+ char tcm_name[32];
+ uint64_t tcm_base_addr;
+ uint64_t workarounds;
+ uint64_t of_dtb_addr; /* NULL if not support */
+} QEMU_PACKED;
+
+struct irq_source_routing_table {
+ uint16_t vers;
+ uint16_t size;
+ uint16_t rtr_bus;
+ uint16_t rtr_devfn;
+ uint32_t vendor;
+ uint32_t device;
+ uint32_t PIC_type; /* conform use HT or PCI to route to CPU-PIC */
+ uint64_t ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
+ uint64_t ht_enable; /* irqs used in this PIC */
+ uint32_t node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
+ uint64_t pci_mem_start_addr;
+ uint64_t pci_mem_end_addr;
+ uint64_t pci_io_start_addr;
+ uint64_t pci_io_end_addr;
+ uint64_t pci_config_addr;
+ uint16_t dma_mask_bits;
+ uint16_t dma_noncoherent;
+} QEMU_PACKED;
+
+struct interface_info {
+ uint16_t vers; /* version of the specificition */
+ uint16_t size;
+ uint8_t flag;
+ char description[64];
+} QEMU_PACKED;
+
+#define MAX_RESOURCE_NUMBER 128
+struct resource_loongson {
+ uint64_t start; /* resource start address */
+ uint64_t end; /* resource end address */
+ char name[64];
+ uint32_t flags;
+};
+
+struct archdev_data {}; /* arch specific additions */
+
+struct board_devices {
+ char name[64]; /* hold the device name */
+ uint32_t num_resources; /* number of device_resource */
+ /* for each device's resource */
+ struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+ /* arch specific additions */
+ struct archdev_data archdata;
+};
+
+struct loongson_special_attribute {
+ uint16_t vers; /* version of this special */
+ char special_name[64]; /* special_atribute_name */
+ uint32_t loongson_special_type; /* type of special device */
+ /* for each device's resource */
+ struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+};
+
+struct loongson_params {
+ uint64_t memory_offset; /* efi_memory_map_loongson struct offset */
+ uint64_t cpu_offset; /* efi_cpuinfo_loongson struct offset */
+ uint64_t system_offset; /* system_loongson struct offset */
+ uint64_t irq_offset; /* irq_source_routing_table struct offset */
+ uint64_t interface_offset; /* interface_info struct offset */
+ uint64_t special_offset; /* loongson_special_attribute struct offset */
+ uint64_t boarddev_table_offset; /* board_devices offset */
+};
+
+struct smbios_tables {
+ uint16_t vers; /* version of smbios */
+ uint64_t vga_bios; /* vga_bios address */
+ struct loongson_params lp;
+};
+
+struct efi_reset_system_t {
+ uint64_t ResetCold;
+ uint64_t ResetWarm;
+ uint64_t ResetType;
+ uint64_t Shutdown;
+ uint64_t DoSuspend; /* NULL if not support */
+};
+
+struct efi_loongson {
+ uint64_t mps; /* MPS table */
+ uint64_t acpi; /* ACPI table (IA64 ext 0.71) */
+ uint64_t acpi20; /* ACPI table (ACPI 2.0) */
+ struct smbios_tables smbios; /* SM BIOS table */
+ uint64_t sal_systab; /* SAL system table */
+ uint64_t boot_info; /* boot info table */
+};
+
+struct boot_params {
+ struct efi_loongson efi;
+ struct efi_reset_system_t reset_system;
+};
+
+/* Overall MMIO & Memory layout */
+enum {
+ VIRT_LOWMEM,
+ VIRT_PM,
+ VIRT_FW_CFG,
+ VIRT_RTC,
+ VIRT_PCIE_PIO,
+ VIRT_PCIE_ECAM,
+ VIRT_BIOS_ROM,
+ VIRT_UART,
+ VIRT_LIOINTC,
+ VIRT_PCIE_MMIO,
+ VIRT_HIGHMEM
+};
+
+/* Low MEM layout for QEMU kernel loader */
+enum {
+ LOADER_KERNEL,
+ LOADER_INITRD,
+ LOADER_CMDLINE
+};
+
+/* BIOS ROM layout for QEMU kernel loader */
+enum {
+ LOADER_BOOTROM,
+ LOADER_PARAM,
+};
+
+struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+};
+
+extern const struct MemmapEntry virt_memmap[];
+void init_loongson_params(struct loongson_params *lp, void *p,
+ uint64_t cpu_freq, uint64_t ram_size);
+void init_reset_system(struct efi_reset_system_t *reset);
+
+#endif
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index c98391ce99..802e5e4a1d 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,6 +1,7 @@
mips_ss = ss.source_set()
mips_ss.add(files('addr.c', 'mips_int.c', 'fw_cfg.c'))
mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
+mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c'))
mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH V14 6/8] hw/mips: Add Loongson-3 boot parameter helpers
2020-10-16 6:51 ` [PATCH V14 6/8] hw/mips: Add Loongson-3 boot parameter helpers Huacai Chen
@ 2020-10-16 14:24 ` Philippe Mathieu-Daudé
2020-10-20 2:22 ` Huacai Chen
0 siblings, 1 reply; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-16 14:24 UTC (permalink / raw)
To: Huacai Chen, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
Hi Huacai,
On 10/16/20 8:51 AM, Huacai Chen wrote:
> Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
> UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
From the kernel documentation [*] on the "Co-developed-by" tag:
A Co-Developed-by: states that the patch was also created
by another developer along with the original author. This
is useful at times when multiple people work on a single
patch. Note, this person also needs to have a Signed-off-by:
line in the patch as well.
Can Jiaxun Yang add his Signed-off-by tag?
[*]
https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by
> ---
> hw/mips/loongson3_bootp.c | 162 +++++++++++++++++++++++++++
> hw/mips/loongson3_bootp.h | 225 ++++++++++++++++++++++++++++++++++++++
> hw/mips/meson.build | 1 +
> 3 files changed, 388 insertions(+)
> create mode 100644 hw/mips/loongson3_bootp.c
> create mode 100644 hw/mips/loongson3_bootp.h
Consider using scripts/git.orderfile to avoid reviewer
scrolling down/up/down/up.
>
> diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
> new file mode 100644
> index 0000000000..eab6f51a01
> --- /dev/null
> +++ b/hw/mips/loongson3_bootp.c
> @@ -0,0 +1,162 @@
> +/*
> + * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) helpers
> + *
> + * Copyright (c) 2017-2020 Huacai Chen (chenhc@lemote.com)
> + * Copyright (c) 2017-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "qemu/cutils.h"
> +#include "cpu.h"
> +#include "hw/boards.h"
> +#include "hw/mips/loongson3_bootp.h"
> +
> +static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq)
> +{
> + struct efi_cpuinfo_loongson *c = g_cpuinfo;
> +
> + stl_le_p(&c->cputype, Loongson_3A);
> + stl_le_p(&c->processor_id, MIPS_CPU(first_cpu)->env.CP0_PRid);
> + if (cpu_freq > UINT_MAX) {
> + stl_le_p(&c->cpu_clock_freq, UINT_MAX);
> + } else {
> + stl_le_p(&c->cpu_clock_freq, cpu_freq);
> + }
> +
> + stw_le_p(&c->cpu_startup_core_id, 0);
> + stl_le_p(&c->nr_cpus, current_machine->smp.cpus);
> + stl_le_p(&c->total_node, (current_machine->smp.cpus + 3) / 4);
Please replace this magic values by a definition, such:
#define LOONGSON3_CORE_PER_NODE 4
Then you can use:
stl_le_p(&c->total_node, DIV_ROUND_UP(current_machine->smp.cpus,
LOONGSON3_CORE_PER_NODE));
> +
> + return c;
> +}
> +
> +static struct efi_memory_map_loongson *init_memory_map(void *g_map, uint64_t ram_size)
> +{
> + struct efi_memory_map_loongson *emap = g_map;
> +
> + stl_le_p(&emap->nr_map, 2);
> + stl_le_p(&emap->mem_freq, 300000000);
> +
> + stl_le_p(&emap->map[0].node_id, 0);
> + stl_le_p(&emap->map[0].mem_type, 1);
> + stq_le_p(&emap->map[0].mem_start, 0x0);
> + stl_le_p(&emap->map[0].mem_size, 240);
> +
> + stl_le_p(&emap->map[1].node_id, 0);
> + stl_le_p(&emap->map[1].mem_type, 2);
> + stq_le_p(&emap->map[1].mem_start, 0x90000000);
> + stl_le_p(&emap->map[1].mem_size, (ram_size / MiB) - 256);
> +
> + return emap;
> +}
> +
> +static struct system_loongson *init_system_loongson(void *g_system)
> +{
> + struct system_loongson *s = g_system;
> +
> + stl_le_p(&s->ccnuma_smp, 0);
> + stl_le_p(&s->sing_double_channel, 1);
> + stl_le_p(&s->nr_uarts, 1);
> + stl_le_p(&s->uarts[0].iotype, 2);
> + stl_le_p(&s->uarts[0].int_offset, 2);
> + stl_le_p(&s->uarts[0].uartclk, 25000000); /* Random value */
> + stq_le_p(&s->uarts[0].uart_base, virt_memmap[VIRT_UART].base);
> +
> + return s;
> +}
> +
> +static struct irq_source_routing_table *init_irq_source(void *g_irq_source)
> +{
> + struct irq_source_routing_table *irq_info = g_irq_source;
> +
> + stl_le_p(&irq_info->node_id, 0);
> + stl_le_p(&irq_info->PIC_type, 0);
> + stw_le_p(&irq_info->dma_mask_bits, 64);
> + stq_le_p(&irq_info->pci_mem_start_addr, virt_memmap[VIRT_PCIE_MMIO].base);
> + stq_le_p(&irq_info->pci_mem_end_addr, virt_memmap[VIRT_PCIE_MMIO].base +
> + virt_memmap[VIRT_PCIE_MMIO].size - 1);
> + stq_le_p(&irq_info->pci_io_start_addr, virt_memmap[VIRT_PCIE_PIO].base);
> +
> + return irq_info;
> +}
> +
> +static struct interface_info *init_interface_info(void *g_interface)
> +{
> + struct interface_info *interface = g_interface;
> +
> + stw_le_p(&interface->vers, 0x01);
> + strpadcpy(interface->description, 64, "UEFI_Version_v1.0", '\0');
> +
> + return interface;
> +}
> +
> +static struct board_devices *board_devices_info(void *g_board)
> +{
> + struct board_devices *bd = g_board;
> +
> + strpadcpy(bd->name, 64, "Loongson-3A-VIRT-1w-V1.00-demo", '\0');
> +
> + return bd;
> +}
> +
> +static struct loongson_special_attribute *init_special_info(void *g_special)
> +{
> + struct loongson_special_attribute *special = g_special;
> +
> + strpadcpy(special->special_name, 64, "2017-10-12", '\0');
> +
> + return special;
> +}
> +
> +void init_loongson_params(struct loongson_params *lp, void *p,
> + uint64_t cpu_freq, uint64_t ram_size)
> +{
> + stq_le_p(&lp->cpu_offset,
> + (uintptr_t)init_cpu_info(p, cpu_freq) - (uintptr_t)lp);
> + p += ROUND_UP(sizeof(struct efi_cpuinfo_loongson), 64);
> +
> + stq_le_p(&lp->memory_offset,
> + (uintptr_t)init_memory_map(p, ram_size) - (uintptr_t)lp);
> + p += ROUND_UP(sizeof(struct efi_memory_map_loongson), 64);
> +
> + stq_le_p(&lp->system_offset,
> + (uintptr_t)init_system_loongson(p) - (uintptr_t)lp);
> + p += ROUND_UP(sizeof(struct system_loongson), 64);
> +
> + stq_le_p(&lp->irq_offset,
> + (uintptr_t)init_irq_source(p) - (uintptr_t)lp);
> + p += ROUND_UP(sizeof(struct irq_source_routing_table), 64);
> +
> + stq_le_p(&lp->interface_offset,
> + (uintptr_t)init_interface_info(p) - (uintptr_t)lp);
> + p += ROUND_UP(sizeof(struct interface_info), 64);
> +
> + stq_le_p(&lp->boarddev_table_offset,
> + (uintptr_t)board_devices_info(p) - (uintptr_t)lp);
> + p += ROUND_UP(sizeof(struct board_devices), 64);
> +
> + stq_le_p(&lp->special_offset,
> + (uintptr_t)init_special_info(p) - (uintptr_t)lp);
> + p += ROUND_UP(sizeof(struct loongson_special_attribute), 64);
> +}
> +
> +void init_reset_system(struct efi_reset_system_t *reset)
> +{
> + stq_le_p(&reset->Shutdown, 0xffffffffbfc000a8);
> + stq_le_p(&reset->ResetCold, 0xffffffffbfc00080);
> + stq_le_p(&reset->ResetWarm, 0xffffffffbfc00080);
> +}
> diff --git a/hw/mips/loongson3_bootp.h b/hw/mips/loongson3_bootp.h
> new file mode 100644
> index 0000000000..1edd736b6a
> --- /dev/null
> +++ b/hw/mips/loongson3_bootp.h
> @@ -0,0 +1,225 @@
> +/*
> + * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structrues
> + * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux kernel
Missing license boilerplate.
> + */
> +
> +#ifndef HW_MIPS_LOONGSON3_BOOTP_H
> +#define HW_MIPS_LOONGSON3_BOOTP_H
> +
> +struct efi_memory_map_loongson {
> + uint16_t vers; /* version of efi_memory_map */
> + uint32_t nr_map; /* number of memory_maps */
> + uint32_t mem_freq; /* memory frequence */
> + struct mem_map {
> + uint32_t node_id; /* node_id which memory attached to */
> + uint32_t mem_type; /* system memory, pci memory, pci io, etc. */
> + uint64_t mem_start; /* memory map start address */
> + uint32_t mem_size; /* each memory_map size, not the total size */
> + } map[128];
> +} QEMU_PACKED;
> +
> +enum loongson_cpu_type {
> + Legacy_2E = 0x0,
> + Legacy_2F = 0x1,
> + Legacy_3A = 0x2,
> + Legacy_3B = 0x3,
> + Legacy_1A = 0x4,
> + Legacy_1B = 0x5,
> + Legacy_2G = 0x6,
> + Legacy_2H = 0x7,
> + Loongson_1A = 0x100,
> + Loongson_1B = 0x101,
> + Loongson_2E = 0x200,
> + Loongson_2F = 0x201,
> + Loongson_2G = 0x202,
> + Loongson_2H = 0x203,
> + Loongson_3A = 0x300,
> + Loongson_3B = 0x301
> +};
> +
> +/*
> + * Capability and feature descriptor structure for MIPS CPU
> + */
> +struct efi_cpuinfo_loongson {
> + uint16_t vers; /* version of efi_cpuinfo_loongson */
> + uint32_t processor_id; /* PRID, e.g. 6305, 6306 */
> + uint32_t cputype; /* Loongson_3A/3B, etc. */
> + uint32_t total_node; /* num of total numa nodes */
> + uint16_t cpu_startup_core_id; /* Boot core id */
> + uint16_t reserved_cores_mask;
> + uint32_t cpu_clock_freq; /* cpu_clock */
> + uint32_t nr_cpus;
> + char cpuname[64];
> +} QEMU_PACKED;
> +
> +#define MAX_UARTS 64
> +struct uart_device {
> + uint32_t iotype;
> + uint32_t uartclk;
> + uint32_t int_offset;
> + uint64_t uart_base;
> +} QEMU_PACKED;
> +
> +#define MAX_SENSORS 64
> +#define SENSOR_TEMPER 0x00000001
> +#define SENSOR_VOLTAGE 0x00000002
> +#define SENSOR_FAN 0x00000004
> +struct sensor_device {
> + char name[32]; /* a formal name */
> + char label[64]; /* a flexible description */
> + uint32_t type; /* SENSOR_* */
> + uint32_t id; /* instance id of a sensor-class */
> + uint32_t fan_policy; /* step speed or constant speed */
> + uint32_t fan_percent;/* only for constant speed policy */
> + uint64_t base_addr; /* base address of device registers */
> +} QEMU_PACKED;
> +
> +struct system_loongson {
> + uint16_t vers; /* version of system_loongson */
> + uint32_t ccnuma_smp; /* 0: no numa; 1: has numa */
> + uint32_t sing_double_channel;/* 1: single; 2: double */
> + uint32_t nr_uarts;
> + struct uart_device uarts[MAX_UARTS];
> + uint32_t nr_sensors;
> + struct sensor_device sensors[MAX_SENSORS];
> + char has_ec;
> + char ec_name[32];
> + uint64_t ec_base_addr;
> + char has_tcm;
> + char tcm_name[32];
> + uint64_t tcm_base_addr;
> + uint64_t workarounds;
> + uint64_t of_dtb_addr; /* NULL if not support */
> +} QEMU_PACKED;
> +
> +struct irq_source_routing_table {
> + uint16_t vers;
> + uint16_t size;
> + uint16_t rtr_bus;
> + uint16_t rtr_devfn;
> + uint32_t vendor;
> + uint32_t device;
> + uint32_t PIC_type; /* conform use HT or PCI to route to CPU-PIC */
> + uint64_t ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
> + uint64_t ht_enable; /* irqs used in this PIC */
> + uint32_t node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
> + uint64_t pci_mem_start_addr;
> + uint64_t pci_mem_end_addr;
> + uint64_t pci_io_start_addr;
> + uint64_t pci_io_end_addr;
> + uint64_t pci_config_addr;
> + uint16_t dma_mask_bits;
> + uint16_t dma_noncoherent;
> +} QEMU_PACKED;
> +
> +struct interface_info {
> + uint16_t vers; /* version of the specificition */
> + uint16_t size;
> + uint8_t flag;
> + char description[64];
> +} QEMU_PACKED;
> +
> +#define MAX_RESOURCE_NUMBER 128
> +struct resource_loongson {
> + uint64_t start; /* resource start address */
> + uint64_t end; /* resource end address */
> + char name[64];
> + uint32_t flags;
> +};
> +
> +struct archdev_data {}; /* arch specific additions */
> +
> +struct board_devices {
> + char name[64]; /* hold the device name */
> + uint32_t num_resources; /* number of device_resource */
> + /* for each device's resource */
> + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> + /* arch specific additions */
> + struct archdev_data archdata;
Maybe drop archdev_data and use:
char arch_specific_data[];
> +};
> +
> +struct loongson_special_attribute {
> + uint16_t vers; /* version of this special */
> + char special_name[64]; /* special_atribute_name */
> + uint32_t loongson_special_type; /* type of special device */
> + /* for each device's resource */
> + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> +};
> +
> +struct loongson_params {
> + uint64_t memory_offset; /* efi_memory_map_loongson struct offset */
> + uint64_t cpu_offset; /* efi_cpuinfo_loongson struct offset */
> + uint64_t system_offset; /* system_loongson struct offset */
> + uint64_t irq_offset; /* irq_source_routing_table struct offset */
> + uint64_t interface_offset; /* interface_info struct offset */
> + uint64_t special_offset; /* loongson_special_attribute struct offset */
> + uint64_t boarddev_table_offset; /* board_devices offset */
> +};
> +
> +struct smbios_tables {
> + uint16_t vers; /* version of smbios */
> + uint64_t vga_bios; /* vga_bios address */
> + struct loongson_params lp;
> +};
> +
> +struct efi_reset_system_t {
> + uint64_t ResetCold;
> + uint64_t ResetWarm;
> + uint64_t ResetType;
> + uint64_t Shutdown;
> + uint64_t DoSuspend; /* NULL if not support */
> +};
> +
> +struct efi_loongson {
> + uint64_t mps; /* MPS table */
> + uint64_t acpi; /* ACPI table (IA64 ext 0.71) */
> + uint64_t acpi20; /* ACPI table (ACPI 2.0) */
> + struct smbios_tables smbios; /* SM BIOS table */
> + uint64_t sal_systab; /* SAL system table */
> + uint64_t boot_info; /* boot info table */
> +};
> +
> +struct boot_params {
> + struct efi_loongson efi;
> + struct efi_reset_system_t reset_system;
> +};
> +
> +/* Overall MMIO & Memory layout */
> +enum {
> + VIRT_LOWMEM,
> + VIRT_PM,
> + VIRT_FW_CFG,
> + VIRT_RTC,
> + VIRT_PCIE_PIO,
> + VIRT_PCIE_ECAM,
> + VIRT_BIOS_ROM,
> + VIRT_UART,
> + VIRT_LIOINTC,
> + VIRT_PCIE_MMIO,
> + VIRT_HIGHMEM
> +};
> +
> +/* Low MEM layout for QEMU kernel loader */
> +enum {
> + LOADER_KERNEL,
> + LOADER_INITRD,
> + LOADER_CMDLINE
> +};
> +
> +/* BIOS ROM layout for QEMU kernel loader */
> +enum {
> + LOADER_BOOTROM,
> + LOADER_PARAM,
> +};
> +
> +struct MemmapEntry {
> + hwaddr base;
> + hwaddr size;
> +};
> +
> +extern const struct MemmapEntry virt_memmap[];
> +void init_loongson_params(struct loongson_params *lp, void *p,
> + uint64_t cpu_freq, uint64_t ram_size);
> +void init_reset_system(struct efi_reset_system_t *reset);
> +
> +#endif
> diff --git a/hw/mips/meson.build b/hw/mips/meson.build
> index c98391ce99..802e5e4a1d 100644
> --- a/hw/mips/meson.build
> +++ b/hw/mips/meson.build
> @@ -1,6 +1,7 @@
> mips_ss = ss.source_set()
> mips_ss.add(files('addr.c', 'mips_int.c', 'fw_cfg.c'))
> mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
> +mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c'))
> mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
> mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
> mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
>
With comment addressed: Reviewed-by: Philippe Mathieu-Daudé
<f4bug@amsat.org>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH V14 6/8] hw/mips: Add Loongson-3 boot parameter helpers
2020-10-16 14:24 ` Philippe Mathieu-Daudé
@ 2020-10-20 2:22 ` Huacai Chen
0 siblings, 0 replies; 20+ messages in thread
From: Huacai Chen @ 2020-10-20 2:22 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Huacai Chen, Aleksandar Markovic, Aleksandar Rikalo,
Aurelien Jarno, QEMU Developers
Hi, Philippe,
On Fri, Oct 16, 2020 at 10:24 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Huacai,
>
> On 10/16/20 8:51 AM, Huacai Chen wrote:
> > Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
> > UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
> >
> > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> From the kernel documentation [*] on the "Co-developed-by" tag:
>
> A Co-Developed-by: states that the patch was also created
> by another developer along with the original author. This
> is useful at times when multiple people work on a single
> patch. Note, this person also needs to have a Signed-off-by:
> line in the patch as well.
>
> Can Jiaxun Yang add his Signed-off-by tag?
OK, I will add him.
>
> [*]
> https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by
>
> > ---
> > hw/mips/loongson3_bootp.c | 162 +++++++++++++++++++++++++++
> > hw/mips/loongson3_bootp.h | 225 ++++++++++++++++++++++++++++++++++++++
> > hw/mips/meson.build | 1 +
> > 3 files changed, 388 insertions(+)
> > create mode 100644 hw/mips/loongson3_bootp.c
> > create mode 100644 hw/mips/loongson3_bootp.h
>
> Consider using scripts/git.orderfile to avoid reviewer
> scrolling down/up/down/up.
OK, I will do.
>
> >
> > diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
> > new file mode 100644
> > index 0000000000..eab6f51a01
> > --- /dev/null
> > +++ b/hw/mips/loongson3_bootp.c
> > @@ -0,0 +1,162 @@
> > +/*
> > + * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) helpers
> > + *
> > + * Copyright (c) 2017-2020 Huacai Chen (chenhc@lemote.com)
> > + * Copyright (c) 2017-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation, either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/units.h"
> > +#include "qemu/cutils.h"
> > +#include "cpu.h"
> > +#include "hw/boards.h"
> > +#include "hw/mips/loongson3_bootp.h"
> > +
> > +static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq)
> > +{
> > + struct efi_cpuinfo_loongson *c = g_cpuinfo;
> > +
> > + stl_le_p(&c->cputype, Loongson_3A);
> > + stl_le_p(&c->processor_id, MIPS_CPU(first_cpu)->env.CP0_PRid);
> > + if (cpu_freq > UINT_MAX) {
> > + stl_le_p(&c->cpu_clock_freq, UINT_MAX);
> > + } else {
> > + stl_le_p(&c->cpu_clock_freq, cpu_freq);
> > + }
> > +
> > + stw_le_p(&c->cpu_startup_core_id, 0);
> > + stl_le_p(&c->nr_cpus, current_machine->smp.cpus);
> > + stl_le_p(&c->total_node, (current_machine->smp.cpus + 3) / 4);
>
> Please replace this magic values by a definition, such:
>
> #define LOONGSON3_CORE_PER_NODE 4
>
> Then you can use:
>
> stl_le_p(&c->total_node, DIV_ROUND_UP(current_machine->smp.cpus,
> LOONGSON3_CORE_PER_NODE));
>
OK, Thank you.
> > +
> > + return c;
> > +}
> > +
> > +static struct efi_memory_map_loongson *init_memory_map(void *g_map, uint64_t ram_size)
> > +{
> > + struct efi_memory_map_loongson *emap = g_map;
> > +
> > + stl_le_p(&emap->nr_map, 2);
> > + stl_le_p(&emap->mem_freq, 300000000);
> > +
> > + stl_le_p(&emap->map[0].node_id, 0);
> > + stl_le_p(&emap->map[0].mem_type, 1);
> > + stq_le_p(&emap->map[0].mem_start, 0x0);
> > + stl_le_p(&emap->map[0].mem_size, 240);
> > +
> > + stl_le_p(&emap->map[1].node_id, 0);
> > + stl_le_p(&emap->map[1].mem_type, 2);
> > + stq_le_p(&emap->map[1].mem_start, 0x90000000);
> > + stl_le_p(&emap->map[1].mem_size, (ram_size / MiB) - 256);
> > +
> > + return emap;
> > +}
> > +
> > +static struct system_loongson *init_system_loongson(void *g_system)
> > +{
> > + struct system_loongson *s = g_system;
> > +
> > + stl_le_p(&s->ccnuma_smp, 0);
> > + stl_le_p(&s->sing_double_channel, 1);
> > + stl_le_p(&s->nr_uarts, 1);
> > + stl_le_p(&s->uarts[0].iotype, 2);
> > + stl_le_p(&s->uarts[0].int_offset, 2);
> > + stl_le_p(&s->uarts[0].uartclk, 25000000); /* Random value */
> > + stq_le_p(&s->uarts[0].uart_base, virt_memmap[VIRT_UART].base);
> > +
> > + return s;
> > +}
> > +
> > +static struct irq_source_routing_table *init_irq_source(void *g_irq_source)
> > +{
> > + struct irq_source_routing_table *irq_info = g_irq_source;
> > +
> > + stl_le_p(&irq_info->node_id, 0);
> > + stl_le_p(&irq_info->PIC_type, 0);
> > + stw_le_p(&irq_info->dma_mask_bits, 64);
> > + stq_le_p(&irq_info->pci_mem_start_addr, virt_memmap[VIRT_PCIE_MMIO].base);
> > + stq_le_p(&irq_info->pci_mem_end_addr, virt_memmap[VIRT_PCIE_MMIO].base +
> > + virt_memmap[VIRT_PCIE_MMIO].size - 1);
> > + stq_le_p(&irq_info->pci_io_start_addr, virt_memmap[VIRT_PCIE_PIO].base);
> > +
> > + return irq_info;
> > +}
> > +
> > +static struct interface_info *init_interface_info(void *g_interface)
> > +{
> > + struct interface_info *interface = g_interface;
> > +
> > + stw_le_p(&interface->vers, 0x01);
> > + strpadcpy(interface->description, 64, "UEFI_Version_v1.0", '\0');
> > +
> > + return interface;
> > +}
> > +
> > +static struct board_devices *board_devices_info(void *g_board)
> > +{
> > + struct board_devices *bd = g_board;
> > +
> > + strpadcpy(bd->name, 64, "Loongson-3A-VIRT-1w-V1.00-demo", '\0');
> > +
> > + return bd;
> > +}
> > +
> > +static struct loongson_special_attribute *init_special_info(void *g_special)
> > +{
> > + struct loongson_special_attribute *special = g_special;
> > +
> > + strpadcpy(special->special_name, 64, "2017-10-12", '\0');
> > +
> > + return special;
> > +}
> > +
> > +void init_loongson_params(struct loongson_params *lp, void *p,
> > + uint64_t cpu_freq, uint64_t ram_size)
> > +{
> > + stq_le_p(&lp->cpu_offset,
> > + (uintptr_t)init_cpu_info(p, cpu_freq) - (uintptr_t)lp);
> > + p += ROUND_UP(sizeof(struct efi_cpuinfo_loongson), 64);
> > +
> > + stq_le_p(&lp->memory_offset,
> > + (uintptr_t)init_memory_map(p, ram_size) - (uintptr_t)lp);
> > + p += ROUND_UP(sizeof(struct efi_memory_map_loongson), 64);
> > +
> > + stq_le_p(&lp->system_offset,
> > + (uintptr_t)init_system_loongson(p) - (uintptr_t)lp);
> > + p += ROUND_UP(sizeof(struct system_loongson), 64);
> > +
> > + stq_le_p(&lp->irq_offset,
> > + (uintptr_t)init_irq_source(p) - (uintptr_t)lp);
> > + p += ROUND_UP(sizeof(struct irq_source_routing_table), 64);
> > +
> > + stq_le_p(&lp->interface_offset,
> > + (uintptr_t)init_interface_info(p) - (uintptr_t)lp);
> > + p += ROUND_UP(sizeof(struct interface_info), 64);
> > +
> > + stq_le_p(&lp->boarddev_table_offset,
> > + (uintptr_t)board_devices_info(p) - (uintptr_t)lp);
> > + p += ROUND_UP(sizeof(struct board_devices), 64);
> > +
> > + stq_le_p(&lp->special_offset,
> > + (uintptr_t)init_special_info(p) - (uintptr_t)lp);
> > + p += ROUND_UP(sizeof(struct loongson_special_attribute), 64);
> > +}
> > +
> > +void init_reset_system(struct efi_reset_system_t *reset)
> > +{
> > + stq_le_p(&reset->Shutdown, 0xffffffffbfc000a8);
> > + stq_le_p(&reset->ResetCold, 0xffffffffbfc00080);
> > + stq_le_p(&reset->ResetWarm, 0xffffffffbfc00080);
> > +}
> > diff --git a/hw/mips/loongson3_bootp.h b/hw/mips/loongson3_bootp.h
> > new file mode 100644
> > index 0000000000..1edd736b6a
> > --- /dev/null
> > +++ b/hw/mips/loongson3_bootp.h
> > @@ -0,0 +1,225 @@
> > +/*
> > + * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structrues
> > + * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux kernel
>
> Missing license boilerplate.
I thought this is unneccesary for a .h file, and I will add that in
the next version.
>
> > + */
> > +
> > +#ifndef HW_MIPS_LOONGSON3_BOOTP_H
> > +#define HW_MIPS_LOONGSON3_BOOTP_H
> > +
> > +struct efi_memory_map_loongson {
> > + uint16_t vers; /* version of efi_memory_map */
> > + uint32_t nr_map; /* number of memory_maps */
> > + uint32_t mem_freq; /* memory frequence */
> > + struct mem_map {
> > + uint32_t node_id; /* node_id which memory attached to */
> > + uint32_t mem_type; /* system memory, pci memory, pci io, etc. */
> > + uint64_t mem_start; /* memory map start address */
> > + uint32_t mem_size; /* each memory_map size, not the total size */
> > + } map[128];
> > +} QEMU_PACKED;
> > +
> > +enum loongson_cpu_type {
> > + Legacy_2E = 0x0,
> > + Legacy_2F = 0x1,
> > + Legacy_3A = 0x2,
> > + Legacy_3B = 0x3,
> > + Legacy_1A = 0x4,
> > + Legacy_1B = 0x5,
> > + Legacy_2G = 0x6,
> > + Legacy_2H = 0x7,
> > + Loongson_1A = 0x100,
> > + Loongson_1B = 0x101,
> > + Loongson_2E = 0x200,
> > + Loongson_2F = 0x201,
> > + Loongson_2G = 0x202,
> > + Loongson_2H = 0x203,
> > + Loongson_3A = 0x300,
> > + Loongson_3B = 0x301
> > +};
> > +
> > +/*
> > + * Capability and feature descriptor structure for MIPS CPU
> > + */
> > +struct efi_cpuinfo_loongson {
> > + uint16_t vers; /* version of efi_cpuinfo_loongson */
> > + uint32_t processor_id; /* PRID, e.g. 6305, 6306 */
> > + uint32_t cputype; /* Loongson_3A/3B, etc. */
> > + uint32_t total_node; /* num of total numa nodes */
> > + uint16_t cpu_startup_core_id; /* Boot core id */
> > + uint16_t reserved_cores_mask;
> > + uint32_t cpu_clock_freq; /* cpu_clock */
> > + uint32_t nr_cpus;
> > + char cpuname[64];
> > +} QEMU_PACKED;
> > +
> > +#define MAX_UARTS 64
> > +struct uart_device {
> > + uint32_t iotype;
> > + uint32_t uartclk;
> > + uint32_t int_offset;
> > + uint64_t uart_base;
> > +} QEMU_PACKED;
> > +
> > +#define MAX_SENSORS 64
> > +#define SENSOR_TEMPER 0x00000001
> > +#define SENSOR_VOLTAGE 0x00000002
> > +#define SENSOR_FAN 0x00000004
> > +struct sensor_device {
> > + char name[32]; /* a formal name */
> > + char label[64]; /* a flexible description */
> > + uint32_t type; /* SENSOR_* */
> > + uint32_t id; /* instance id of a sensor-class */
> > + uint32_t fan_policy; /* step speed or constant speed */
> > + uint32_t fan_percent;/* only for constant speed policy */
> > + uint64_t base_addr; /* base address of device registers */
> > +} QEMU_PACKED;
> > +
> > +struct system_loongson {
> > + uint16_t vers; /* version of system_loongson */
> > + uint32_t ccnuma_smp; /* 0: no numa; 1: has numa */
> > + uint32_t sing_double_channel;/* 1: single; 2: double */
> > + uint32_t nr_uarts;
> > + struct uart_device uarts[MAX_UARTS];
> > + uint32_t nr_sensors;
> > + struct sensor_device sensors[MAX_SENSORS];
> > + char has_ec;
> > + char ec_name[32];
> > + uint64_t ec_base_addr;
> > + char has_tcm;
> > + char tcm_name[32];
> > + uint64_t tcm_base_addr;
> > + uint64_t workarounds;
> > + uint64_t of_dtb_addr; /* NULL if not support */
> > +} QEMU_PACKED;
> > +
> > +struct irq_source_routing_table {
> > + uint16_t vers;
> > + uint16_t size;
> > + uint16_t rtr_bus;
> > + uint16_t rtr_devfn;
> > + uint32_t vendor;
> > + uint32_t device;
> > + uint32_t PIC_type; /* conform use HT or PCI to route to CPU-PIC */
> > + uint64_t ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
> > + uint64_t ht_enable; /* irqs used in this PIC */
> > + uint32_t node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
> > + uint64_t pci_mem_start_addr;
> > + uint64_t pci_mem_end_addr;
> > + uint64_t pci_io_start_addr;
> > + uint64_t pci_io_end_addr;
> > + uint64_t pci_config_addr;
> > + uint16_t dma_mask_bits;
> > + uint16_t dma_noncoherent;
> > +} QEMU_PACKED;
> > +
> > +struct interface_info {
> > + uint16_t vers; /* version of the specificition */
> > + uint16_t size;
> > + uint8_t flag;
> > + char description[64];
> > +} QEMU_PACKED;
> > +
> > +#define MAX_RESOURCE_NUMBER 128
> > +struct resource_loongson {
> > + uint64_t start; /* resource start address */
> > + uint64_t end; /* resource end address */
> > + char name[64];
> > + uint32_t flags;
> > +};
> > +
> > +struct archdev_data {}; /* arch specific additions */
> > +
> > +struct board_devices {
> > + char name[64]; /* hold the device name */
> > + uint32_t num_resources; /* number of device_resource */
> > + /* for each device's resource */
> > + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> > + /* arch specific additions */
> > + struct archdev_data archdata;
>
> Maybe drop archdev_data and use:
>
> char arch_specific_data[];
I just keep consistency with Linux kernel here.
>
> > +};
> > +
> > +struct loongson_special_attribute {
> > + uint16_t vers; /* version of this special */
> > + char special_name[64]; /* special_atribute_name */
> > + uint32_t loongson_special_type; /* type of special device */
> > + /* for each device's resource */
> > + struct resource_loongson resource[MAX_RESOURCE_NUMBER];
> > +};
> > +
> > +struct loongson_params {
> > + uint64_t memory_offset; /* efi_memory_map_loongson struct offset */
> > + uint64_t cpu_offset; /* efi_cpuinfo_loongson struct offset */
> > + uint64_t system_offset; /* system_loongson struct offset */
> > + uint64_t irq_offset; /* irq_source_routing_table struct offset */
> > + uint64_t interface_offset; /* interface_info struct offset */
> > + uint64_t special_offset; /* loongson_special_attribute struct offset */
> > + uint64_t boarddev_table_offset; /* board_devices offset */
> > +};
> > +
> > +struct smbios_tables {
> > + uint16_t vers; /* version of smbios */
> > + uint64_t vga_bios; /* vga_bios address */
> > + struct loongson_params lp;
> > +};
> > +
> > +struct efi_reset_system_t {
> > + uint64_t ResetCold;
> > + uint64_t ResetWarm;
> > + uint64_t ResetType;
> > + uint64_t Shutdown;
> > + uint64_t DoSuspend; /* NULL if not support */
> > +};
> > +
> > +struct efi_loongson {
> > + uint64_t mps; /* MPS table */
> > + uint64_t acpi; /* ACPI table (IA64 ext 0.71) */
> > + uint64_t acpi20; /* ACPI table (ACPI 2.0) */
> > + struct smbios_tables smbios; /* SM BIOS table */
> > + uint64_t sal_systab; /* SAL system table */
> > + uint64_t boot_info; /* boot info table */
> > +};
> > +
> > +struct boot_params {
> > + struct efi_loongson efi;
> > + struct efi_reset_system_t reset_system;
> > +};
> > +
> > +/* Overall MMIO & Memory layout */
> > +enum {
> > + VIRT_LOWMEM,
> > + VIRT_PM,
> > + VIRT_FW_CFG,
> > + VIRT_RTC,
> > + VIRT_PCIE_PIO,
> > + VIRT_PCIE_ECAM,
> > + VIRT_BIOS_ROM,
> > + VIRT_UART,
> > + VIRT_LIOINTC,
> > + VIRT_PCIE_MMIO,
> > + VIRT_HIGHMEM
> > +};
> > +
> > +/* Low MEM layout for QEMU kernel loader */
> > +enum {
> > + LOADER_KERNEL,
> > + LOADER_INITRD,
> > + LOADER_CMDLINE
> > +};
> > +
> > +/* BIOS ROM layout for QEMU kernel loader */
> > +enum {
> > + LOADER_BOOTROM,
> > + LOADER_PARAM,
> > +};
> > +
> > +struct MemmapEntry {
> > + hwaddr base;
> > + hwaddr size;
> > +};
> > +
> > +extern const struct MemmapEntry virt_memmap[];
> > +void init_loongson_params(struct loongson_params *lp, void *p,
> > + uint64_t cpu_freq, uint64_t ram_size);
> > +void init_reset_system(struct efi_reset_system_t *reset);
> > +
> > +#endif
> > diff --git a/hw/mips/meson.build b/hw/mips/meson.build
> > index c98391ce99..802e5e4a1d 100644
> > --- a/hw/mips/meson.build
> > +++ b/hw/mips/meson.build
> > @@ -1,6 +1,7 @@
> > mips_ss = ss.source_set()
> > mips_ss.add(files('addr.c', 'mips_int.c', 'fw_cfg.c'))
> > mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
> > +mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c'))
> > mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
> > mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
> > mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
> >
>
> With comment addressed: Reviewed-by: Philippe Mathieu-Daudé
> <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH V14 7/8] hw/mips: Add Loongson-3 machine support
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
` (5 preceding siblings ...)
2020-10-16 6:51 ` [PATCH V14 6/8] hw/mips: Add Loongson-3 boot parameter helpers Huacai Chen
@ 2020-10-16 6:51 ` Huacai Chen
2020-10-17 15:58 ` Philippe Mathieu-Daudé
2020-10-16 6:52 ` [PATCH V14 8/8] docs/system: Update MIPS machine documentation Huacai Chen
` (2 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
Add Loongson-3 based machine support, it use liointc as the interrupt
controler and use GPEX as the pci controller. Currently it can work with
both TCG and KVM.
As the machine model is not based on any exiting physical hardware, the
name of the machine is "loongson3-virt". It may be superseded in future
by a real machine model. If this happens, then a regular deprecation
procedure shall occur for "loongson3-virt" machine.
We now already have a full functional Linux kernel (based on Linux-5.4.x
LTS, the kvm host side and guest side have both been upstream for Linux-
5.9, but Linux-5.9 has not been released yet) here:
https://github.com/chenhuacai/linux
Of course the upstream kernel is also usable (though it is "unstable"
now):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
How to use QEMU/Loongson-3?
1, Download kernel source from the above URL;
2, Build a kernel with arch/mips/configs/loongson3_defconfig;
3, Boot a Loongson-3A4000 host with this kernel (for KVM mode);
4, Build QEMU-master with this patchset;
5, modprobe kvm (only necessary for KVM mode);
6, Use QEMU with TCG:
qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ...
Use QEMU with KVM:
qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ...
The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
default-configs/devices/mips64el-softmmu.mak | 1 +
hw/mips/Kconfig | 12 +
hw/mips/loongson3_virt.c | 615 +++++++++++++++++++
hw/mips/meson.build | 2 +-
4 files changed, 629 insertions(+), 1 deletion(-)
create mode 100644 hw/mips/loongson3_virt.c
diff --git a/default-configs/devices/mips64el-softmmu.mak b/default-configs/devices/mips64el-softmmu.mak
index 9f8a3ef156..26c660a05c 100644
--- a/default-configs/devices/mips64el-softmmu.mak
+++ b/default-configs/devices/mips64el-softmmu.mak
@@ -3,6 +3,7 @@
include mips-softmmu-common.mak
CONFIG_IDE_VIA=y
CONFIG_FULOONG=y
+CONFIG_LOONGSON3V=y
CONFIG_ATI_VGA=y
CONFIG_RTL8139_PCI=y
CONFIG_JAZZ=y
diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index 67d39c56a4..6562b346ab 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -45,6 +45,18 @@ config FULOONG
bool
select PCI_BONITO
+config LOONGSON3V
+ bool
+ select PCKBD
+ select SERIAL
+ select GOLDFISH_RTC
+ select LOONGSON_LIOINTC
+ select PCI_DEVICES
+ select PCI_EXPRESS_GENERIC_BRIDGE
+ select VIRTIO_VGA
+ select QXL if SPICE
+ select MSI_NONBROKEN
+
config MIPS_CPS
bool
select PTIMER
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
new file mode 100644
index 0000000000..c298a16793
--- /dev/null
+++ b/hw/mips/loongson3_virt.c
@@ -0,0 +1,627 @@
+/*
+ * Generic Loongson-3 Platform support
+ *
+ * Copyright (c) 2017-2020 Huacai Chen (chenhc@lemote.com)
+ * Copyright (c) 2017-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
+ * extensions, 800~2000MHz)
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "elf.h"
+#include "kvm_mips.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/mips/mips.h"
+#include "hw/mips/cpudevs.h"
+#include "hw/mips/fw_cfg.h"
+#include "hw/mips/loongson3_bootp.h"
+#include "hw/misc/unimp.h"
+#include "hw/intc/i8259.h"
+#include "hw/loader.h"
+#include "hw/isa/superio.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb.h"
+#include "net/net.h"
+#include "exec/address-spaces.h"
+#include "sysemu/kvm.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+
+#define PM_CNTL_MODE 0x10
+
+#define LOONGSON_MAX_VCPUS 16
+
+/*
+ * Loongson-3's virtual machine BIOS can be obtained here:
+ * 1, https://github.com/loongson-community/firmware-nonfree
+ * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin
+ * 3, http://www.anheng.com.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
+ * 4, http://mirrors.ustc.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
+ * 5, http://mirrors.nju.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
+ * 6, https://mirrors.tuna.tsinghua.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
+ * 7, https://mirrors.bfsu.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
+ * 8, https://mirrors.cloud.tencent.com/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
+ */
+#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
+
+#define UART_IRQ 0
+#define RTC_IRQ 1
+#define PCIE_IRQ_BASE 2
+
+const struct MemmapEntry virt_memmap[] = {
+ [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
+ [VIRT_PM] = { 0x10080000, 0x100 },
+ [VIRT_FW_CFG] = { 0x10080100, 0x100 },
+ [VIRT_RTC] = { 0x10081000, 0x1000 },
+ [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
+ [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
+ [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
+ [VIRT_UART] = { 0x1fe001e0, 0x8 },
+ [VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
+ [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
+ [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
+};
+
+static const struct MemmapEntry loader_memmap[] = {
+ [LOADER_KERNEL] = { 0x00000000, 0x4000000 },
+ [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */
+ [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 },
+};
+
+static const struct MemmapEntry loader_rommap[] = {
+ [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 },
+ [LOADER_PARAM] = { 0x1fc01000, 0x10000 },
+};
+
+static struct _loaderparams {
+ uint64_t cpu_freq;
+ uint64_t ram_size;
+ const char *kernel_cmdline;
+ const char *kernel_filename;
+ const char *initrd_filename;
+ uint64_t kernel_entry;
+ uint64_t a0, a1, a2;
+} loaderparams;
+
+static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return 0;
+}
+
+static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+ if (addr != PM_CNTL_MODE) {
+ return;
+ }
+
+ switch (val) {
+ case 0x00:
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
+ case 0xff:
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ return;
+ default:
+ return;
+ }
+}
+
+static const MemoryRegionOps loongson3_pm_ops = {
+ .read = loongson3_pm_read,
+ .write = loongson3_pm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+#define DEF_TCG_FREQ (200 * 1000 * 1000)
+#define DEF_KVM_FREQ (1600 * 1000 * 1000)
+
+static uint64_t get_cpu_freq(void)
+{
+#ifdef CONFIG_KVM
+ int ret;
+ uint64_t freq;
+ struct kvm_one_reg freq_reg = {
+ .id = KVM_REG_MIPS_COUNT_HZ,
+ .addr = (uintptr_t)(&freq)
+ };
+
+ if (kvm_enabled()) {
+ ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
+ if (ret < 0) {
+ return DEF_KVM_FREQ;
+ }
+ return freq * 2;
+ } else {
+ /*
+ * TCG has a default CP0 Timer period 10 ns, which is 100MHz,
+ * CPU frequency is defined as double of CP0 timer frequency.
+ */
+ return DEF_TCG_FREQ;
+ }
+#else
+ return DEF_TCG_FREQ;
+#endif
+}
+
+static void init_boot_param(void)
+{
+ void *p;
+ struct boot_params *bp;
+
+ p = g_malloc0(loader_rommap[LOADER_PARAM].size);
+ bp = p;
+
+ stw_le_p(&bp->efi.smbios.vers, 1);
+ init_reset_system(&(bp->reset_system));
+ p += ROUND_UP(sizeof(struct boot_params), 64);
+ init_loongson_params(&(bp->efi.smbios.lp), p,
+ loaderparams.cpu_freq, loaderparams.ram_size);
+
+ rom_add_blob_fixed("params_rom", bp,
+ loader_rommap[LOADER_PARAM].size,
+ loader_rommap[LOADER_PARAM].base);
+
+ g_free(bp);
+
+ loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, loader_rommap[LOADER_PARAM].base);
+}
+
+static void init_boot_rom(void)
+{
+ const unsigned int boot_code[] = {
+ 0x40086000, /* mfc0 t0, CP0_STATUS */
+ 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */
+ 0x01094025, /* or t0, t0, t1 */
+ 0x3C090040, /* lui t1, 0x40 #set bev */
+ 0x01094025, /* or t0, t0, t1 */
+ 0x40886000, /* mtc0 t0, CP0_STATUS */
+ 0x00000000,
+ 0x40806800, /* mtc0 zero, CP0_CAUSE */
+ 0x00000000,
+ 0x400A7801, /* mfc0 t2, $15, 1 */
+ 0x314A00FF, /* andi t2, 0x0ff */
+ 0x3C089000, /* dli t0, 0x900000003ff01000 */
+ 0x00084438,
+ 0x35083FF0,
+ 0x00084438,
+ 0x35081000,
+ 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */
+ 0x000B5A00, /* sll t3, 8 */
+ 0x010B4025, /* or t0, t0, t3 */
+ 0x314C000C, /* andi t4, t2, 0xc #node id */
+ 0x000C62BC, /* dsll t4, 42 */
+ 0x010C4025, /* or t0, t0, t4 */
+ /* WaitForInit: */
+ 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */
+ 0x1040FFFE, /* beqz v0, WaitForInit */
+ 0x00000000, /* nop */
+ 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */
+ 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */
+ 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */
+ 0x00400008, /* jr v0 #byebye */
+ 0x00000000, /* nop */
+ 0x1000FFFF, /* 1: b 1b */
+ 0x00000000, /* nop */
+
+ /* Reset */
+ 0x3C0C9000, /* dli t0, 0x9000000010080010 */
+ 0x358C0000,
+ 0x000C6438,
+ 0x358C1008,
+ 0x000C6438,
+ 0x358C0010,
+ 0x240D0000, /* li t1, 0x00 */
+ 0xA18D0000, /* sb t1, (t0) */
+ 0x1000FFFF, /* 1: b 1b */
+ 0x00000000, /* nop */
+
+ /* Shutdown */
+ 0x3C0C9000, /* dli t0, 0x9000000010080010 */
+ 0x358C0000,
+ 0x000C6438,
+ 0x358C1008,
+ 0x000C6438,
+ 0x358C0010,
+ 0x240D00FF, /* li t1, 0xff */
+ 0xA18D0000, /* sb t1, (t0) */
+ 0x1000FFFF, /* 1: b 1b */
+ 0x00000000 /* nop */
+ };
+
+ rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
+ loader_rommap[LOADER_BOOTROM].base);
+}
+
+static void fw_cfg_boot_set(void *opaque, const char *boot_device,
+ Error **errp)
+{
+ fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
+}
+
+static void fw_conf_init(unsigned long ram_size)
+{
+ FWCfgState *fw_cfg;
+ hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
+
+ fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq());
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
+}
+
+static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
+{
+ hwaddr cmdline_vaddr;
+ char memenv[32];
+ char highmemenv[32];
+ void *cmdline_buf;
+ unsigned int *parg_env;
+ int ret = 0;
+
+ /* Allocate cmdline_buf for command line. */
+ cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
+ cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
+ loader_memmap[LOADER_CMDLINE].base);
+
+ /*
+ * Layout of cmdline_buf looks like this:
+ * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
+ * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
+ */
+ parg_env = (void *)cmdline_buf;
+
+ ret = (3 + 1) * 4;
+ *parg_env++ = cmdline_vaddr + ret;
+ ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
+
+ /* argv1 */
+ *parg_env++ = cmdline_vaddr + ret;
+ if (initrd_size > 0)
+ ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
+ "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
+ cpu_mips_phys_to_kseg0(NULL, initrd_offset),
+ initrd_size, loaderparams.kernel_cmdline));
+ else
+ ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
+ loaderparams.kernel_cmdline));
+
+ /* argv2 */
+ *parg_env++ = cmdline_vaddr + 4 * ret;
+
+ /* env */
+ sprintf(memenv, "%d", 256);
+ sprintf(highmemenv, "%ld", (unsigned long)(loaderparams.ram_size / MiB) - 256);
+
+ rom_add_blob_fixed("cmdline", cmdline_buf,
+ loader_memmap[LOADER_CMDLINE].size,
+ loader_memmap[LOADER_CMDLINE].base);
+
+ g_free(cmdline_buf);
+
+ loaderparams.a0 = 2;
+ loaderparams.a1 = cmdline_vaddr;
+
+ return 0;
+}
+
+static uint64_t load_kernel(CPUMIPSState *env)
+{
+ long kernel_size;
+ ram_addr_t initrd_offset;
+ uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
+
+ kernel_size = load_elf(loaderparams.kernel_filename, NULL,
+ cpu_mips_kseg0_to_phys, NULL,
+ (uint64_t *)&kernel_entry,
+ (uint64_t *)&kernel_low, (uint64_t *)&kernel_high,
+ NULL, 0, EM_MIPS, 1, 0);
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s': %s",
+ loaderparams.kernel_filename,
+ load_elf_strerror(kernel_size));
+ exit(1);
+ }
+
+ /* load initrd */
+ initrd_size = 0;
+ initrd_offset = 0;
+ if (loaderparams.initrd_filename) {
+ initrd_size = get_image_size(loaderparams.initrd_filename);
+ if (initrd_size > 0) {
+ initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
+ INITRD_PAGE_MASK;
+ initrd_offset = MAX(initrd_offset,
+ loader_memmap[LOADER_INITRD].base);
+
+ if (initrd_offset + initrd_size > ram_size) {
+ error_report("memory too small for initial ram disk '%s'",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+
+ initrd_size = load_image_targphys(loaderparams.initrd_filename,
+ initrd_offset,
+ ram_size - initrd_offset);
+ }
+
+ if (initrd_size == (target_ulong) -1) {
+ error_report("could not load initial ram disk '%s'",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+ }
+
+ /* Setup prom cmdline. */
+ set_prom_cmdline(initrd_offset, initrd_size);
+
+ return kernel_entry;
+}
+
+static void main_cpu_reset(void *opaque)
+{
+ MIPSCPU *cpu = opaque;
+ CPUMIPSState *env = &cpu->env;
+
+ cpu_reset(CPU(cpu));
+
+ /* Loongson-3 reset stuff */
+ if (loaderparams.kernel_filename) {
+ if (cpu == MIPS_CPU(first_cpu)) {
+ env->active_tc.gpr[4] = loaderparams.a0;
+ env->active_tc.gpr[5] = loaderparams.a1;
+ env->active_tc.gpr[6] = loaderparams.a2;
+ env->active_tc.PC = loaderparams.kernel_entry;
+ }
+ env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
+ }
+}
+
+static inline void loongson3_virt_devices_init(MachineState *machine, DeviceState *pic)
+{
+ int i;
+ qemu_irq irq;
+ PCIBus *pci_bus;
+ DeviceState *dev;
+ MemoryRegion *pio_alias;
+ MemoryRegion *mmio_alias, *mmio_reg;
+ MemoryRegion *ecam_alias, *ecam_reg;
+
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+ ecam_alias = g_new0(MemoryRegion, 1);
+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
+ ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
+ memory_region_add_subregion(get_system_memory(),
+ virt_memmap[VIRT_PCIE_ECAM].base, ecam_alias);
+
+ mmio_alias = g_new0(MemoryRegion, 1);
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
+ mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
+ virt_memmap[VIRT_PCIE_MMIO].size);
+ memory_region_add_subregion(get_system_memory(),
+ virt_memmap[VIRT_PCIE_MMIO].base, mmio_alias);
+
+ pio_alias = g_new0(MemoryRegion, 1);
+ memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
+ get_system_io(), 0, virt_memmap[VIRT_PCIE_PIO].size);
+ memory_region_add_subregion(get_system_memory(),
+ virt_memmap[VIRT_PCIE_PIO].base, pio_alias);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
+
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
+ gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
+ }
+
+ pci_vga_init(pci_bus);
+
+ if (defaults_enabled()) {
+ pci_create_simple(pci_bus, -1, "pci-ohci");
+ usb_create_simple(usb_bus_find(-1), "usb-kbd");
+ usb_create_simple(usb_bus_find(-1), "usb-tablet");
+ }
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
+}
+
+static void mips_loongson3_virt_init(MachineState *machine)
+{
+ int i;
+ long bios_size;
+ MIPSCPU *cpu;
+ CPUMIPSState *env;
+ DeviceState *liointc;
+ char *filename;
+ const char *kernel_cmdline = machine->kernel_cmdline;
+ const char *kernel_filename = machine->kernel_filename;
+ const char *initrd_filename = machine->initrd_filename;
+ ram_addr_t ram_size = machine->ram_size;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
+
+ /* TODO: TCG will support all CPU types */
+ if (!kvm_enabled()) {
+ if (!machine->cpu_type) {
+ machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
+ }
+ if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
+ error_report("Loongson-3/TCG needs cpu type Loongson-3A1000");
+ exit(1);
+ }
+ } else {
+ if (!machine->cpu_type) {
+ machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
+ }
+ if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
+ error_report("Loongson-3/KVM needs cpu type Loongson-3A4000");
+ exit(1);
+ }
+ }
+
+ if (ram_size < 512 * MiB) {
+ error_report("Loongson-3 machine needs at least 512MB memory");
+ exit(1);
+ }
+
+ /*
+ * The whole MMIO range among configure registers doesn't generate
+ * exception when accessing invalid memory. Create some unimplememted
+ * devices to emulate this feature.
+ */
+ create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB);
+ create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB);
+
+ liointc = qdev_new("loongson.liointc");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
+
+ serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
+ qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0),
+ DEVICE_NATIVE_ENDIAN);
+
+ sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
+ qdev_get_gpio_in(liointc, RTC_IRQ));
+
+ for (i = 0; i < machine->smp.cpus; i++) {
+ int ip;
+
+ /* init CPUs */
+ cpu = MIPS_CPU(cpu_create(machine->cpu_type));
+
+ /* Init internal devices */
+ cpu_mips_irq_init_cpu(cpu);
+ cpu_mips_clock_init(cpu);
+ qemu_register_reset(main_cpu_reset, cpu);
+
+ if (i >= 4) {
+ continue; /* Only node-0 can be connected to LIOINTC */
+ }
+
+ for (ip = 0; ip < 4 ; ip++) {
+ int pin = i * 4 + ip;
+ sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
+ pin, cpu->env.irq[ip + 2]);
+ }
+ }
+ env = &MIPS_CPU(first_cpu)->env;
+
+ /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
+ memory_region_init_rom(bios, NULL, "loongson3.bios",
+ virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
+ memory_region_init_alias(ram, NULL, "loongson3.lowmem",
+ machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
+ memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
+ NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
+
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_LOWMEM].base, ram);
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_BIOS_ROM].base, bios);
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_HIGHMEM].base, machine->ram);
+ memory_region_add_subregion(address_space_mem,
+ virt_memmap[VIRT_PM].base, iomem);
+
+ /*
+ * We do not support flash operation, just loading bios.bin as raw BIOS.
+ * Please use -L to set the BIOS path and -bios to set bios name.
+ */
+
+ if (kernel_filename) {
+ loaderparams.cpu_freq = get_cpu_freq();
+ loaderparams.ram_size = ram_size;
+ loaderparams.kernel_filename = kernel_filename;
+ loaderparams.kernel_cmdline = kernel_cmdline;
+ loaderparams.initrd_filename = initrd_filename;
+ loaderparams.kernel_entry = load_kernel(env);
+
+ init_boot_rom();
+ init_boot_param();
+ } else {
+ if (bios_name == NULL) {
+ bios_name = LOONGSON3_BIOSNAME;
+ }
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ bios_size = load_image_targphys(filename,
+ virt_memmap[VIRT_BIOS_ROM].base,
+ virt_memmap[VIRT_BIOS_ROM].size);
+ g_free(filename);
+ } else {
+ bios_size = -1;
+ }
+
+ if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
+ !kernel_filename && !qtest_enabled()) {
+ error_report("Could not load MIPS bios '%s'", bios_name);
+ exit(1);
+ }
+
+ fw_conf_init(ram_size);
+ }
+
+ msi_nonbroken = true;
+ loongson3_virt_devices_init(machine, liointc);
+}
+
+static void mips_loongson3_virt_machine_init(MachineClass *mc)
+{
+ mc->desc = "Loongson-3 Virtualization Platform";
+ mc->init = mips_loongson3_virt_init;
+ mc->block_default_type = IF_IDE;
+ mc->max_cpus = LOONGSON_MAX_VCPUS;
+ mc->default_ram_id = "loongson3.highram";
+ mc->default_ram_size = 1600 * MiB;
+ mc->kvm_type = mips_kvm_type;
+ mc->minimum_page_bits = 14;
+}
+
+DEFINE_MACHINE("loongson3-virt", mips_loongson3_virt_machine_init)
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index 802e5e4a1d..72db43c488 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,7 +1,7 @@
mips_ss = ss.source_set()
mips_ss.add(files('addr.c', 'mips_int.c', 'fw_cfg.c'))
mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
-mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c'))
+mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c'))
mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH V14 7/8] hw/mips: Add Loongson-3 machine support
2020-10-16 6:51 ` [PATCH V14 7/8] hw/mips: Add Loongson-3 machine support Huacai Chen
@ 2020-10-17 15:58 ` Philippe Mathieu-Daudé
2020-10-20 8:05 ` Huacai Chen
0 siblings, 1 reply; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-17 15:58 UTC (permalink / raw)
To: Huacai Chen, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Paolo Bonzini,
Huacai Chen, Aurelien Jarno
On 10/16/20 8:51 AM, Huacai Chen wrote:
> Add Loongson-3 based machine support, it use liointc as the interrupt
> controler and use GPEX as the pci controller. Currently it can work with
> both TCG and KVM.
>
> As the machine model is not based on any exiting physical hardware, the
> name of the machine is "loongson3-virt". It may be superseded in future
> by a real machine model. If this happens, then a regular deprecation
> procedure shall occur for "loongson3-virt" machine.
>
> We now already have a full functional Linux kernel (based on Linux-5.4.x
> LTS, the kvm host side and guest side have both been upstream for Linux-
> 5.9, but Linux-5.9 has not been released yet) here:
>
> https://github.com/chenhuacai/linux
>
> Of course the upstream kernel is also usable (though it is "unstable"
> now):
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
>
> How to use QEMU/Loongson-3?
> 1, Download kernel source from the above URL;
> 2, Build a kernel with arch/mips/configs/loongson3_defconfig;
> 3, Boot a Loongson-3A4000 host with this kernel (for KVM mode);
> 4, Build QEMU-master with this patchset;
> 5, modprobe kvm (only necessary for KVM mode);
> 6, Use QEMU with TCG:
> qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ...
> Use QEMU with KVM:
> qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ...
>
> The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> default-configs/devices/mips64el-softmmu.mak | 1 +
> hw/mips/Kconfig | 12 +
> hw/mips/loongson3_virt.c | 615 +++++++++++++++++++
> hw/mips/meson.build | 2 +-
> 4 files changed, 629 insertions(+), 1 deletion(-)
> create mode 100644 hw/mips/loongson3_virt.c
>
> diff --git a/default-configs/devices/mips64el-softmmu.mak b/default-configs/devices/mips64el-softmmu.mak
> index 9f8a3ef156..26c660a05c 100644
> --- a/default-configs/devices/mips64el-softmmu.mak
> +++ b/default-configs/devices/mips64el-softmmu.mak
> @@ -3,6 +3,7 @@
> include mips-softmmu-common.mak
> CONFIG_IDE_VIA=y
> CONFIG_FULOONG=y
> +CONFIG_LOONGSON3V=y
> CONFIG_ATI_VGA=y
> CONFIG_RTL8139_PCI=y
> CONFIG_JAZZ=y
> diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
> index 67d39c56a4..6562b346ab 100644
> --- a/hw/mips/Kconfig
> +++ b/hw/mips/Kconfig
> @@ -45,6 +45,18 @@ config FULOONG
> bool
> select PCI_BONITO
>
> +config LOONGSON3V
> + bool
> + select PCKBD
> + select SERIAL
> + select GOLDFISH_RTC
> + select LOONGSON_LIOINTC
> + select PCI_DEVICES
> + select PCI_EXPRESS_GENERIC_BRIDGE
> + select VIRTIO_VGA
> + select QXL if SPICE
> + select MSI_NONBROKEN
> +
> config MIPS_CPS
> bool
> select PTIMER
> diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
> new file mode 100644
> index 0000000000..c298a16793
> --- /dev/null
> +++ b/hw/mips/loongson3_virt.c
> @@ -0,0 +1,627 @@
> +/*
> + * Generic Loongson-3 Platform support
> + *
> + * Copyright (c) 2017-2020 Huacai Chen (chenhc@lemote.com)
> + * Copyright (c) 2017-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> + */
> +
> +/*
> + * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
> + * extensions, 800~2000MHz)
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "qemu/units.h"
> +#include "qemu/cutils.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "elf.h"
> +#include "kvm_mips.h"
> +#include "hw/boards.h"
> +#include "hw/char/serial.h"
> +#include "hw/mips/mips.h"
> +#include "hw/mips/cpudevs.h"
> +#include "hw/mips/fw_cfg.h"
> +#include "hw/mips/loongson3_bootp.h"
> +#include "hw/misc/unimp.h"
> +#include "hw/intc/i8259.h"
> +#include "hw/loader.h"
> +#include "hw/isa/superio.h"
> +#include "hw/pci/msi.h"
> +#include "hw/pci/pci.h"
> +#include "hw/pci/pci_host.h"
> +#include "hw/pci-host/gpex.h"
> +#include "hw/rtc/mc146818rtc.h"
> +#include "hw/usb.h"
> +#include "net/net.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/kvm.h"
> +#include "sysemu/qtest.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
> +#include "qemu/log.h"
> +#include "qemu/error-report.h"
> +
> +#define PM_CNTL_MODE 0x10
> +
> +#define LOONGSON_MAX_VCPUS 16
> +
> +/*
> + * Loongson-3's virtual machine BIOS can be obtained here:
> + * 1, https://github.com/loongson-community/firmware-nonfree
> + * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin
I'd simply list #2, as it seems the official.
The BIOS is extremly slow (eating 100% of a core) when trying
to list the devices:
Shell> devices
T D
Y C I
P F A
CTRL E G G #P #D #C Device Name
==== = = = == == ===
=========================================================
[50sec here]
23 R - - 0 1 1
VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)
30 R - - 0 1 4 PciRoot(0x0)
36 D - - 1 0 0 Primary Console Input Device
37 D - - 2 0 0 Primary Console Output Device
38 D - - 1 0 0 Primary Standard Error Device
66 D - - 1 0 0 PciRoot(0x0)/Pci(0x0,0x0)
67 B - - 1 1 1 QEMU Video PCI Adapter
68 D - - 1 2 0 Usb Universal Host Controller
69 B - - 1 2 1 Virtio Network Device
Is that a known issue?
> + * 3, http://www.anheng.com.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> + * 4, http://mirrors.ustc.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> + * 5, http://mirrors.nju.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> + * 6, https://mirrors.tuna.tsinghua.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> + * 7, https://mirrors.bfsu.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> + * 8, https://mirrors.cloud.tencent.com/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> + */
> +#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
> +
> +#define UART_IRQ 0
> +#define RTC_IRQ 1
> +#define PCIE_IRQ_BASE 2
> +
> +const struct MemmapEntry virt_memmap[] = {
> + [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
> + [VIRT_PM] = { 0x10080000, 0x100 },
> + [VIRT_FW_CFG] = { 0x10080100, 0x100 },
> + [VIRT_RTC] = { 0x10081000, 0x1000 },
> + [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
> + [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
> + [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
> + [VIRT_UART] = { 0x1fe001e0, 0x8 },
> + [VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
> + [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
> + [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
> +};
> +
> +static const struct MemmapEntry loader_memmap[] = {
> + [LOADER_KERNEL] = { 0x00000000, 0x4000000 },
> + [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */
> + [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 },
> +};
> +
> +static const struct MemmapEntry loader_rommap[] = {
> + [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 },
> + [LOADER_PARAM] = { 0x1fc01000, 0x10000 },
> +};
> +
> +static struct _loaderparams {
> + uint64_t cpu_freq;
> + uint64_t ram_size;
> + const char *kernel_cmdline;
> + const char *kernel_filename;
> + const char *initrd_filename;
> + uint64_t kernel_entry;
> + uint64_t a0, a1, a2;
> +} loaderparams;
> +
> +static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + return 0;
> +}
> +
> +static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
> +{
> + if (addr != PM_CNTL_MODE) {
> + return;
> + }
> +
> + switch (val) {
> + case 0x00:
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + return;
> + case 0xff:
> + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
> + return;
> + default:
> + return;
> + }
> +}
> +
> +static const MemoryRegionOps loongson3_pm_ops = {
> + .read = loongson3_pm_read,
> + .write = loongson3_pm_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +#define DEF_TCG_FREQ (200 * 1000 * 1000)
> +#define DEF_KVM_FREQ (1600 * 1000 * 1000)
> +
> +static uint64_t get_cpu_freq(void)
Please rename get_cpu_freq_hz().
> +{
> +#ifdef CONFIG_KVM
> + int ret;
> + uint64_t freq;
> + struct kvm_one_reg freq_reg = {
> + .id = KVM_REG_MIPS_COUNT_HZ,
> + .addr = (uintptr_t)(&freq)
> + };
> +
> + if (kvm_enabled()) {
This is not working as expected... as this returns TRUE
using TCG on x86.
> + ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
> + if (ret < 0) {
> + return DEF_KVM_FREQ;
> + }
> + return freq * 2;
> + } else {
> + /*
> + * TCG has a default CP0 Timer period 10 ns, which is 100MHz,
> + * CPU frequency is defined as double of CP0 timer frequency.
> + */
> + return DEF_TCG_FREQ;
> + }
> +#else
> + return DEF_TCG_FREQ;
> +#endif
> +}
> +
> +static void init_boot_param(void)
> +{
> + void *p;
> + struct boot_params *bp;
> +
> + p = g_malloc0(loader_rommap[LOADER_PARAM].size);
> + bp = p;
> +
> + stw_le_p(&bp->efi.smbios.vers, 1);
> + init_reset_system(&(bp->reset_system));
> + p += ROUND_UP(sizeof(struct boot_params), 64);
> + init_loongson_params(&(bp->efi.smbios.lp), p,
> + loaderparams.cpu_freq, loaderparams.ram_size);
> +
> + rom_add_blob_fixed("params_rom", bp,
> + loader_rommap[LOADER_PARAM].size,
> + loader_rommap[LOADER_PARAM].base);
> +
> + g_free(bp);
> +
> + loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, loader_rommap[LOADER_PARAM].base);
> +}
> +
> +static void init_boot_rom(void)
> +{
> + const unsigned int boot_code[] = {
> + 0x40086000, /* mfc0 t0, CP0_STATUS */
> + 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */
> + 0x01094025, /* or t0, t0, t1 */
> + 0x3C090040, /* lui t1, 0x40 #set bev */
> + 0x01094025, /* or t0, t0, t1 */
> + 0x40886000, /* mtc0 t0, CP0_STATUS */
> + 0x00000000,
> + 0x40806800, /* mtc0 zero, CP0_CAUSE */
> + 0x00000000,
> + 0x400A7801, /* mfc0 t2, $15, 1 */
> + 0x314A00FF, /* andi t2, 0x0ff */
> + 0x3C089000, /* dli t0, 0x900000003ff01000 */
> + 0x00084438,
> + 0x35083FF0,
> + 0x00084438,
> + 0x35081000,
> + 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */
> + 0x000B5A00, /* sll t3, 8 */
> + 0x010B4025, /* or t0, t0, t3 */
> + 0x314C000C, /* andi t4, t2, 0xc #node id */
> + 0x000C62BC, /* dsll t4, 42 */
> + 0x010C4025, /* or t0, t0, t4 */
> + /* WaitForInit: */
> + 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */
> + 0x1040FFFE, /* beqz v0, WaitForInit */
> + 0x00000000, /* nop */
> + 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */
> + 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */
> + 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */
> + 0x00400008, /* jr v0 #byebye */
> + 0x00000000, /* nop */
> + 0x1000FFFF, /* 1: b 1b */
> + 0x00000000, /* nop */
> +
> + /* Reset */
> + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> + 0x358C0000,
> + 0x000C6438,
> + 0x358C1008,
> + 0x000C6438,
> + 0x358C0010,
> + 0x240D0000, /* li t1, 0x00 */
> + 0xA18D0000, /* sb t1, (t0) */
> + 0x1000FFFF, /* 1: b 1b */
> + 0x00000000, /* nop */
> +
> + /* Shutdown */
> + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> + 0x358C0000,
> + 0x000C6438,
> + 0x358C1008,
> + 0x000C6438,
> + 0x358C0010,
> + 0x240D00FF, /* li t1, 0xff */
> + 0xA18D0000, /* sb t1, (t0) */
> + 0x1000FFFF, /* 1: b 1b */
> + 0x00000000 /* nop */
> + };
> +
> + rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
> + loader_rommap[LOADER_BOOTROM].base);
> +}
> +
> +static void fw_cfg_boot_set(void *opaque, const char *boot_device,
> + Error **errp)
> +{
> + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
> +}
> +
> +static void fw_conf_init(unsigned long ram_size)
> +{
> + FWCfgState *fw_cfg;
> + hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
> +
> + fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
> + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> + fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
> + fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq());
> + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> +}
> +
> +static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
> +{
> + hwaddr cmdline_vaddr;
> + char memenv[32];
> + char highmemenv[32];
> + void *cmdline_buf;
> + unsigned int *parg_env;
> + int ret = 0;
> +
> + /* Allocate cmdline_buf for command line. */
> + cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
> + cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
> + loader_memmap[LOADER_CMDLINE].base);
> +
> + /*
> + * Layout of cmdline_buf looks like this:
> + * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
> + * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
> + */
> + parg_env = (void *)cmdline_buf;
> +
> + ret = (3 + 1) * 4;
> + *parg_env++ = cmdline_vaddr + ret;
> + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
> +
> + /* argv1 */
> + *parg_env++ = cmdline_vaddr + ret;
> + if (initrd_size > 0)
> + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
> + "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
> + cpu_mips_phys_to_kseg0(NULL, initrd_offset),
> + initrd_size, loaderparams.kernel_cmdline));
> + else
> + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
> + loaderparams.kernel_cmdline));
> +
> + /* argv2 */
> + *parg_env++ = cmdline_vaddr + 4 * ret;
> +
> + /* env */
> + sprintf(memenv, "%d", 256);
> + sprintf(highmemenv, "%ld", (unsigned long)(loaderparams.ram_size / MiB) - 256);
> +
> + rom_add_blob_fixed("cmdline", cmdline_buf,
> + loader_memmap[LOADER_CMDLINE].size,
> + loader_memmap[LOADER_CMDLINE].base);
> +
> + g_free(cmdline_buf);
> +
> + loaderparams.a0 = 2;
> + loaderparams.a1 = cmdline_vaddr;
> +
> + return 0;
> +}
> +
> +static uint64_t load_kernel(CPUMIPSState *env)
> +{
> + long kernel_size;
> + ram_addr_t initrd_offset;
> + uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
> +
> + kernel_size = load_elf(loaderparams.kernel_filename, NULL,
> + cpu_mips_kseg0_to_phys, NULL,
> + (uint64_t *)&kernel_entry,
> + (uint64_t *)&kernel_low, (uint64_t *)&kernel_high,
> + NULL, 0, EM_MIPS, 1, 0);
> + if (kernel_size < 0) {
> + error_report("could not load kernel '%s': %s",
> + loaderparams.kernel_filename,
> + load_elf_strerror(kernel_size));
> + exit(1);
> + }
> +
> + /* load initrd */
> + initrd_size = 0;
> + initrd_offset = 0;
> + if (loaderparams.initrd_filename) {
> + initrd_size = get_image_size(loaderparams.initrd_filename);
> + if (initrd_size > 0) {
> + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
> + INITRD_PAGE_MASK;
> + initrd_offset = MAX(initrd_offset,
> + loader_memmap[LOADER_INITRD].base);
Now you can use directly:
initrd_offset = MAX(ROUND_UP(kernel_high, INITRD_PAGE_SIZE),
loader_memmap[LOADER_INITRD].base);
> +
> + if (initrd_offset + initrd_size > ram_size) {
> + error_report("memory too small for initial ram disk '%s'",
> + loaderparams.initrd_filename);
> + exit(1);
> + }
> +
> + initrd_size = load_image_targphys(loaderparams.initrd_filename,
> + initrd_offset,
> + ram_size - initrd_offset);
> + }
> +
> + if (initrd_size == (target_ulong) -1) {
> + error_report("could not load initial ram disk '%s'",
> + loaderparams.initrd_filename);
> + exit(1);
> + }
> + }
> +
> + /* Setup prom cmdline. */
> + set_prom_cmdline(initrd_offset, initrd_size);
> +
> + return kernel_entry;
> +}
> +
> +static void main_cpu_reset(void *opaque)
> +{
> + MIPSCPU *cpu = opaque;
> + CPUMIPSState *env = &cpu->env;
> +
> + cpu_reset(CPU(cpu));
> +
> + /* Loongson-3 reset stuff */
> + if (loaderparams.kernel_filename) {
> + if (cpu == MIPS_CPU(first_cpu)) {
> + env->active_tc.gpr[4] = loaderparams.a0;
> + env->active_tc.gpr[5] = loaderparams.a1;
> + env->active_tc.gpr[6] = loaderparams.a2;
> + env->active_tc.PC = loaderparams.kernel_entry;
> + }
> + env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
> + }
> +}
> +
> +static inline void loongson3_virt_devices_init(MachineState *machine, DeviceState *pic)
> +{
> + int i;
> + qemu_irq irq;
> + PCIBus *pci_bus;
> + DeviceState *dev;
> + MemoryRegion *pio_alias;
> + MemoryRegion *mmio_alias, *mmio_reg;
> + MemoryRegion *ecam_alias, *ecam_reg;
> +
> + dev = qdev_new(TYPE_GPEX_HOST);
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> + pci_bus = PCI_HOST_BRIDGE(dev)->bus;
> +
> + ecam_alias = g_new0(MemoryRegion, 1);
> + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
> + ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
> + memory_region_add_subregion(get_system_memory(),
> + virt_memmap[VIRT_PCIE_ECAM].base, ecam_alias);
> +
> + mmio_alias = g_new0(MemoryRegion, 1);
> + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
> + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
> + mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
> + virt_memmap[VIRT_PCIE_MMIO].size);
> + memory_region_add_subregion(get_system_memory(),
> + virt_memmap[VIRT_PCIE_MMIO].base, mmio_alias);
> +
> + pio_alias = g_new0(MemoryRegion, 1);
> + memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
> + get_system_io(), 0, virt_memmap[VIRT_PCIE_PIO].size);
> + memory_region_add_subregion(get_system_memory(),
> + virt_memmap[VIRT_PCIE_PIO].base, pio_alias);
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
> +
> + for (i = 0; i < GPEX_NUM_IRQS; i++) {
> + irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
> + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
> + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
> + }
> +
> + pci_vga_init(pci_bus);
> +
> + if (defaults_enabled()) {
> + pci_create_simple(pci_bus, -1, "pci-ohci");
> + usb_create_simple(usb_bus_find(-1), "usb-kbd");
> + usb_create_simple(usb_bus_find(-1), "usb-tablet");
> + }
> +
> + for (i = 0; i < nb_nics; i++) {
> + NICInfo *nd = &nd_table[i];
> +
> + if (!nd->model) {
> + nd->model = g_strdup("virtio");
> + }
> +
> + pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
> + }
> +}
> +
> +static void mips_loongson3_virt_init(MachineState *machine)
> +{
> + int i;
> + long bios_size;
> + MIPSCPU *cpu;
> + CPUMIPSState *env;
> + DeviceState *liointc;
> + char *filename;
> + const char *kernel_cmdline = machine->kernel_cmdline;
> + const char *kernel_filename = machine->kernel_filename;
> + const char *initrd_filename = machine->initrd_filename;
> + ram_addr_t ram_size = machine->ram_size;
> + MemoryRegion *address_space_mem = get_system_memory();
> + MemoryRegion *ram = g_new(MemoryRegion, 1);
> + MemoryRegion *bios = g_new(MemoryRegion, 1);
> + MemoryRegion *iomem = g_new(MemoryRegion, 1);
> +
> + /* TODO: TCG will support all CPU types */
> + if (!kvm_enabled()) {
> + if (!machine->cpu_type) {
> + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
> + }
> + if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
> + error_report("Loongson-3/TCG needs cpu type Loongson-3A1000");
> + exit(1);
> + }
> + } else {
> + if (!machine->cpu_type) {
> + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
> + }
> + if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
> + error_report("Loongson-3/KVM needs cpu type Loongson-3A4000");
> + exit(1);
> + }
> + }
> +
> + if (ram_size < 512 * MiB) {
> + error_report("Loongson-3 machine needs at least 512MB memory");
> + exit(1);
> + }
> +
> + /*
> + * The whole MMIO range among configure registers doesn't generate
> + * exception when accessing invalid memory. Create some unimplememted
> + * devices to emulate this feature.
> + */
> + create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB);
> + create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB);
The problem using large container to ignore accesses is we have
no idea what the firmware is trying to do:
mmio fallback 1: unimplemented device write (size 8, offset 0xff01038,
value 0x980000000e3d1000)
mmio fallback 1: unimplemented device write (size 8, offset 0xff01020,
value 0x980000000e720ef8)
> +
> + liointc = qdev_new("loongson.liointc");
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
> +
> + serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
> + qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0),
> + DEVICE_NATIVE_ENDIAN);
> +
> + sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
> + qdev_get_gpio_in(liointc, RTC_IRQ));
> +
> + for (i = 0; i < machine->smp.cpus; i++) {
> + int ip;
> +
> + /* init CPUs */
> + cpu = MIPS_CPU(cpu_create(machine->cpu_type));
> +
> + /* Init internal devices */
> + cpu_mips_irq_init_cpu(cpu);
> + cpu_mips_clock_init(cpu);
> + qemu_register_reset(main_cpu_reset, cpu);
> +
> + if (i >= 4) {
> + continue; /* Only node-0 can be connected to LIOINTC */
> + }
> +
> + for (ip = 0; ip < 4 ; ip++) {
> + int pin = i * 4 + ip;
> + sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
> + pin, cpu->env.irq[ip + 2]);
> + }
> + }
> + env = &MIPS_CPU(first_cpu)->env;
> +
> + /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
> + memory_region_init_rom(bios, NULL, "loongson3.bios",
> + virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
> + memory_region_init_alias(ram, NULL, "loongson3.lowmem",
> + machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
> + memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
> + NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
> +
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_LOWMEM].base, ram);
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_BIOS_ROM].base, bios);
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_HIGHMEM].base, machine->ram);
> + memory_region_add_subregion(address_space_mem,
> + virt_memmap[VIRT_PM].base, iomem);
> +
> + /*
> + * We do not support flash operation, just loading bios.bin as raw BIOS.
> + * Please use -L to set the BIOS path and -bios to set bios name.
> + */
> +
> + if (kernel_filename) {
> + loaderparams.cpu_freq = get_cpu_freq();
> + loaderparams.ram_size = ram_size;
> + loaderparams.kernel_filename = kernel_filename;
> + loaderparams.kernel_cmdline = kernel_cmdline;
> + loaderparams.initrd_filename = initrd_filename;
> + loaderparams.kernel_entry = load_kernel(env);
> +
> + init_boot_rom();
> + init_boot_param();
> + } else {
> + if (bios_name == NULL) {
> + bios_name = LOONGSON3_BIOSNAME;
> + }
> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> + if (filename) {
> + bios_size = load_image_targphys(filename,
> + virt_memmap[VIRT_BIOS_ROM].base,
> + virt_memmap[VIRT_BIOS_ROM].size);
> + g_free(filename);
> + } else {
> + bios_size = -1;
> + }
> +
> + if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
> + !kernel_filename && !qtest_enabled()) {
> + error_report("Could not load MIPS bios '%s'", bios_name);
> + exit(1);
> + }
> +
> + fw_conf_init(ram_size);
> + }
> +
> + msi_nonbroken = true;
> + loongson3_virt_devices_init(machine, liointc);
> +}
> +
> +static void mips_loongson3_virt_machine_init(MachineClass *mc)
> +{
> + mc->desc = "Loongson-3 Virtualization Platform";
> + mc->init = mips_loongson3_virt_init;
> + mc->block_default_type = IF_IDE;
> + mc->max_cpus = LOONGSON_MAX_VCPUS;
> + mc->default_ram_id = "loongson3.highram";
> + mc->default_ram_size = 1600 * MiB;
> + mc->kvm_type = mips_kvm_type;
> + mc->minimum_page_bits = 14;
> +}
I tested on top of mips-next using:
-- >8 --
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 6a42808015d..2f1fa2e72ea 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -31,6 +31,7 @@
#include "cpu.h"
#include "elf.h"
#include "kvm_mips.h"
+#include "hw/clock.h"
#include "hw/boards.h"
#include "hw/char/serial.h"
#include "hw/mips/mips.h"
@@ -141,9 +142,6 @@ static const MemoryRegionOps loongson3_pm_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-#define DEF_TCG_FREQ (200 * 1000 * 1000)
-#define DEF_KVM_FREQ (1600 * 1000 * 1000)
-
static uint64_t get_cpu_freq(void)
{
#ifdef CONFIG_KVM
@@ -156,20 +154,12 @@ static uint64_t get_cpu_freq(void)
if (kvm_enabled()) {
ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
- if (ret < 0) {
- return DEF_KVM_FREQ;
+ if (ret >= 0) {
+ return freq * 2;
}
- return freq * 2;
- } else {
- /*
- * TCG has a default CP0 Timer period 10 ns, which is 100MHz,
- * CPU frequency is defined as double of CP0 timer frequency.
- */
- return DEF_TCG_FREQ;
}
-#else
- return DEF_TCG_FREQ;
#endif
+ return 1600 * 1000 * 1000;
}
static void init_boot_param(void)
@@ -471,6 +461,7 @@ static void mips_loongson3_virt_init(MachineState
*machine)
{
int i;
long bios_size;
+ Clock *cpuclk;
MIPSCPU *cpu;
CPUMIPSState *env;
DeviceState *liointc;
@@ -528,11 +519,14 @@ static void mips_loongson3_virt_init(MachineState
*machine)
sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
qdev_get_gpio_in(liointc, RTC_IRQ));
+ cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
+ clock_set_hz(cpuclk, get_cpu_freq());
+
for (i = 0; i < machine->smp.cpus; i++) {
int ip;
/* init CPUs */
- cpu = MIPS_CPU(cpu_create(machine->cpu_type));
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
---
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH V14 7/8] hw/mips: Add Loongson-3 machine support
2020-10-17 15:58 ` Philippe Mathieu-Daudé
@ 2020-10-20 8:05 ` Huacai Chen
0 siblings, 0 replies; 20+ messages in thread
From: Huacai Chen @ 2020-10-20 8:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Huacai Chen, Aleksandar Rikalo, QEMU Developers,
Aleksandar Markovic, Paolo Bonzini, Aurelien Jarno
Hi, Philippe,
On Sat, Oct 17, 2020 at 11:58 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/16/20 8:51 AM, Huacai Chen wrote:
> > Add Loongson-3 based machine support, it use liointc as the interrupt
> > controler and use GPEX as the pci controller. Currently it can work with
> > both TCG and KVM.
> >
> > As the machine model is not based on any exiting physical hardware, the
> > name of the machine is "loongson3-virt". It may be superseded in future
> > by a real machine model. If this happens, then a regular deprecation
> > procedure shall occur for "loongson3-virt" machine.
> >
> > We now already have a full functional Linux kernel (based on Linux-5.4.x
> > LTS, the kvm host side and guest side have both been upstream for Linux-
> > 5.9, but Linux-5.9 has not been released yet) here:
> >
> > https://github.com/chenhuacai/linux
> >
> > Of course the upstream kernel is also usable (though it is "unstable"
> > now):
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> >
> > How to use QEMU/Loongson-3?
> > 1, Download kernel source from the above URL;
> > 2, Build a kernel with arch/mips/configs/loongson3_defconfig;
> > 3, Boot a Loongson-3A4000 host with this kernel (for KVM mode);
> > 4, Build QEMU-master with this patchset;
> > 5, modprobe kvm (only necessary for KVM mode);
> > 6, Use QEMU with TCG:
> > qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ...
> > Use QEMU with KVM:
> > qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ...
> >
> > The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically.
> >
> > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > ---
> > default-configs/devices/mips64el-softmmu.mak | 1 +
> > hw/mips/Kconfig | 12 +
> > hw/mips/loongson3_virt.c | 615 +++++++++++++++++++
> > hw/mips/meson.build | 2 +-
> > 4 files changed, 629 insertions(+), 1 deletion(-)
> > create mode 100644 hw/mips/loongson3_virt.c
> >
> > diff --git a/default-configs/devices/mips64el-softmmu.mak b/default-configs/devices/mips64el-softmmu.mak
> > index 9f8a3ef156..26c660a05c 100644
> > --- a/default-configs/devices/mips64el-softmmu.mak
> > +++ b/default-configs/devices/mips64el-softmmu.mak
> > @@ -3,6 +3,7 @@
> > include mips-softmmu-common.mak
> > CONFIG_IDE_VIA=y
> > CONFIG_FULOONG=y
> > +CONFIG_LOONGSON3V=y
> > CONFIG_ATI_VGA=y
> > CONFIG_RTL8139_PCI=y
> > CONFIG_JAZZ=y
> > diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
> > index 67d39c56a4..6562b346ab 100644
> > --- a/hw/mips/Kconfig
> > +++ b/hw/mips/Kconfig
> > @@ -45,6 +45,18 @@ config FULOONG
> > bool
> > select PCI_BONITO
> >
> > +config LOONGSON3V
> > + bool
> > + select PCKBD
> > + select SERIAL
> > + select GOLDFISH_RTC
> > + select LOONGSON_LIOINTC
> > + select PCI_DEVICES
> > + select PCI_EXPRESS_GENERIC_BRIDGE
> > + select VIRTIO_VGA
> > + select QXL if SPICE
> > + select MSI_NONBROKEN
> > +
> > config MIPS_CPS
> > bool
> > select PTIMER
> > diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
> > new file mode 100644
> > index 0000000000..c298a16793
> > --- /dev/null
> > +++ b/hw/mips/loongson3_virt.c
> > @@ -0,0 +1,627 @@
> > +/*
> > + * Generic Loongson-3 Platform support
> > + *
> > + * Copyright (c) 2017-2020 Huacai Chen (chenhc@lemote.com)
> > + * Copyright (c) 2017-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation, either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program. If not, see <https://www.gnu.org/licenses/>.
> > + */
> > +
> > +/*
> > + * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
> > + * extensions, 800~2000MHz)
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu-common.h"
> > +#include "qemu/units.h"
> > +#include "qemu/cutils.h"
> > +#include "qapi/error.h"
> > +#include "cpu.h"
> > +#include "elf.h"
> > +#include "kvm_mips.h"
> > +#include "hw/boards.h"
> > +#include "hw/char/serial.h"
> > +#include "hw/mips/mips.h"
> > +#include "hw/mips/cpudevs.h"
> > +#include "hw/mips/fw_cfg.h"
> > +#include "hw/mips/loongson3_bootp.h"
> > +#include "hw/misc/unimp.h"
> > +#include "hw/intc/i8259.h"
> > +#include "hw/loader.h"
> > +#include "hw/isa/superio.h"
> > +#include "hw/pci/msi.h"
> > +#include "hw/pci/pci.h"
> > +#include "hw/pci/pci_host.h"
> > +#include "hw/pci-host/gpex.h"
> > +#include "hw/rtc/mc146818rtc.h"
> > +#include "hw/usb.h"
> > +#include "net/net.h"
> > +#include "exec/address-spaces.h"
> > +#include "sysemu/kvm.h"
> > +#include "sysemu/qtest.h"
> > +#include "sysemu/reset.h"
> > +#include "sysemu/runstate.h"
> > +#include "qemu/log.h"
> > +#include "qemu/error-report.h"
> > +
> > +#define PM_CNTL_MODE 0x10
> > +
> > +#define LOONGSON_MAX_VCPUS 16
> > +
> > +/*
> > + * Loongson-3's virtual machine BIOS can be obtained here:
> > + * 1, https://github.com/loongson-community/firmware-nonfree
> > + * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin
>
> I'd simply list #2, as it seems the official.
Hmmm, let me remove all mirrors and list #1, #2. because there may be
some trouble to access #2 if you are not in China.
>
> The BIOS is extremly slow (eating 100% of a core) when trying
> to list the devices:
>
> Shell> devices
> T D
> Y C I
> P F A
> CTRL E G G #P #D #C Device Name
> ==== = = = == == ===
> =========================================================
> [50sec here]
> 23 R - - 0 1 1
> VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)
> 30 R - - 0 1 4 PciRoot(0x0)
> 36 D - - 1 0 0 Primary Console Input Device
> 37 D - - 2 0 0 Primary Console Output Device
> 38 D - - 1 0 0 Primary Standard Error Device
> 66 D - - 1 0 0 PciRoot(0x0)/Pci(0x0,0x0)
> 67 B - - 1 1 1 QEMU Video PCI Adapter
> 68 D - - 1 2 0 Usb Universal Host Controller
> 69 B - - 1 2 1 Virtio Network Device
>
> Is that a known issue?
Yes, it is, the virtual BIOS is a modified UEFI from real hardware, it
try to load many modules such as grub. In current implementation, TCG
has a poor performance if there are lots of memory access.
>
> > + * 3, http://www.anheng.com.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> > + * 4, http://mirrors.ustc.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> > + * 5, http://mirrors.nju.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> > + * 6, https://mirrors.tuna.tsinghua.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> > + * 7, https://mirrors.bfsu.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> > + * 8, https://mirrors.cloud.tencent.com/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
> > + */
> > +#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
> > +
> > +#define UART_IRQ 0
> > +#define RTC_IRQ 1
> > +#define PCIE_IRQ_BASE 2
> > +
> > +const struct MemmapEntry virt_memmap[] = {
> > + [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
> > + [VIRT_PM] = { 0x10080000, 0x100 },
> > + [VIRT_FW_CFG] = { 0x10080100, 0x100 },
> > + [VIRT_RTC] = { 0x10081000, 0x1000 },
> > + [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
> > + [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
> > + [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
> > + [VIRT_UART] = { 0x1fe001e0, 0x8 },
> > + [VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
> > + [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
> > + [VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
> > +};
> > +
> > +static const struct MemmapEntry loader_memmap[] = {
> > + [LOADER_KERNEL] = { 0x00000000, 0x4000000 },
> > + [LOADER_INITRD] = { 0x04000000, 0x0 }, /* Variable */
> > + [LOADER_CMDLINE] = { 0x0ff00000, 0x100000 },
> > +};
> > +
> > +static const struct MemmapEntry loader_rommap[] = {
> > + [LOADER_BOOTROM] = { 0x1fc00000, 0x1000 },
> > + [LOADER_PARAM] = { 0x1fc01000, 0x10000 },
> > +};
> > +
> > +static struct _loaderparams {
> > + uint64_t cpu_freq;
> > + uint64_t ram_size;
> > + const char *kernel_cmdline;
> > + const char *kernel_filename;
> > + const char *initrd_filename;
> > + uint64_t kernel_entry;
> > + uint64_t a0, a1, a2;
> > +} loaderparams;
> > +
> > +static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
> > +{
> > + return 0;
> > +}
> > +
> > +static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
> > +{
> > + if (addr != PM_CNTL_MODE) {
> > + return;
> > + }
> > +
> > + switch (val) {
> > + case 0x00:
> > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> > + return;
> > + case 0xff:
> > + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
> > + return;
> > + default:
> > + return;
> > + }
> > +}
> > +
> > +static const MemoryRegionOps loongson3_pm_ops = {
> > + .read = loongson3_pm_read,
> > + .write = loongson3_pm_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > +};
> > +
> > +#define DEF_TCG_FREQ (200 * 1000 * 1000)
> > +#define DEF_KVM_FREQ (1600 * 1000 * 1000)
> > +
> > +static uint64_t get_cpu_freq(void)
>
> Please rename get_cpu_freq_hz().
OK.
>
> > +{
> > +#ifdef CONFIG_KVM
> > + int ret;
> > + uint64_t freq;
> > + struct kvm_one_reg freq_reg = {
> > + .id = KVM_REG_MIPS_COUNT_HZ,
> > + .addr = (uintptr_t)(&freq)
> > + };
> > +
> > + if (kvm_enabled()) {
>
> This is not working as expected... as this returns TRUE
> using TCG on x86.
I will improve this, as you listed below.
>
> > + ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
> > + if (ret < 0) {
> > + return DEF_KVM_FREQ;
> > + }
> > + return freq * 2;
> > + } else {
> > + /*
> > + * TCG has a default CP0 Timer period 10 ns, which is 100MHz,
> > + * CPU frequency is defined as double of CP0 timer frequency.
> > + */
> > + return DEF_TCG_FREQ;
> > + }
> > +#else
> > + return DEF_TCG_FREQ;
> > +#endif
> > +}
> > +
> > +static void init_boot_param(void)
> > +{
> > + void *p;
> > + struct boot_params *bp;
> > +
> > + p = g_malloc0(loader_rommap[LOADER_PARAM].size);
> > + bp = p;
> > +
> > + stw_le_p(&bp->efi.smbios.vers, 1);
> > + init_reset_system(&(bp->reset_system));
> > + p += ROUND_UP(sizeof(struct boot_params), 64);
> > + init_loongson_params(&(bp->efi.smbios.lp), p,
> > + loaderparams.cpu_freq, loaderparams.ram_size);
> > +
> > + rom_add_blob_fixed("params_rom", bp,
> > + loader_rommap[LOADER_PARAM].size,
> > + loader_rommap[LOADER_PARAM].base);
> > +
> > + g_free(bp);
> > +
> > + loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, loader_rommap[LOADER_PARAM].base);
> > +}
> > +
> > +static void init_boot_rom(void)
> > +{
> > + const unsigned int boot_code[] = {
> > + 0x40086000, /* mfc0 t0, CP0_STATUS */
> > + 0x240900E4, /* li t1, 0xe4 #set kx, sx, ux, erl */
> > + 0x01094025, /* or t0, t0, t1 */
> > + 0x3C090040, /* lui t1, 0x40 #set bev */
> > + 0x01094025, /* or t0, t0, t1 */
> > + 0x40886000, /* mtc0 t0, CP0_STATUS */
> > + 0x00000000,
> > + 0x40806800, /* mtc0 zero, CP0_CAUSE */
> > + 0x00000000,
> > + 0x400A7801, /* mfc0 t2, $15, 1 */
> > + 0x314A00FF, /* andi t2, 0x0ff */
> > + 0x3C089000, /* dli t0, 0x900000003ff01000 */
> > + 0x00084438,
> > + 0x35083FF0,
> > + 0x00084438,
> > + 0x35081000,
> > + 0x314B0003, /* andi t3, t2, 0x3 #local cpuid */
> > + 0x000B5A00, /* sll t3, 8 */
> > + 0x010B4025, /* or t0, t0, t3 */
> > + 0x314C000C, /* andi t4, t2, 0xc #node id */
> > + 0x000C62BC, /* dsll t4, 42 */
> > + 0x010C4025, /* or t0, t0, t4 */
> > + /* WaitForInit: */
> > + 0xDD020020, /* ld v0, FN_OFF(t0) #FN_OFF 0x020 */
> > + 0x1040FFFE, /* beqz v0, WaitForInit */
> > + 0x00000000, /* nop */
> > + 0xDD1D0028, /* ld sp, SP_OFF(t0) #FN_OFF 0x028 */
> > + 0xDD1C0030, /* ld gp, GP_OFF(t0) #FN_OFF 0x030 */
> > + 0xDD050038, /* ld a1, A1_OFF(t0) #FN_OFF 0x038 */
> > + 0x00400008, /* jr v0 #byebye */
> > + 0x00000000, /* nop */
> > + 0x1000FFFF, /* 1: b 1b */
> > + 0x00000000, /* nop */
> > +
> > + /* Reset */
> > + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> > + 0x358C0000,
> > + 0x000C6438,
> > + 0x358C1008,
> > + 0x000C6438,
> > + 0x358C0010,
> > + 0x240D0000, /* li t1, 0x00 */
> > + 0xA18D0000, /* sb t1, (t0) */
> > + 0x1000FFFF, /* 1: b 1b */
> > + 0x00000000, /* nop */
> > +
> > + /* Shutdown */
> > + 0x3C0C9000, /* dli t0, 0x9000000010080010 */
> > + 0x358C0000,
> > + 0x000C6438,
> > + 0x358C1008,
> > + 0x000C6438,
> > + 0x358C0010,
> > + 0x240D00FF, /* li t1, 0xff */
> > + 0xA18D0000, /* sb t1, (t0) */
> > + 0x1000FFFF, /* 1: b 1b */
> > + 0x00000000 /* nop */
> > + };
> > +
> > + rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
> > + loader_rommap[LOADER_BOOTROM].base);
> > +}
> > +
> > +static void fw_cfg_boot_set(void *opaque, const char *boot_device,
> > + Error **errp)
> > +{
> > + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
> > +}
> > +
> > +static void fw_conf_init(unsigned long ram_size)
> > +{
> > + FWCfgState *fw_cfg;
> > + hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
> > +
> > + fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
> > + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
> > + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
> > + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> > + fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
> > + fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq());
> > + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> > +}
> > +
> > +static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
> > +{
> > + hwaddr cmdline_vaddr;
> > + char memenv[32];
> > + char highmemenv[32];
> > + void *cmdline_buf;
> > + unsigned int *parg_env;
> > + int ret = 0;
> > +
> > + /* Allocate cmdline_buf for command line. */
> > + cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
> > + cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
> > + loader_memmap[LOADER_CMDLINE].base);
> > +
> > + /*
> > + * Layout of cmdline_buf looks like this:
> > + * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
> > + * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
> > + */
> > + parg_env = (void *)cmdline_buf;
> > +
> > + ret = (3 + 1) * 4;
> > + *parg_env++ = cmdline_vaddr + ret;
> > + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
> > +
> > + /* argv1 */
> > + *parg_env++ = cmdline_vaddr + ret;
> > + if (initrd_size > 0)
> > + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
> > + "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
> > + cpu_mips_phys_to_kseg0(NULL, initrd_offset),
> > + initrd_size, loaderparams.kernel_cmdline));
> > + else
> > + ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
> > + loaderparams.kernel_cmdline));
> > +
> > + /* argv2 */
> > + *parg_env++ = cmdline_vaddr + 4 * ret;
> > +
> > + /* env */
> > + sprintf(memenv, "%d", 256);
> > + sprintf(highmemenv, "%ld", (unsigned long)(loaderparams.ram_size / MiB) - 256);
> > +
> > + rom_add_blob_fixed("cmdline", cmdline_buf,
> > + loader_memmap[LOADER_CMDLINE].size,
> > + loader_memmap[LOADER_CMDLINE].base);
> > +
> > + g_free(cmdline_buf);
> > +
> > + loaderparams.a0 = 2;
> > + loaderparams.a1 = cmdline_vaddr;
> > +
> > + return 0;
> > +}
> > +
> > +static uint64_t load_kernel(CPUMIPSState *env)
> > +{
> > + long kernel_size;
> > + ram_addr_t initrd_offset;
> > + uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
> > +
> > + kernel_size = load_elf(loaderparams.kernel_filename, NULL,
> > + cpu_mips_kseg0_to_phys, NULL,
> > + (uint64_t *)&kernel_entry,
> > + (uint64_t *)&kernel_low, (uint64_t *)&kernel_high,
> > + NULL, 0, EM_MIPS, 1, 0);
> > + if (kernel_size < 0) {
> > + error_report("could not load kernel '%s': %s",
> > + loaderparams.kernel_filename,
> > + load_elf_strerror(kernel_size));
> > + exit(1);
> > + }
> > +
> > + /* load initrd */
> > + initrd_size = 0;
> > + initrd_offset = 0;
> > + if (loaderparams.initrd_filename) {
> > + initrd_size = get_image_size(loaderparams.initrd_filename);
> > + if (initrd_size > 0) {
> > + initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
> > + INITRD_PAGE_MASK;
> > + initrd_offset = MAX(initrd_offset,
> > + loader_memmap[LOADER_INITRD].base);
>
> Now you can use directly:
>
> initrd_offset = MAX(ROUND_UP(kernel_high, INITRD_PAGE_SIZE),
> loader_memmap[LOADER_INITRD].base);
>
OK.
> > +
> > + if (initrd_offset + initrd_size > ram_size) {
> > + error_report("memory too small for initial ram disk '%s'",
> > + loaderparams.initrd_filename);
> > + exit(1);
> > + }
> > +
> > + initrd_size = load_image_targphys(loaderparams.initrd_filename,
> > + initrd_offset,
> > + ram_size - initrd_offset);
> > + }
> > +
> > + if (initrd_size == (target_ulong) -1) {
> > + error_report("could not load initial ram disk '%s'",
> > + loaderparams.initrd_filename);
> > + exit(1);
> > + }
> > + }
> > +
> > + /* Setup prom cmdline. */
> > + set_prom_cmdline(initrd_offset, initrd_size);
> > +
> > + return kernel_entry;
> > +}
> > +
> > +static void main_cpu_reset(void *opaque)
> > +{
> > + MIPSCPU *cpu = opaque;
> > + CPUMIPSState *env = &cpu->env;
> > +
> > + cpu_reset(CPU(cpu));
> > +
> > + /* Loongson-3 reset stuff */
> > + if (loaderparams.kernel_filename) {
> > + if (cpu == MIPS_CPU(first_cpu)) {
> > + env->active_tc.gpr[4] = loaderparams.a0;
> > + env->active_tc.gpr[5] = loaderparams.a1;
> > + env->active_tc.gpr[6] = loaderparams.a2;
> > + env->active_tc.PC = loaderparams.kernel_entry;
> > + }
> > + env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
> > + }
> > +}
> > +
> > +static inline void loongson3_virt_devices_init(MachineState *machine, DeviceState *pic)
> > +{
> > + int i;
> > + qemu_irq irq;
> > + PCIBus *pci_bus;
> > + DeviceState *dev;
> > + MemoryRegion *pio_alias;
> > + MemoryRegion *mmio_alias, *mmio_reg;
> > + MemoryRegion *ecam_alias, *ecam_reg;
> > +
> > + dev = qdev_new(TYPE_GPEX_HOST);
> > + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> > + pci_bus = PCI_HOST_BRIDGE(dev)->bus;
> > +
> > + ecam_alias = g_new0(MemoryRegion, 1);
> > + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> > + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
> > + ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
> > + memory_region_add_subregion(get_system_memory(),
> > + virt_memmap[VIRT_PCIE_ECAM].base, ecam_alias);
> > +
> > + mmio_alias = g_new0(MemoryRegion, 1);
> > + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
> > + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
> > + mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
> > + virt_memmap[VIRT_PCIE_MMIO].size);
> > + memory_region_add_subregion(get_system_memory(),
> > + virt_memmap[VIRT_PCIE_MMIO].base, mmio_alias);
> > +
> > + pio_alias = g_new0(MemoryRegion, 1);
> > + memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
> > + get_system_io(), 0, virt_memmap[VIRT_PCIE_PIO].size);
> > + memory_region_add_subregion(get_system_memory(),
> > + virt_memmap[VIRT_PCIE_PIO].base, pio_alias);
> > + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
> > +
> > + for (i = 0; i < GPEX_NUM_IRQS; i++) {
> > + irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
> > + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
> > + }
> > +
> > + pci_vga_init(pci_bus);
> > +
> > + if (defaults_enabled()) {
> > + pci_create_simple(pci_bus, -1, "pci-ohci");
> > + usb_create_simple(usb_bus_find(-1), "usb-kbd");
> > + usb_create_simple(usb_bus_find(-1), "usb-tablet");
> > + }
> > +
> > + for (i = 0; i < nb_nics; i++) {
> > + NICInfo *nd = &nd_table[i];
> > +
> > + if (!nd->model) {
> > + nd->model = g_strdup("virtio");
> > + }
> > +
> > + pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
> > + }
> > +}
> > +
> > +static void mips_loongson3_virt_init(MachineState *machine)
> > +{
> > + int i;
> > + long bios_size;
> > + MIPSCPU *cpu;
> > + CPUMIPSState *env;
> > + DeviceState *liointc;
> > + char *filename;
> > + const char *kernel_cmdline = machine->kernel_cmdline;
> > + const char *kernel_filename = machine->kernel_filename;
> > + const char *initrd_filename = machine->initrd_filename;
> > + ram_addr_t ram_size = machine->ram_size;
> > + MemoryRegion *address_space_mem = get_system_memory();
> > + MemoryRegion *ram = g_new(MemoryRegion, 1);
> > + MemoryRegion *bios = g_new(MemoryRegion, 1);
> > + MemoryRegion *iomem = g_new(MemoryRegion, 1);
> > +
> > + /* TODO: TCG will support all CPU types */
> > + if (!kvm_enabled()) {
> > + if (!machine->cpu_type) {
> > + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
> > + }
> > + if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
> > + error_report("Loongson-3/TCG needs cpu type Loongson-3A1000");
> > + exit(1);
> > + }
> > + } else {
> > + if (!machine->cpu_type) {
> > + machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
> > + }
> > + if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
> > + error_report("Loongson-3/KVM needs cpu type Loongson-3A4000");
> > + exit(1);
> > + }
> > + }
> > +
> > + if (ram_size < 512 * MiB) {
> > + error_report("Loongson-3 machine needs at least 512MB memory");
> > + exit(1);
> > + }
> > +
> > + /*
> > + * The whole MMIO range among configure registers doesn't generate
> > + * exception when accessing invalid memory. Create some unimplememted
> > + * devices to emulate this feature.
> > + */
> > + create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB);
> > + create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB);
>
> The problem using large container to ignore accesses is we have
> no idea what the firmware is trying to do:
>
> mmio fallback 1: unimplemented device write (size 8, offset 0xff01038,
> value 0x980000000e3d1000)
> mmio fallback 1: unimplemented device write (size 8, offset 0xff01020,
> value 0x980000000e720ef8)
We can compute these addresses and find it in Loongson's documents,
this is also need to do for small regions.
And, the address caught by UNIMP devices are always "useless"
addresses for a virtual machine (because useful addresses are catched
by implemented devices).
>
> > +
> > + liointc = qdev_new("loongson.liointc");
> > + sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
> > +
> > + sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
> > +
> > + serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
> > + qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0),
> > + DEVICE_NATIVE_ENDIAN);
> > +
> > + sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
> > + qdev_get_gpio_in(liointc, RTC_IRQ));
> > +
> > + for (i = 0; i < machine->smp.cpus; i++) {
> > + int ip;
> > +
> > + /* init CPUs */
> > + cpu = MIPS_CPU(cpu_create(machine->cpu_type));
> > +
> > + /* Init internal devices */
> > + cpu_mips_irq_init_cpu(cpu);
> > + cpu_mips_clock_init(cpu);
> > + qemu_register_reset(main_cpu_reset, cpu);
> > +
> > + if (i >= 4) {
> > + continue; /* Only node-0 can be connected to LIOINTC */
> > + }
> > +
> > + for (ip = 0; ip < 4 ; ip++) {
> > + int pin = i * 4 + ip;
> > + sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
> > + pin, cpu->env.irq[ip + 2]);
> > + }
> > + }
> > + env = &MIPS_CPU(first_cpu)->env;
> > +
> > + /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
> > + memory_region_init_rom(bios, NULL, "loongson3.bios",
> > + virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
> > + memory_region_init_alias(ram, NULL, "loongson3.lowmem",
> > + machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
> > + memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
> > + NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
> > +
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_LOWMEM].base, ram);
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_BIOS_ROM].base, bios);
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_HIGHMEM].base, machine->ram);
> > + memory_region_add_subregion(address_space_mem,
> > + virt_memmap[VIRT_PM].base, iomem);
> > +
> > + /*
> > + * We do not support flash operation, just loading bios.bin as raw BIOS.
> > + * Please use -L to set the BIOS path and -bios to set bios name.
> > + */
> > +
> > + if (kernel_filename) {
> > + loaderparams.cpu_freq = get_cpu_freq();
> > + loaderparams.ram_size = ram_size;
> > + loaderparams.kernel_filename = kernel_filename;
> > + loaderparams.kernel_cmdline = kernel_cmdline;
> > + loaderparams.initrd_filename = initrd_filename;
> > + loaderparams.kernel_entry = load_kernel(env);
> > +
> > + init_boot_rom();
> > + init_boot_param();
> > + } else {
> > + if (bios_name == NULL) {
> > + bios_name = LOONGSON3_BIOSNAME;
> > + }
> > + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> > + if (filename) {
> > + bios_size = load_image_targphys(filename,
> > + virt_memmap[VIRT_BIOS_ROM].base,
> > + virt_memmap[VIRT_BIOS_ROM].size);
> > + g_free(filename);
> > + } else {
> > + bios_size = -1;
> > + }
> > +
> > + if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
> > + !kernel_filename && !qtest_enabled()) {
> > + error_report("Could not load MIPS bios '%s'", bios_name);
> > + exit(1);
> > + }
> > +
> > + fw_conf_init(ram_size);
> > + }
> > +
> > + msi_nonbroken = true;
> > + loongson3_virt_devices_init(machine, liointc);
> > +}
> > +
> > +static void mips_loongson3_virt_machine_init(MachineClass *mc)
> > +{
> > + mc->desc = "Loongson-3 Virtualization Platform";
> > + mc->init = mips_loongson3_virt_init;
> > + mc->block_default_type = IF_IDE;
> > + mc->max_cpus = LOONGSON_MAX_VCPUS;
> > + mc->default_ram_id = "loongson3.highram";
> > + mc->default_ram_size = 1600 * MiB;
> > + mc->kvm_type = mips_kvm_type;
> > + mc->minimum_page_bits = 14;
> > +}
>
> I tested on top of mips-next using:
>
> -- >8 --
> diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
> index 6a42808015d..2f1fa2e72ea 100644
> --- a/hw/mips/loongson3_virt.c
> +++ b/hw/mips/loongson3_virt.c
> @@ -31,6 +31,7 @@
> #include "cpu.h"
> #include "elf.h"
> #include "kvm_mips.h"
> +#include "hw/clock.h"
> #include "hw/boards.h"
> #include "hw/char/serial.h"
> #include "hw/mips/mips.h"
> @@ -141,9 +142,6 @@ static const MemoryRegionOps loongson3_pm_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -#define DEF_TCG_FREQ (200 * 1000 * 1000)
> -#define DEF_KVM_FREQ (1600 * 1000 * 1000)
> -
> static uint64_t get_cpu_freq(void)
> {
> #ifdef CONFIG_KVM
> @@ -156,20 +154,12 @@ static uint64_t get_cpu_freq(void)
>
> if (kvm_enabled()) {
> ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
> - if (ret < 0) {
> - return DEF_KVM_FREQ;
> + if (ret >= 0) {
> + return freq * 2;
> }
> - return freq * 2;
> - } else {
> - /*
> - * TCG has a default CP0 Timer period 10 ns, which is 100MHz,
> - * CPU frequency is defined as double of CP0 timer frequency.
> - */
> - return DEF_TCG_FREQ;
> }
> -#else
> - return DEF_TCG_FREQ;
> #endif
> + return 1600 * 1000 * 1000;
> }
>
> static void init_boot_param(void)
> @@ -471,6 +461,7 @@ static void mips_loongson3_virt_init(MachineState
> *machine)
> {
> int i;
> long bios_size;
> + Clock *cpuclk;
> MIPSCPU *cpu;
> CPUMIPSState *env;
> DeviceState *liointc;
> @@ -528,11 +519,14 @@ static void mips_loongson3_virt_init(MachineState
> *machine)
> sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
> qdev_get_gpio_in(liointc, RTC_IRQ));
>
> + cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
> + clock_set_hz(cpuclk, get_cpu_freq());
> +
> for (i = 0; i < machine->smp.cpus; i++) {
> int ip;
>
> /* init CPUs */
> - cpu = MIPS_CPU(cpu_create(machine->cpu_type));
> + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
>
> /* Init internal devices */
> cpu_mips_irq_init_cpu(cpu);
> ---
Huacai
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH V14 8/8] docs/system: Update MIPS machine documentation
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
` (6 preceding siblings ...)
2020-10-16 6:51 ` [PATCH V14 7/8] hw/mips: Add Loongson-3 machine support Huacai Chen
@ 2020-10-16 6:52 ` Huacai Chen
2020-10-16 14:25 ` Philippe Mathieu-Daudé
2020-10-16 7:06 ` [PATCH V14 0/8] mips: Add Loongson-3 machine support no-reply
2020-10-16 16:47 ` Philippe Mathieu-Daudé
9 siblings, 1 reply; 20+ messages in thread
From: Huacai Chen @ 2020-10-16 6:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic
Cc: Aleksandar Rikalo, Huacai Chen, qemu-devel, Huacai Chen, Aurelien Jarno
Add Loongson-3A CPU models and Loongson-3 based machine description.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
docs/system/cpu-models-mips.rst.inc | 10 ++++++++--
docs/system/target-mips.rst | 10 ++++++++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/docs/system/cpu-models-mips.rst.inc b/docs/system/cpu-models-mips.rst.inc
index 499b5b6fed..02cc4bb884 100644
--- a/docs/system/cpu-models-mips.rst.inc
+++ b/docs/system/cpu-models-mips.rst.inc
@@ -48,11 +48,17 @@ across all desired hosts.
``I6400``
MIPS64 Processor (Release 6, 2014)
+``Loongson-2E``
+ MIPS64 Processor (Loongson 2, 2006)
+
``Loongson-2F``
MIPS64 Processor (Loongson 2, 2008)
-``Loongson-2E``
- MIPS64 Processor (Loongson 2, 2006)
+``Loongson-3A1000``
+ MIPS64 Processor (Loongson 3, 2010)
+
+``Loongson-3A4000``
+ MIPS64 Processor (Loongson 3, 2018)
``mips64dspr2``
MIPS64 Processor (Release 2, 2006)
diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst
index cd2a931edf..138441bdec 100644
--- a/docs/system/target-mips.rst
+++ b/docs/system/target-mips.rst
@@ -84,6 +84,16 @@ The Fuloong 2E emulation supports:
- RTL8139D as a network card chipset
+The Loongson-3 virtual platform emulation supports:
+
+- Loongson 3A CPU
+
+- LIOINTC as interrupt controller
+
+- GPEX and virtio as peripheral devices
+
+- Both KVM and TCG supported
+
The mipssim pseudo board emulation provides an environment similar to
what the proprietary MIPS emulator uses for running Linux. It supports:
--
2.17.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH V14 8/8] docs/system: Update MIPS machine documentation
2020-10-16 6:52 ` [PATCH V14 8/8] docs/system: Update MIPS machine documentation Huacai Chen
@ 2020-10-16 14:25 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-16 14:25 UTC (permalink / raw)
To: Huacai Chen, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
On 10/16/20 8:52 AM, Huacai Chen wrote:
> Add Loongson-3A CPU models and Loongson-3 based machine description.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> docs/system/cpu-models-mips.rst.inc | 10 ++++++++--
> docs/system/target-mips.rst | 10 ++++++++++
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/docs/system/cpu-models-mips.rst.inc b/docs/system/cpu-models-mips.rst.inc
> index 499b5b6fed..02cc4bb884 100644
> --- a/docs/system/cpu-models-mips.rst.inc
> +++ b/docs/system/cpu-models-mips.rst.inc
> @@ -48,11 +48,17 @@ across all desired hosts.
> ``I6400``
> MIPS64 Processor (Release 6, 2014)
>
> +``Loongson-2E``
> + MIPS64 Processor (Loongson 2, 2006)
> +
> ``Loongson-2F``
> MIPS64 Processor (Loongson 2, 2008)
>
> -``Loongson-2E``
> - MIPS64 Processor (Loongson 2, 2006)
> +``Loongson-3A1000``
> + MIPS64 Processor (Loongson 3, 2010)
> +
> +``Loongson-3A4000``
> + MIPS64 Processor (Loongson 3, 2018)
>
> ``mips64dspr2``
> MIPS64 Processor (Release 2, 2006)
I'm queuing the CPU models part for now.
> diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst
> index cd2a931edf..138441bdec 100644
> --- a/docs/system/target-mips.rst
> +++ b/docs/system/target-mips.rst
> @@ -84,6 +84,16 @@ The Fuloong 2E emulation supports:
>
> - RTL8139D as a network card chipset
>
> +The Loongson-3 virtual platform emulation supports:
> +
> +- Loongson 3A CPU
> +
> +- LIOINTC as interrupt controller
> +
> +- GPEX and virtio as peripheral devices
> +
> +- Both KVM and TCG supported
> +
> The mipssim pseudo board emulation provides an environment similar to
> what the proprietary MIPS emulator uses for running Linux. It supports:
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 0/8] mips: Add Loongson-3 machine support
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
` (7 preceding siblings ...)
2020-10-16 6:52 ` [PATCH V14 8/8] docs/system: Update MIPS machine documentation Huacai Chen
@ 2020-10-16 7:06 ` no-reply
2020-10-16 16:47 ` Philippe Mathieu-Daudé
9 siblings, 0 replies; 20+ messages in thread
From: no-reply @ 2020-10-16 7:06 UTC (permalink / raw)
To: zltjiangshi
Cc: aleksandar.rikalo, chenhuacai, f4bug, qemu-devel,
aleksandar.qemu.devel, chenhc, aurelien
Patchew URL: https://patchew.org/QEMU/1602831120-3377-1-git-send-email-chenhc@lemote.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1602831120-3377-1-git-send-email-chenhc@lemote.com
Subject: [PATCH V14 0/8] mips: Add Loongson-3 machine support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1602831120-3377-1-git-send-email-chenhc@lemote.com -> patchew/1602831120-3377-1-git-send-email-chenhc@lemote.com
Switched to a new branch 'test'
d292df4 docs/system: Update MIPS machine documentation
4e63ead hw/mips: Add Loongson-3 machine support
1bf0737 hw/mips: Add Loongson-3 boot parameter helpers
bd43b2f hw/mips: Implement fw_cfg_arch_key_name()
f93634a target/mips: Add loongson-ext lsdc2 group of instructions
b55eee0 target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
2c2eaaa target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
ab68efd target/mips: Fix PageMask with variable page size
=== OUTPUT BEGIN ===
1/8 Checking commit ab68efdc70ef (target/mips: Fix PageMask with variable page size)
2/8 Checking commit 2c2eaaabbd3a (target/mips: Add loongson-ext lswc2 group of instructions (Part 1))
3/8 Checking commit b55eee07bfbe (target/mips: Add loongson-ext lswc2 group of instructions (Part 2))
4/8 Checking commit f93634a586de (target/mips: Add loongson-ext lsdc2 group of instructions)
5/8 Checking commit bd43b2ff95e9 (hw/mips: Implement fw_cfg_arch_key_name())
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16:
new file mode 100644
total: 0 errors, 1 warnings, 60 lines checked
Patch 5/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/8 Checking commit 1bf0737aee8c (hw/mips: Add Loongson-3 boot parameter helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
WARNING: line over 80 characters
#47: FILE: hw/mips/loongson3_bootp.c:28:
+static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq)
WARNING: line over 80 characters
#66: FILE: hw/mips/loongson3_bootp.c:47:
+static struct efi_memory_map_loongson *init_memory_map(void *g_map, uint64_t ram_size)
total: 0 errors, 3 warnings, 394 lines checked
Patch 6/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/8 Checking commit 4e63ead64501 (hw/mips: Add Loongson-3 machine support)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#80:
new file mode 100644
ERROR: line over 90 characters
#151: FILE: hw/mips/loongson3_virt.c:67:
+ * 3, http://www.anheng.com.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
ERROR: line over 90 characters
#152: FILE: hw/mips/loongson3_virt.c:68:
+ * 4, http://mirrors.ustc.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
ERROR: line over 90 characters
#153: FILE: hw/mips/loongson3_virt.c:69:
+ * 5, http://mirrors.nju.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
ERROR: line over 90 characters
#154: FILE: hw/mips/loongson3_virt.c:70:
+ * 6, https://mirrors.tuna.tsinghua.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
ERROR: line over 90 characters
#155: FILE: hw/mips/loongson3_virt.c:71:
+ * 7, https://mirrors.bfsu.edu.cn/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
ERROR: line over 90 characters
#156: FILE: hw/mips/loongson3_virt.c:72:
+ * 8, https://mirrors.cloud.tencent.com/loongson/firmware-nonfree/uefi/loongson3-virt/bios_loongson3.bin
WARNING: line over 80 characters
#204: FILE: hw/mips/loongson3_virt.c:120:
+static void loongson3_pm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
WARNING: line over 80 characters
#279: FILE: hw/mips/loongson3_virt.c:195:
+ loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL, loader_rommap[LOADER_PARAM].base);
WARNING: line over 80 characters
#361: FILE: hw/mips/loongson3_virt.c:277:
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
WARNING: line over 80 characters
#409: FILE: hw/mips/loongson3_virt.c:325:
+ sprintf(highmemenv, "%ld", (unsigned long)(loaderparams.ram_size / MiB) - 256);
WARNING: line over 80 characters
#495: FILE: hw/mips/loongson3_virt.c:411:
+static inline void loongson3_virt_devices_init(MachineState *machine, DeviceState *pic)
WARNING: line over 80 characters
#526: FILE: hw/mips/loongson3_virt.c:442:
+ get_system_io(), 0, virt_memmap[VIRT_PCIE_PIO].size);
WARNING: line over 80 characters
#640: FILE: hw/mips/loongson3_virt.c:556:
+ /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
total: 6 errors, 8 warnings, 660 lines checked
Patch 7/8 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/8 Checking commit d292df465eb8 (docs/system: Update MIPS machine documentation)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1602831120-3377-1-git-send-email-chenhc@lemote.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH V14 0/8] mips: Add Loongson-3 machine support
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
` (8 preceding siblings ...)
2020-10-16 7:06 ` [PATCH V14 0/8] mips: Add Loongson-3 machine support no-reply
@ 2020-10-16 16:47 ` Philippe Mathieu-Daudé
9 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-16 16:47 UTC (permalink / raw)
To: Huacai Chen, Aleksandar Markovic
Cc: Huacai Chen, Huacai Chen, Aleksandar Rikalo, qemu-devel, Aurelien Jarno
On 10/16/20 8:51 AM, Huacai Chen wrote:
> Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
> R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
> Loongson-3A R4 is the newest and its ISA is almost the superset of all
> others. To reduce complexity, in QEMU we just define two CPU types:
>
> 1, "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
> suitable for TCG because Loongson-3A R1 has fewest ASE.
> 2, "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
> suitable for KVM because Loongson-3A R4 has the VZ ASE.
>
> Loongson-3 lacks English documents. I've tried to translated them with
> translate.google.com, and the machine translated documents (together
> with their original Chinese versions) are available here.
>
> Loongson-3A R1 (Loongson-3A1000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A1000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P1.pdf (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A1000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P2.pdf (Chinese Version)
>
> Loongson-3A R2 (Loongson-3A2000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A2000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A2000_user1.pdf (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A2000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A2000_user2.pdf (Chinese Version)
>
> Loongson-3A R3 (Loongson-3A3000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A3000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual1.pdf (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A3000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual2.pdf (Chinese Version)
>
> Loongson-3A R4 (Loongson-3A4000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A4000_p1.pdf
> http://ftp.godson.ac.cn/lemote/3A4000user.pdf (Chinese Version)
> User Manual Part 2:
> I'm sorry that it is unavailable now.
>
> And human-translated documents (W.I.P) are available here now:
> https://github.com/loongson-community/docs/tree/master/English-translation-of-Loongson-manual
Patches 2-4 applied to mips-next (fixing the
bisectability build failure in patch 2 & 3).
^ permalink raw reply [flat|nested] 20+ messages in thread