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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id 140sm5314248pfv.38.2020.06.04.14.32.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Jun 2020 14:32:03 -0700 (PDT) Subject: Re: [PATCH v8 58/62] target/riscv: floating-point scalar move instructions To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20200521094413.10425-1-zhiwei_liu@c-sky.com> <20200521094413.10425-59-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: Date: Thu, 4 Jun 2020 14:32:01 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200521094413.10425-59-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, wenmeng_zhang@c-sky.com, alistair.francis@wdc.com, wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/21/20 2:44 AM, LIU Zhiwei wrote: > +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) > +{ > + if (!s->vill && has_ext(s, RVF) && > + (s->mstatus_fs != 0) && (s->sew != 0)) { > + unsigned int ofs = (8 << s->sew); > + unsigned int len = 64 - ofs; > + TCGv_i64 t_nan; > + > + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); > + /* NaN-box f[rd] as necessary for SEW */ > + if (len) { > + t_nan = tcg_const_i64(UINT64_MAX); > + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], > + t_nan, ofs, len); > + tcg_temp_free_i64(t_nan); > + } I guess this is correct, but it looks odd. I would have done unsigned int len = 8 << s->sew; if (len < 64) { tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], MAKE_64BIT_MASK(len, 64 - len)); } and to match, I might use MAKE_64BIT_MASK(32, 32) in trans_vfmv_s_f. Otherwise, Reviewed-by: Richard Henderson r~