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Tue, 7 Sep 2021 21:55:08 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.165.20]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4H48vX0p9qz1RvlR; Tue, 7 Sep 2021 21:55:03 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v2 3/3] target/riscv: Set mtval and stval support Date: Wed, 8 Sep 2021 14:54:57 +1000 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=87817de26=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d11db1f031..5b0bbf2fca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -309,6 +309,7 @@ struct RISCVCPU { bool mmu; bool pmp; bool epmp; + bool mtval_inst; uint64_t resetvec; } cfg; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579..537f2af341 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -437,6 +437,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } } =20 + if (cpu->cfg.mtval_inst) { + set_feature(env, RISCV_FEATURE_MTVAL_INST); + } + set_resetvec(env, cpu->cfg.resetvec); =20 /* If only XLEN is set for misa, then set misa from properties */ @@ -600,7 +604,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - + DEFINE_PROP_BOOL("tval-inst", RISCVCPU, cfg.mtval_inst, true), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVE= C), DEFINE_PROP_END_OF_LIST(), }; --=20 2.31.1