* [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
@ 2019-08-21 16:28 Georg Kotheimer
2019-08-23 22:44 ` Jim Wilson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Georg Kotheimer @ 2019-08-21 16:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Palmer Dabbelt, qemu-riscv, Georg Kotheimer
The size of the FPU registers depends solely on the floating point
extensions supported by the target architecture.
However, in the previous implementation the floating point register
size was derived from whether the target architecture is 32-bit or
64-bit.
To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
riscv_gdb_set_fpu() were necessary.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
---
configure | 4 ++--
target/riscv/gdbstub.c | 45 ++++++++++++++++++++++++------------------
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/configure b/configure
index 714e7fb6a1..44ee953022 100755
--- a/configure
+++ b/configure
@@ -7596,14 +7596,14 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 27be93279b..89b2543c9d 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -303,19 +303,22 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- return gdb_get_reg64(mem_buf, env->fpr[n]);
+ if (env->misa & RVD) {
+ return gdb_get_reg64(mem_buf, env->fpr[n]);
+ }
+ return gdb_get_reg32(mem_buf, env->fpr[n]);
/* there is hole between ft11 and fflags in fpu.xml */
} else if (n < 36 && n > 32) {
target_ulong val = 0;
int result;
/*
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
- * register 33, so we recalculate the map index.
+ * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
+ * register 33, so we recalculate the csr index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
+ result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, &val, 0, 0);
if (result == 0) {
- return gdb_get_regl(mem_buf, val);
+ return gdb_get_reg32(mem_buf, val);
}
}
return 0;
@@ -324,20 +327,25 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
- env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
- return sizeof(uint64_t);
+ if (env->misa & RVD) {
+ env->fpr[n] = ldq_p(mem_buf);
+ return sizeof(uint64_t);
+ } else {
+ env->fpr[n] = ldl_p(mem_buf);
+ return sizeof(uint32_t);
+ }
/* there is hole between ft11 and fflags in fpu.xml */
} else if (n < 36 && n > 32) {
- target_ulong val = ldtul_p(mem_buf);
+ target_ulong val = ldl_p(mem_buf);
int result;
/*
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
- * register 33, so we recalculate the map index.
+ * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
+ * register 33, so we recalculate the csr index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
+ result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, NULL, val, -1);
if (result == 0) {
- return sizeof(target_ulong);
+ return sizeof(uint32_t);
}
}
return 0;
@@ -375,20 +383,19 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-#if defined(TARGET_RISCV32)
- if (env->misa & RVF) {
+
+ if (env->misa & RVD) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 36, "riscv-64bit-fpu.xml", 0);
+ } else if (env->misa & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
+#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-32bit-csr.xml", 0);
#elif defined(TARGET_RISCV64)
- if (env->misa & RVF) {
- gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-64bit-fpu.xml", 0);
- }
-
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-64bit-csr.xml", 0);
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
2019-08-21 16:28 [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions Georg Kotheimer
@ 2019-08-23 22:44 ` Jim Wilson
2019-08-24 0:13 ` Alistair Francis
2020-01-07 11:26 ` Alex Bennée
2 siblings, 0 replies; 5+ messages in thread
From: Jim Wilson @ 2019-08-23 22:44 UTC (permalink / raw)
To: Georg Kotheimer, qemu-devel; +Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis
On 8/21/19 9:28 AM, Georg Kotheimer wrote:
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target architecture is 32-bit or
> 64-bit.
>
> To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
> riscv_gdb_set_fpu() were necessary.
Reviewed-by: Jim Wilson <jimw@sifive.com>
Jim
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
2019-08-21 16:28 [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions Georg Kotheimer
2019-08-23 22:44 ` Jim Wilson
@ 2019-08-24 0:13 ` Alistair Francis
2020-01-07 11:26 ` Alex Bennée
2 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2019-08-24 0:13 UTC (permalink / raw)
To: Georg Kotheimer
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Aug 21, 2019 at 9:36 AM Georg Kotheimer
<georg.kotheimer@kernkonzept.com> wrote:
>
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target architecture is 32-bit or
> 64-bit.
>
> To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
> riscv_gdb_set_fpu() were necessary.
>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configure | 4 ++--
> target/riscv/gdbstub.c | 45 ++++++++++++++++++++++++------------------
> 2 files changed, 28 insertions(+), 21 deletions(-)
>
> diff --git a/configure b/configure
> index 714e7fb6a1..44ee953022 100755
> --- a/configure
> +++ b/configure
> @@ -7596,14 +7596,14 @@ case "$target_name" in
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
> + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml"
> target_compiler=$cross_cc_riscv32
> ;;
> riscv64)
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> + gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> target_compiler=$cross_cc_riscv64
> ;;
> sh4|sh4eb)
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 27be93279b..89b2543c9d 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -303,19 +303,22 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> {
> if (n < 32) {
> - return gdb_get_reg64(mem_buf, env->fpr[n]);
> + if (env->misa & RVD) {
> + return gdb_get_reg64(mem_buf, env->fpr[n]);
> + }
> + return gdb_get_reg32(mem_buf, env->fpr[n]);
> /* there is hole between ft11 and fflags in fpu.xml */
> } else if (n < 36 && n > 32) {
> target_ulong val = 0;
> int result;
> /*
> - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
> - * register 33, so we recalculate the map index.
> + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
> + * register 33, so we recalculate the csr index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
> + result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, &val, 0, 0);
> if (result == 0) {
> - return gdb_get_regl(mem_buf, val);
> + return gdb_get_reg32(mem_buf, val);
> }
> }
> return 0;
> @@ -324,20 +327,25 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> {
> if (n < 32) {
> - env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> - return sizeof(uint64_t);
> + if (env->misa & RVD) {
> + env->fpr[n] = ldq_p(mem_buf);
> + return sizeof(uint64_t);
> + } else {
> + env->fpr[n] = ldl_p(mem_buf);
> + return sizeof(uint32_t);
> + }
> /* there is hole between ft11 and fflags in fpu.xml */
> } else if (n < 36 && n > 32) {
> - target_ulong val = ldtul_p(mem_buf);
> + target_ulong val = ldl_p(mem_buf);
> int result;
> /*
> - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
> - * register 33, so we recalculate the map index.
> + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
> + * register 33, so we recalculate the csr index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> + result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, NULL, val, -1);
> if (result == 0) {
> - return sizeof(target_ulong);
> + return sizeof(uint32_t);
> }
> }
> return 0;
> @@ -375,20 +383,19 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> -#if defined(TARGET_RISCV32)
> - if (env->misa & RVF) {
> +
> + if (env->misa & RVD) {
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 36, "riscv-64bit-fpu.xml", 0);
> + } else if (env->misa & RVF) {
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-32bit-fpu.xml", 0);
> }
>
> +#if defined(TARGET_RISCV32)
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> 4096, "riscv-32bit-csr.xml", 0);
> #elif defined(TARGET_RISCV64)
> - if (env->misa & RVF) {
> - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> - 36, "riscv-64bit-fpu.xml", 0);
> - }
> -
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> 4096, "riscv-64bit-csr.xml", 0);
> #endif
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
2019-08-21 16:28 [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions Georg Kotheimer
2019-08-23 22:44 ` Jim Wilson
2019-08-24 0:13 ` Alistair Francis
@ 2020-01-07 11:26 ` Alex Bennée
2020-01-17 12:08 ` Alistair Francis
2 siblings, 1 reply; 5+ messages in thread
From: Alex Bennée @ 2020-01-07 11:26 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis, Georg Kotheimer
Georg Kotheimer <georg.kotheimer@kernkonzept.com> writes:
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target architecture is 32-bit or
> 64-bit.
>
> To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
> riscv_gdb_set_fpu() were necessary.
>
> Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
> ---
> configure | 4 ++--
> target/riscv/gdbstub.c | 45 ++++++++++++++++++++++++------------------
> 2 files changed, 28 insertions(+), 21 deletions(-)
>
> diff --git a/configure b/configure
> index 714e7fb6a1..44ee953022 100755
> --- a/configure
> +++ b/configure
> @@ -7596,14 +7596,14 @@ case "$target_name" in
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
> + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml"
> target_compiler=$cross_cc_riscv32
> ;;
> riscv64)
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> + gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> target_compiler=$cross_cc_riscv64
> ;;
> sh4|sh4eb)
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 27be93279b..89b2543c9d 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -303,19 +303,22 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> {
> if (n < 32) {
> - return gdb_get_reg64(mem_buf, env->fpr[n]);
> + if (env->misa & RVD) {
> + return gdb_get_reg64(mem_buf, env->fpr[n]);
> + }
> + return gdb_get_reg32(mem_buf, env->fpr[n]);
> /* there is hole between ft11 and fflags in fpu.xml */
> } else if (n < 36 && n > 32) {
> target_ulong val = 0;
> int result;
> /*
> - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
> - * register 33, so we recalculate the map index.
> + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
> + * register 33, so we recalculate the csr index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
> + result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, &val, 0, 0);
> if (result == 0) {
> - return gdb_get_regl(mem_buf, val);
> + return gdb_get_reg32(mem_buf, val);
> }
> }
> return 0;
> @@ -324,20 +327,25 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> {
> if (n < 32) {
> - env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> - return sizeof(uint64_t);
> + if (env->misa & RVD) {
> + env->fpr[n] = ldq_p(mem_buf);
> + return sizeof(uint64_t);
> + } else {
> + env->fpr[n] = ldl_p(mem_buf);
> + return sizeof(uint32_t);
> + }
What endianess can RISC-V support? Unless specifically stated by the
architecture values should be returned in tgarget endian format.
> /* there is hole between ft11 and fflags in fpu.xml */
> } else if (n < 36 && n > 32) {
> - target_ulong val = ldtul_p(mem_buf);
> + target_ulong val = ldl_p(mem_buf);
> int result;
> /*
> - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
> - * register 33, so we recalculate the map index.
> + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
> + * register 33, so we recalculate the csr index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> + result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, NULL, val, -1);
> if (result == 0) {
> - return sizeof(target_ulong);
> + return sizeof(uint32_t);
> }
> }
> return 0;
> @@ -375,20 +383,19 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> -#if defined(TARGET_RISCV32)
> - if (env->misa & RVF) {
> +
> + if (env->misa & RVD) {
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 36, "riscv-64bit-fpu.xml", 0);
> + } else if (env->misa & RVF) {
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-32bit-fpu.xml", 0);
> }
>
> +#if defined(TARGET_RISCV32)
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> 4096, "riscv-32bit-csr.xml", 0);
> #elif defined(TARGET_RISCV64)
> - if (env->misa & RVF) {
> - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> - 36, "riscv-64bit-fpu.xml", 0);
> - }
> -
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> 4096, "riscv-64bit-csr.xml", 0);
> #endif
--
Alex Bennée
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
2020-01-07 11:26 ` Alex Bennée
@ 2020-01-17 12:08 ` Alistair Francis
0 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2020-01-17 12:08 UTC (permalink / raw)
To: Alex Bennée
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Georg Kotheimer
On Tue, Jan 7, 2020 at 10:21 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Georg Kotheimer <georg.kotheimer@kernkonzept.com> writes:
>
> > The size of the FPU registers depends solely on the floating point
> > extensions supported by the target architecture.
> > However, in the previous implementation the floating point register
> > size was derived from whether the target architecture is 32-bit or
> > 64-bit.
> >
> > To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
> > riscv_gdb_set_fpu() were necessary.
> >
> > Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
> > ---
> > configure | 4 ++--
> > target/riscv/gdbstub.c | 45 ++++++++++++++++++++++++------------------
> > 2 files changed, 28 insertions(+), 21 deletions(-)
> >
> > diff --git a/configure b/configure
> > index 714e7fb6a1..44ee953022 100755
> > --- a/configure
> > +++ b/configure
> > @@ -7596,14 +7596,14 @@ case "$target_name" in
> > TARGET_BASE_ARCH=riscv
> > TARGET_ABI_DIR=riscv
> > mttcg=yes
> > - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
> > + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml"
> > target_compiler=$cross_cc_riscv32
> > ;;
> > riscv64)
> > TARGET_BASE_ARCH=riscv
> > TARGET_ABI_DIR=riscv
> > mttcg=yes
> > - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> > + gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> > target_compiler=$cross_cc_riscv64
> > ;;
> > sh4|sh4eb)
> > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> > index 27be93279b..89b2543c9d 100644
> > --- a/target/riscv/gdbstub.c
> > +++ b/target/riscv/gdbstub.c
> > @@ -303,19 +303,22 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> > static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> > {
> > if (n < 32) {
> > - return gdb_get_reg64(mem_buf, env->fpr[n]);
> > + if (env->misa & RVD) {
> > + return gdb_get_reg64(mem_buf, env->fpr[n]);
> > + }
> > + return gdb_get_reg32(mem_buf, env->fpr[n]);
> > /* there is hole between ft11 and fflags in fpu.xml */
> > } else if (n < 36 && n > 32) {
> > target_ulong val = 0;
> > int result;
> > /*
> > - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
> > - * register 33, so we recalculate the map index.
> > + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
> > + * register 33, so we recalculate the csr index.
> > * This also works for CSR_FRM and CSR_FCSR.
> > */
> > - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
> > + result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, &val, 0, 0);
> > if (result == 0) {
> > - return gdb_get_regl(mem_buf, val);
> > + return gdb_get_reg32(mem_buf, val);
> > }
> > }
> > return 0;
> > @@ -324,20 +327,25 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> > static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> > {
> > if (n < 32) {
> > - env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> > - return sizeof(uint64_t);
> > + if (env->misa & RVD) {
> > + env->fpr[n] = ldq_p(mem_buf);
> > + return sizeof(uint64_t);
> > + } else {
> > + env->fpr[n] = ldl_p(mem_buf);
> > + return sizeof(uint32_t);
> > + }
>
> What endianess can RISC-V support? Unless specifically stated by the
> architecture values should be returned in tgarget endian format.
It can support both.
What needs to be changed?
Alistair
>
> > /* there is hole between ft11 and fflags in fpu.xml */
> > } else if (n < 36 && n > 32) {
> > - target_ulong val = ldtul_p(mem_buf);
> > + target_ulong val = ldl_p(mem_buf);
> > int result;
> > /*
> > - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
> > - * register 33, so we recalculate the map index.
> > + * CSR_FFLAGS is at index 1 in the csr space, and gdb says it is FP
> > + * register 33, so we recalculate the csr index.
> > * This also works for CSR_FRM and CSR_FCSR.
> > */
> > - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> > + result = riscv_csrrw_debug(env, n - 33 + CSR_FFLAGS, NULL, val, -1);
> > if (result == 0) {
> > - return sizeof(target_ulong);
> > + return sizeof(uint32_t);
> > }
> > }
> > return 0;
> > @@ -375,20 +383,19 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> > {
> > RISCVCPU *cpu = RISCV_CPU(cs);
> > CPURISCVState *env = &cpu->env;
> > -#if defined(TARGET_RISCV32)
> > - if (env->misa & RVF) {
> > +
> > + if (env->misa & RVD) {
> > + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> > + 36, "riscv-64bit-fpu.xml", 0);
> > + } else if (env->misa & RVF) {
> > gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> > 36, "riscv-32bit-fpu.xml", 0);
> > }
> >
> > +#if defined(TARGET_RISCV32)
> > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> > 4096, "riscv-32bit-csr.xml", 0);
> > #elif defined(TARGET_RISCV64)
> > - if (env->misa & RVF) {
> > - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> > - 36, "riscv-64bit-fpu.xml", 0);
> > - }
> > -
> > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> > 4096, "riscv-64bit-csr.xml", 0);
> > #endif
>
>
> --
> Alex Bennée
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-17 12:09 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-21 16:28 [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions Georg Kotheimer
2019-08-23 22:44 ` Jim Wilson
2019-08-24 0:13 ` Alistair Francis
2020-01-07 11:26 ` Alex Bennée
2020-01-17 12:08 ` Alistair Francis
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