From: Richard Henderson <richard.henderson@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>, qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, "Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH] target/arm: ensure we use current exception state after SCR update
Date: Wed, 11 Dec 2019 16:31:33 -0800 [thread overview]
Message-ID: <c0c7e5e4-9d62-6a07-b972-d8cbf2c18c25@linaro.org> (raw)
In-Reply-To: <20191209143723.6368-1-alex.bennee@linaro.org>
On 12/9/19 6:37 AM, Alex Bennée wrote:
> +/* Re-read the current EL, don't use cached values */
> #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
> #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
> #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
...
> @@ -5179,7 +5179,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
> .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
> .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
> .resetvalue = 0, .writefn = scr_write },
> - { .name = "SCR", .type = ARM_CP_ALIAS,
> + { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_CURRENTEL,
I don't think you should reuse this value. It is not a simple bit.
While ARM_CP_* all appear to implement a 16-bit quantity, the type field is
already an int, and so can easily hold more. I think you should use a new bit
for this.
r~
prev parent reply other threads:[~2019-12-12 0:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 14:37 [PATCH] target/arm: ensure we use current exception state after SCR update Alex Bennée
2019-12-09 14:44 ` Philippe Mathieu-Daudé
2019-12-09 19:28 ` no-reply
2019-12-12 0:31 ` Richard Henderson [this message]
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