From: Robert Hoo <robert.hu@linux.intel.com>
To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v4] i386/cpu_dump: support AVX512 ZMM regs dump
Date: Fri, 26 Mar 2021 23:01:49 +0800 [thread overview]
Message-ID: <c31c1d0033d1cdf7aee6dc20cb3c4c27ec754222.camel@linux.intel.com> (raw)
In-Reply-To: <1616770469-36979-1-git-send-email-robert.hu@linux.intel.com>
On Fri, 2021-03-26 at 22:54 +0800, Robert Hoo wrote:
> Since commit fa4518741e (target-i386: Rename struct XMMReg to
> ZMMReg),
> CPUX86State.xmm_regs[] has already been extended to 512bit to support
> AVX512.
> Also, other qemu level supports for AVX512 registers are there for
> years.
> But in x86_cpu_dump_state(), still only dump XMM registers no matter
> YMM/ZMM is enabled.
> This patch is to complement this, let it dump XMM/YMM/ZMM
> accordingly.
>
> Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
> ---
> Changelog:
> v4: stringent AVX512 case and AVX case judgement criteria
> v3: fix some coding style issue.
> v2: dump XMM/YMM/ZMM according to XSAVE state-components enablement.
>
> target/i386/cpu-dump.c | 62 ++++++++++++++++++++++++++++++++++++++
> ------------
> 1 file changed, 47 insertions(+), 15 deletions(-)
>
> diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
> index aac21f1..dea4564 100644
> --- a/target/i386/cpu-dump.c
> +++ b/target/i386/cpu-dump.c
> @@ -478,6 +478,11 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f,
> int flags)
> qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
> if (flags & CPU_DUMP_FPU) {
> int fptag;
> + const uint64_t avx512_mask = XSTATE_OPMASK_MASK | \
> + XSTATE_ZMM_Hi256_MASK | \
> + XSTATE_Hi16_ZMM_MASK | \
> + XSTATE_YMM_MASK |
> XSTATE_SSE_MASK,
> + avx_mask = XSTATE_YMM_MASK | XSTATE_SSE_MASK;
> fptag = 0;
> for(i = 0; i < 8; i++) {
> fptag |= ((!env->fptags[i]) << i);
> @@ -499,21 +504,48 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f,
> int flags)
> else
> qemu_fprintf(f, " ");
> }
> - if (env->hflags & HF_CS64_MASK)
> - nb = 16;
> - else
> - nb = 8;
> - for(i=0;i<nb;i++) {
> - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
> - i,
> - env->xmm_regs[i].ZMM_L(3),
> - env->xmm_regs[i].ZMM_L(2),
> - env->xmm_regs[i].ZMM_L(1),
> - env->xmm_regs[i].ZMM_L(0));
> - if ((i & 1) == 1)
> - qemu_fprintf(f, "\n");
> - else
> - qemu_fprintf(f, " ");
> +
> + if ((env->xcr0 & avx512_mask) == avx512_mask) {
> + /* XSAVE enabled AVX512 */
> + for (i = 0; i < NB_OPMASK_REGS; i++) {
> + qemu_fprintf(f, "Opmask%02d=%016lx%s", i, env-
> >opmask_regs[i],
> + ((i & 3) == 3) ? "\n" : " ");
> + }
> +
> + nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
> + for (i = 0; i < nb; i++) {
> + qemu_fprintf(f, "ZMM%02d=%016lx %016lx %016lx %016lx
> %016lx "
> + "%016lx %016lx %016lx\n",
> + i,
> + env->xmm_regs[i].ZMM_Q(7),
> + env->xmm_regs[i].ZMM_Q(6),
> + env->xmm_regs[i].ZMM_Q(5),
> + env->xmm_regs[i].ZMM_Q(4),
> + env->xmm_regs[i].ZMM_Q(3),
> + env->xmm_regs[i].ZMM_Q(2),
> + env->xmm_regs[i].ZMM_Q(1),
> + env->xmm_regs[i].ZMM_Q(0));
> + }
> + } else if (env->xcr0 & avx_mask) {
Here should be
else if ((env->xcr0 & avx_mask) == avx_mask)
Sorry about my sleepy head.
> + /* XSAVE enabled AVX */
> + nb = env->hflags & HF_CS64_MASK ? 16 : 8;
> + for (i = 0; i < nb; i++) {
> + qemu_fprintf(f, "YMM%02d=%016lx %016lx %016lx
> %016lx\n",
> + i,
> + env->xmm_regs[i].ZMM_Q(3),
> + env->xmm_regs[i].ZMM_Q(2),
> + env->xmm_regs[i].ZMM_Q(1),
> + env->xmm_regs[i].ZMM_Q(0));
> + }
> + } else { /* SSE and below cases */
> + nb = env->hflags & HF_CS64_MASK ? 16 : 8;
> + for (i = 0; i < nb; i++) {
> + qemu_fprintf(f, "XMM%02d=%016lx %016lx%s",
> + i,
> + env->xmm_regs[i].ZMM_Q(1),
> + env->xmm_regs[i].ZMM_Q(0),
> + (i & 1) ? "\n" : " ");
> + }
> }
> }
> if (flags & CPU_DUMP_CODE) {
next prev parent reply other threads:[~2021-03-26 15:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 14:54 [PATCH v4] i386/cpu_dump: support AVX512 ZMM regs dump Robert Hoo
2021-03-26 15:01 ` Robert Hoo [this message]
2021-04-06 2:36 ` Robert Hoo
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