From: "Philippe Mathieu-Daudé via" <qemu-devel@nongnu.org>
To: Wilfred Mallawa <wilfred.mallawa@opensource.wdc.com>,
Alistair.Francis@wdc.com, qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org, Wilfred Mallawa <wilfred.mallawa@wdc.com>
Subject: Re: [PATCH v4 3/4] hw/ssi: ibex_spi: fixup/add rw1c functionality
Date: Tue, 30 Aug 2022 14:33:33 +0200 [thread overview]
Message-ID: <c33257a3-645f-9386-52e5-21a15ef0ebe5@amsat.org> (raw)
In-Reply-To: <20220823061201.132342-4-wilfred.mallawa@opensource.wdc.com>
On 23/8/22 08:12, Wilfred Mallawa wrote:
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> This patch adds the `rw1c` functionality to the respective
> registers. The status fields are cleared when the respective
> field is set.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/ssi/ibex_spi_host.c | 34 ++++++++++++++++++++++++++++++++--
> include/hw/ssi/ibex_spi_host.h | 4 ++--
> 2 files changed, 34 insertions(+), 4 deletions(-)
>
> diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
> index d52b193a1a..40d401ad47 100644
> --- a/hw/ssi/ibex_spi_host.c
> +++ b/hw/ssi/ibex_spi_host.c
> @@ -352,7 +352,17 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
>
> switch (addr) {
> /* Skipping any R/O registers */
> - case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE:
> + case IBEX_SPI_HOST_INTR_STATE:
> + /* rw1c status register */
> + if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
> + data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
> + }
> + if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
> + data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
> + }
> + s->regs[addr] = data;
> + break;
> + case IBEX_SPI_HOST_INTR_ENABLE:
> s->regs[addr] = val32;
> break;
> case IBEX_SPI_HOST_INTR_TEST:
> @@ -495,7 +505,27 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
> * When an error occurs, the corresponding bit must be cleared
> * here before issuing any further commands
> */
> - s->regs[addr] = val32;
> + status = s->regs[addr];
> + /* rw1c status register */
> + if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
> + status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
> + }
> + if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
> + status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
> + }
> + if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
> + status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
> + }
> + if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
> + status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
> + }
> + if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
> + status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
> + }
> + if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
> + status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
> + }
Alistair, does this call to add some FIELD_1CLEAR() API?
next prev parent reply other threads:[~2022-08-30 12:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-23 6:11 [PATCH v4 0/4] hw/ssi: ibex_spi: cleanup and fixup bugs Wilfred Mallawa
2022-08-23 6:12 ` [PATCH v4 1/4] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Wilfred Mallawa
2022-08-23 6:12 ` [PATCH v4 2/4] hw/ssi: ibex_spi: fixup coverity issue Wilfred Mallawa
2022-08-30 9:11 ` Alistair Francis
2022-09-08 11:30 ` Alistair Francis
2022-08-23 6:12 ` [PATCH v4 3/4] hw/ssi: ibex_spi: fixup/add rw1c functionality Wilfred Mallawa
2022-08-30 12:33 ` Philippe Mathieu-Daudé via [this message]
2022-08-30 15:50 ` Alistair Francis
2022-08-23 6:12 ` [PATCH v4 4/4] hw/ssi: ibex_spi: update reg addr Wilfred Mallawa
2022-09-08 9:08 ` [PATCH v4 0/4] hw/ssi: ibex_spi: cleanup and fixup bugs Alistair Francis
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