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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions
Date: Thu,  1 Apr 2021 11:17:48 -0400	[thread overview]
Message-ID: <cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1617290165.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5dc2aa9845..a82a98061b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -181,7 +181,11 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
 static RISCVException hmode32(CPURISCVState *env, int csrno)
 {
     if (!riscv_cpu_is_32bit(env)) {
-        return RISCV_EXCP_NONE;
+        if (riscv_cpu_virt_enabled(env)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        } else {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
     }
 
     return hmode(env, csrno);
-- 
2.31.0



  parent reply	other threads:[~2021-04-01 15:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-01 15:17 [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use Alistair Francis
2021-04-01 15:17 ` [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-04-02 17:11   ` Richard Henderson
2021-04-01 15:17 ` [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-04-02 17:14   ` Richard Henderson
2021-04-06  8:34   ` Bin Meng
2021-04-01 15:17 ` Alistair Francis [this message]
2021-04-02 17:14   ` [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions Richard Henderson
2021-04-06  8:34   ` Bin Meng
2021-04-01 15:17 ` [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-04-02 17:17   ` Richard Henderson
2021-04-06  8:34   ` Bin Meng
2021-04-01 15:18 ` [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-04-02 17:18   ` Richard Henderson
2021-04-06  8:34   ` Bin Meng
2021-04-07 13:55 ` [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use Alistair Francis

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