From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: [PATCH v1 0/3] Updates to the OpenTitan machine
Date: Fri, 2 Jul 2021 15:18:35 +1000 [thread overview]
Message-ID: <cover.1625202999.git.alistair.francis@wdc.com> (raw)
Alistair Francis (3):
char: ibex_uart: Update the register layout
hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
hw/riscv: opentitan: Add the flash alias
include/hw/riscv/opentitan.h | 3 +++
hw/char/ibex_uart.c | 19 ++++++++++---------
hw/riscv/opentitan.c | 9 +++++++++
3 files changed, 22 insertions(+), 9 deletions(-)
--
2.31.1
next reply other threads:[~2021-07-02 5:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-02 5:18 Alistair Francis [this message]
2021-07-02 5:19 ` [PATCH v1 1/3] char: ibex_uart: Update the register layout Alistair Francis
2021-07-05 6:16 ` Bin Meng
2021-07-02 5:19 ` [PATCH v1 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-05 6:16 ` Bin Meng
2021-07-02 5:20 ` [PATCH v1 3/3] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-05 6:16 ` Bin Meng
2021-07-06 4:49 ` Alistair Francis
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