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[93.34.153.63]) by smtp.gmail.com with ESMTPSA id j7sm25686965wru.54.2019.06.26.11.29.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 11:29:22 -0700 (PDT) To: Stefan Brankovic , qemu-devel@nongnu.org References: <1560942225-24728-1-git-send-email-stefan.brankovic@rt-rk.com> <1560942225-24728-3-git-send-email-stefan.brankovic@rt-rk.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: Date: Wed, 26 Jun 2019 17:34:16 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1560942225-24728-3-git-send-email-stefan.brankovic@rt-rk.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: Re: [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/19/19 1:03 PM, Stefan Brankovic wrote: > Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt). > Perform shift operation (left and right respectively) on 128 bit value of > register vA by value specified in bits 125-127 of register vB. Lowest 3 > bits in each byte element of register vB must be identical or result is > undefined. > > For vsl instruction, the first step is bits 125-127 of register vB have > to be saved in variable sh. Then, the highest sh bits of the lower > doubleword element of register vA are saved in variable shifted, > in order not to lose those bits when shift operation is performed on > the lower doubleword element of register vA, which is the next > step. After shifting the lower doubleword element shift operation > is performed on higher doubleword element of vA, with replacement of > the lowest sh bits(that are now 0) with bits saved in shifted. > > For vsr instruction, firstly, the bits 125-127 of register vB have > to be saved in variable sh. Then, the lowest sh bits of the higher > doubleword element of register vA are saved in variable shifted, > in odred not to lose those bits when the shift operation is > performed on the higher doubleword element of register vA, which is > the next step. After shifting higher doubleword element, shift operation > is performed on lower doubleword element of vA, with replacement of > highest sh bits(that are now 0) with bits saved in shifted. > > Signed-off-by: Stefan Brankovic > --- > target/ppc/helper.h | 2 - > target/ppc/int_helper.c | 35 ------------- > target/ppc/translate/vmx-impl.inc.c | 99 ++++++++++++++++++++++++++++++++++++- > 3 files changed, 97 insertions(+), 39 deletions(-) Reviewed-by: Richard Henderson r~