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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Alistair Francis <alistair23@gmail.com>,
	Bug 1923629 <1923629@bugs.launchpad.net>,
	Kito Cheng <kito.cheng@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating
Date: Thu, 15 Apr 2021 12:18:22 +0800	[thread overview]
Message-ID: <d8a3da4f-69d5-d254-497b-c2a0397db029@c-sky.com> (raw)
In-Reply-To: <CAKmqyKM7iVth4dzSLgdx6u=V3icoQuFnZ+JeqwUzmvim14BRRg@mail.gmail.com>

Hi Alistair,

I think that this bug has been resolved in my packed-extension patch set[1].

Would you mind to have a test and merge it before the whole patch set?

Thanks.


Best Regards,

Zhiwei

[1]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg782125.html



On 2021/4/15 上午11:57, Alistair Francis wrote:
> + LIU Zhiwei and Kito Cheng
>
> Alistair
>
> On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923629@bugs.launchpad.net> wrote:
>> Public bug reported:
>>
>> I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an
>> incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).
>>
>> Here is the bit of the code:
>>
>>                  vmv.v.i         v16, 0
>>                  …
>> 8f040457        vssub.vv        v8,v16,v8
>>
>> I believe the instruction encoding is correct (vssub.vv with vd = v8,
>> vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.
>>
>> I’ve just tested with what I think is the latest branch (
>> https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb
>> 2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still
>> exists.
>>
>> ** Affects: qemu
>>       Importance: Undecided
>>           Status: New
>>
>>
>> ** Tags: riscv vector
>>
>> --
>> You received this bug notification because you are a member of qemu-
>> devel-ml, which is subscribed to QEMU.
>> https://bugs.launchpad.net/bugs/1923629
>>
>> Title:
>>    RISC-V Vector Instruction vssub.vv not saturating
>>
>> Status in QEMU:
>>    New
>>
>> Bug description:
>>    I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an
>>    incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).
>>
>>    Here is the bit of the code:
>>
>>                  vmv.v.i         v16, 0
>>                  …
>>    8f040457      vssub.vv        v8,v16,v8
>>
>>    I believe the instruction encoding is correct (vssub.vv with vd = v8,
>>    vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.
>>
>>    I’ve just tested with what I think is the latest branch (
>>    https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb
>>    2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still
>>    exists.
>>
>> To manage notifications about this bug go to:
>> https://bugs.launchpad.net/qemu/+bug/1923629/+subscriptions
>>


  parent reply	other threads:[~2021-04-15  4:19 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-13 15:21 [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating Tony Cole
2021-04-15  3:57 ` Alistair Francis
2021-04-15  4:00   ` Kito Cheng
2021-04-15  4:18   ` LIU Zhiwei [this message]
2021-04-15  4:42     ` Alistair Francis
2021-04-15  4:42 ` [Bug 1923629] " Alistair Francis
2021-04-15  7:31 ` Frank Chang
2021-05-12 23:58 ` Alistair Francis
2021-08-25  7:18 ` Thomas Huth

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