From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AC70C433C1 for ; Tue, 23 Mar 2021 18:35:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 87F2061963 for ; Tue, 23 Mar 2021 18:35:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 87F2061963 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lOlsW-0003eg-N2 for qemu-devel@archiver.kernel.org; Tue, 23 Mar 2021 14:35:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lOknn-0003zd-4t for qemu-devel@nongnu.org; Tue, 23 Mar 2021 13:26:47 -0400 Received: from mga18.intel.com ([134.134.136.126]:35204) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lOknj-0003iU-5s for qemu-devel@nongnu.org; Tue, 23 Mar 2021 13:26:46 -0400 IronPort-SDR: fnbVuUPnNVF/GwZN+crrh/03EC/bfP/68lAxH0QtX2ceXBlQluCMFV2vGhihOGkjMNdHhi04uU HvBBEm+JL/cw== X-IronPort-AV: E=McAfee;i="6000,8403,9932"; a="178093239" X-IronPort-AV: E=Sophos;i="5.81,272,1610438400"; d="scan'208";a="178093239" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2021 10:26:37 -0700 IronPort-SDR: cVigCD4kPpFTawqv0u25jxC0q38KtY6+lh/2aFf3oB8Q06hdfTPJx96E8niVZafbR4MtZbwB+h sxKQ9k3Hx+Xg== X-IronPort-AV: E=Sophos;i="5.81,272,1610438400"; d="scan'208";a="607801300" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2021 10:26:36 -0700 From: Isaku Yamahata To: qemu-devel@nongnu.org, mst@redhat.com, peter.maydell@linaro.org, imammedo@redhat.com, f4bug@amsat.org Subject: [PATCH v2 2/3] pci: sprinkle assert in PCI pin number Date: Tue, 23 Mar 2021 10:24:30 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=134.134.136.126; envelope-from=isaku.yamahata@intel.com; helo=mga18.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, Peter Maydell , isaku.yamahata@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" If a device model (a) doesn't set the value to a correct interrupt number and then (b) triggers an interrupt for itself, it's device model bug. Add assert on interrupt pin number to catch this kind of bug more obviously. Suggested-by: Peter Maydell Signed-off-by: Isaku Yamahata --- hw/pci/pci.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index ac9a24889c..cb6bab999b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1450,6 +1450,8 @@ static void pci_irq_handler(void *opaque, int irq_num, int level) PCIDevice *pci_dev = opaque; int change; + assert(0 <= irq_num && irq_num < PCI_NUM_PINS); + assert(level == 0 || level == 1); change = level - pci_irq_state(pci_dev, irq_num); if (!change) return; @@ -1463,7 +1465,13 @@ static void pci_irq_handler(void *opaque, int irq_num, int level) static inline int pci_intx(PCIDevice *pci_dev) { - return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; + int intx = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; + /* + * This function is used to setup/trigger irq. + * So PIN = 0 (interrupt isn't used) doesn't make sense. + */ + assert(0 <= intx && intx < PCI_NUM_PINS); + return intx; } qemu_irq pci_allocate_irq(PCIDevice *pci_dev) -- 2.25.1