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[2.142.241.104]) by smtp.gmail.com with ESMTPSA id e12sm28350712wrq.20.2021.11.10.03.23.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Nov 2021 03:23:41 -0800 (PST) Subject: Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> <20211110070452.48539-13-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: Date: Wed, 10 Nov 2021 12:23:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211110070452.48539-13-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.678, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/10/21 8:04 AM, LIU Zhiwei wrote: > We need not specially process vtype when XLEN changes. > Signed-off-by: LIU Zhiwei > --- > target/riscv/cpu.h | 1 + > target/riscv/csr.c | 15 ++++++++++++++- > target/riscv/machine.c | 1 + > target/riscv/vector_helper.c | 7 ++----- > 4 files changed, 18 insertions(+), 6 deletions(-) This patch should come before patch 6, which is over-complicated. > + target_ulong vill; This could be bool, though there's no good place to slot it that does not result in unused padding. Comments should be added to show that this bit is now missing from vtype. > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 19e982d3f0..cc4dda4b93 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector = { > VMSTATE_UINTTL(env.vl, RISCVCPU), > VMSTATE_UINTTL(env.vstart, RISCVCPU), > VMSTATE_UINTTL(env.vtype, RISCVCPU), > + VMSTATE_UINTTL(env.vill, RISCVCPU), > VMSTATE_END_OF_LIST() This will need a bump to version. > @@ -45,11 +45,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > } > if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { > /* only set vill bit. */ > - if (xlen < TARGET_LONG_BITS) { > - env->vtype = FIELD_DP64(0, VTYPE, VILL_XLEN32, 1); > - } else { > - env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); > - } > + env->vill = 1; > + env->vtype = 0; This is fine. You're missing the updates to cpu_get_tb_cpu_state. r~