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[83.53.161.74]) by smtp.gmail.com with ESMTPSA id f14sm6605477wrv.72.2020.10.03.11.14.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Oct 2020 11:14:16 -0700 (PDT) Subject: Re: [PATCH 04/14] hw/arm/raspi: add a skeleton implementation of the cprman To: Luc Michel References: <20200925101731.2159827-1-luc@lmichel.fr> <20200925101731.2159827-5-luc@lmichel.fr> <85ccb491-8d4a-caf3-595d-7415471f5dc7@amsat.org> <20200928084515.r7s3cl6jlzm465iw@sekoia-pc.home.lmichel.fr> <4aa9f0c3-dc4b-1e87-d601-87b0498de8b1@amsat.org> <20201003115444.m2woqcpit34vfv3u@sekoia-pc.home.lmichel.fr> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sat, 3 Oct 2020 20:14:15 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20201003115444.m2woqcpit34vfv3u@sekoia-pc.home.lmichel.fr> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.252, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Andrew Baumann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/3/20 1:54 PM, Luc Michel wrote: > On 16:37 Fri 02 Oct , Philippe Mathieu-Daudé wrote: > > [snip] > >>>>> +struct BCM2835CprmanState { >>>>> + /*< private >*/ >>>>> + SysBusDevice parent_obj; >>>>> + >>>>> + /*< public >*/ >>>>> + MemoryRegion iomem; >>>>> + >>>>> + uint32_t regs[CPRMAN_NUM_REGS]; >>>>> + uint32_t xosc_freq; >>>>> + >>>>> + Clock *xosc; >> >> Isn't it xosc external to the CPRMAN? >> > Yes on real hardware I'm pretty sure it's the oscillator we can see on > the board itself, near the SoC (on the bottom side). This is how I first > planned to implement it. I then realized that would add complexity to > the BCM2835Peripherals model for no good reasons IMHO (mainly because of > migration). So at the end I put it inside the CPRMAN for simplicity, and > added a property to set its frequency. OK as long as all boards have a 19.2MHz crystal, but if the property is not easily accessible why not use a #define in "hw/arm/raspi_platform.h" instead? Else we should alias the property using object_property_add_alias() in TYPE_BCM2835_PERIPHERALS. > >>>>> +}; > > [snip] > >>>>> +static const MemoryRegionOps cprman_ops = { >>>>> + .read = cprman_read, >>>>> + .write = cprman_write, >>>>> + .endianness = DEVICE_LITTLE_ENDIAN, >>>>> + .valid = { >>>>> + .min_access_size = 4, >>>>> + .max_access_size = 4, >>>> >>>> I couldn't find this in the public datasheets (any pointer?). >>>> >>>> Since your implementation is 32bit, can you explicit .impl >>>> min/max = 4? >>> >>> I could not find this information either, but I assumed this is the >>> case, mainly because of the 'PASSWORD' field in all registers. >> >> Good point. Do you mind adding a comment about it here please? >> > > OK > >>> >>> Regarding .impl, I thought that having .valid was enough? >> >> Until we eventually figure out we can do 64-bit accesses, >> so someone change .valid.max to 8 and your model is broken :/ > > OK, I'll add the .impl constraints. > > [snip] >