* [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
@ 2019-06-19 0:38 Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions Alistair Francis
` (5 more replies)
0 siblings, 6 replies; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 0:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
This is an RFC as it will break ALL current users! See below for details.
This series consolidates the current RISC-V kernel loading
impelementation while also adding support for the -bios option and more
advanced kernel image types.
After consolidating the kernel loading we can extend the boot loader to
support a -bios option. We can also extend the kernel loading options to
support not just ELF files but other standard formats.
Finally we can include the OpenSBI firmware by default for QEMU users.
At the end of this series we are in the good place of no longer
requiring users to build firmware to boot a kernel. Instead users can
just run QEMu with the -kernel option and everything will work. They can
also override the firmware with their own using the -bios option. Using
"-bios none" will result in no firmware being loaded (as it is today).
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Unfortunately this series (patch 5 specifically) results in all current
Linux boots being broken as users are already loading in their own
firmware, which overlaps with the now included default. They will
see this error:
rom: requested regions overlap (rom phdr #0: ./images/qemuriscv64/fw_jump.elf. free=0x0000000080008090, addr=0x0000000080000000)
qemu-system-riscv64: rom check and register reset failed
If a current user specieifies "-bios none" their flow will continue
working. A user can instead no longer load their firmware and
use the default or they can load their firmware with the -bios option.
At the moment the best idea I have to not break all users is to only
include the default firmware if the user specifies "-bios opensbi".
That is change the default to not loading the firmware. Then we can work
on updating documentation and maybe in future change the default to
include a firmware and anyone who doesn't want a default firmware can
specify "-bios none".
Any other ideas on how to not break everything?
Alistair Francis (5):
hw/riscv: Split out the boot functions
hw/riscv: Add support for loading a firmware
hw/riscv: Extend the kernel loading support
roms: Add OpenSBI version 0.3
hw/riscv: Load OpenSBI as the default firmware
.gitmodules | 3 +
Makefile | 3 +-
configure | 1 +
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c | 143 ++++++++++++++++++++++++++++
hw/riscv/sifive_e.c | 17 +---
hw/riscv/sifive_u.c | 19 +---
hw/riscv/spike.c | 21 +---
hw/riscv/virt.c | 54 ++---------
include/hw/riscv/boot.h | 30 ++++++
pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
roms/Makefile | 17 ++++
roms/opensbi | 1 +
14 files changed, 216 insertions(+), 94 deletions(-)
create mode 100644 hw/riscv/boot.c
create mode 100644 include/hw/riscv/boot.h
create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
create mode 160000 roms/opensbi
--
2.22.0
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
@ 2019-06-19 0:38 ` Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware Alistair Francis
` (4 subsequent siblings)
5 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 0:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c | 69 +++++++++++++++++++++++++++++++++++++++++
hw/riscv/sifive_e.c | 17 ++--------
hw/riscv/sifive_u.c | 17 ++--------
hw/riscv/spike.c | 21 +++----------
hw/riscv/virt.c | 51 +++---------------------------
include/hw/riscv/boot.h | 27 ++++++++++++++++
7 files changed, 110 insertions(+), 93 deletions(-)
create mode 100644 hw/riscv/boot.c
create mode 100644 include/hw/riscv/boot.h
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index a65027304a..eb9d4f9ffc 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -1,3 +1,4 @@
+obj-y += boot.o
obj-$(CONFIG_SPIKE) += riscv_htif.o
obj-$(CONFIG_HART) += riscv_hart.o
obj-$(CONFIG_SIFIVE_E) += sifive_e.o
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
new file mode 100644
index 0000000000..62f94aaf8a
--- /dev/null
+++ b/hw/riscv/boot.c
@@ -0,0 +1,69 @@
+/*
+ * QEMU RISC-V Boot Helper
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/error-report.h"
+#include "exec/cpu-defs.h"
+#include "hw/loader.h"
+#include "hw/riscv/boot.h"
+#include "elf.h"
+
+target_ulong riscv_load_kernel(const char *kernel_filename)
+{
+ uint64_t kernel_entry, kernel_high;
+
+ if (load_elf(kernel_filename, NULL, NULL, NULL,
+ &kernel_entry, NULL, &kernel_high,
+ 0, EM_RISCV, 1, 0) < 0) {
+ error_report("could not load kernel '%s'", kernel_filename);
+ exit(1);
+ }
+
+ return kernel_entry;
+}
+
+hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
+ uint64_t kernel_entry, hwaddr *start)
+{
+ int size;
+
+ /* We want to put the initrd far enough into RAM that when the
+ * kernel is uncompressed it will not clobber the initrd. However
+ * on boards without much RAM we must ensure that we still leave
+ * enough room for a decent sized initrd, and on boards with large
+ * amounts of RAM we must avoid the initrd being so far up in RAM
+ * that it is outside lowmem and inaccessible to the kernel.
+ * So for boards with less than 256MB of RAM we put the initrd
+ * halfway into RAM, and for boards with 256MB of RAM or more we put
+ * the initrd at 128MB.
+ */
+ *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+
+ size = load_ramdisk(filename, *start, mem_size - *start);
+ if (size == -1) {
+ size = load_image_targphys(filename, *start, mem_size - *start);
+ if (size == -1) {
+ error_report("could not load ramdisk '%s'", filename);
+ exit(1);
+ }
+ }
+
+ return *start + size;
+}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 80ac56fa7d..9d58ae362b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -44,10 +44,10 @@
#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
+#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "exec/address-spaces.h"
-#include "elf.h"
static const struct MemmapEntry {
hwaddr base;
@@ -74,19 +74,6 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static target_ulong load_kernel(const char *kernel_filename)
-{
- uint64_t kernel_entry, kernel_high;
-
- if (load_elf(kernel_filename, NULL, NULL, NULL,
- &kernel_entry, NULL, &kernel_high,
- 0, EM_RISCV, 1, 0) < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
- return kernel_entry;
-}
-
static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
uintptr_t offset, uintptr_t length)
{
@@ -131,7 +118,7 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
- load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine->kernel_filename);
}
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ecc47cea3..1b9281bd4a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -41,11 +41,11 @@
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
+#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
-#include "elf.h"
#include <libfdt.h>
@@ -65,19 +65,6 @@ static const struct MemmapEntry {
#define GEM_REVISION 0x10070109
-static target_ulong load_kernel(const char *kernel_filename)
-{
- uint64_t kernel_entry, kernel_high;
-
- if (load_elf(kernel_filename, NULL, NULL, NULL,
- &kernel_entry, NULL, &kernel_high,
- 0, EM_RISCV, 1, 0) < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
- return kernel_entry;
-}
-
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
uint64_t mem_size, const char *cmdline)
{
@@ -280,7 +267,7 @@ static void riscv_sifive_u_init(MachineState *machine)
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
if (machine->kernel_filename) {
- load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine->kernel_filename);
}
/* reset vector */
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 5b33d4be3b..e68be00a5f 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -36,12 +36,12 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/spike.h"
+#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
-#include "elf.h"
#include <libfdt.h>
@@ -54,19 +54,6 @@ static const struct MemmapEntry {
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
-static target_ulong load_kernel(const char *kernel_filename)
-{
- uint64_t kernel_entry, kernel_high;
-
- if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
- &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0,
- NULL, true, htif_symbol_callback) < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
- return kernel_entry;
-}
-
static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
uint64_t mem_size, const char *cmdline)
{
@@ -199,7 +186,7 @@ static void spike_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
- load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine->kernel_filename);
}
/* reset vector */
@@ -287,7 +274,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
- load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine->kernel_filename);
}
/* reset vector */
@@ -372,7 +359,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
- load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine->kernel_filename);
}
/* reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42..5f8c11471b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -34,13 +34,13 @@
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
+#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
-#include "elf.h"
#include <libfdt.h>
@@ -61,47 +61,6 @@ static const struct MemmapEntry {
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
};
-static target_ulong load_kernel(const char *kernel_filename)
-{
- uint64_t kernel_entry, kernel_high;
-
- if (load_elf(kernel_filename, NULL, NULL, NULL,
- &kernel_entry, NULL, &kernel_high,
- 0, EM_RISCV, 1, 0) < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
- return kernel_entry;
-}
-
-static hwaddr load_initrd(const char *filename, uint64_t mem_size,
- uint64_t kernel_entry, hwaddr *start)
-{
- int size;
-
- /* We want to put the initrd far enough into RAM that when the
- * kernel is uncompressed it will not clobber the initrd. However
- * on boards without much RAM we must ensure that we still leave
- * enough room for a decent sized initrd, and on boards with large
- * amounts of RAM we must avoid the initrd being so far up in RAM
- * that it is outside lowmem and inaccessible to the kernel.
- * So for boards with less than 256MB of RAM we put the initrd
- * halfway into RAM, and for boards with 256MB of RAM or more we put
- * the initrd at 128MB.
- */
- *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
-
- size = load_ramdisk(filename, *start, mem_size - *start);
- if (size == -1) {
- size = load_image_targphys(filename, *start, mem_size - *start);
- if (size == -1) {
- error_report("could not load ramdisk '%s'", filename);
- exit(1);
- }
- }
- return *start + size;
-}
-
static void create_pcie_irq_map(void *fdt, char *nodename,
uint32_t plic_phandle)
{
@@ -422,13 +381,13 @@ static void riscv_virt_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
- uint64_t kernel_entry = load_kernel(machine->kernel_filename);
+ uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
if (machine->initrd_filename) {
hwaddr start;
- hwaddr end = load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
- &start);
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
qemu_fdt_setprop_cell(fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
new file mode 100644
index 0000000000..f84fd6c2df
--- /dev/null
+++ b/include/hw/riscv/boot.h
@@ -0,0 +1,27 @@
+/*
+ * QEMU RISC-V Boot Helper
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_BOOT_H
+#define RISCV_BOOT_H
+
+target_ulong riscv_load_kernel(const char *kernel_filename);
+hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
+ uint64_t kernel_entry, hwaddr *start);
+
+#endif /* RISCV_BOOT_H */
--
2.22.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions Alistair Francis
@ 2019-06-19 0:38 ` Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support Alistair Francis
` (3 subsequent siblings)
5 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 0:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:
qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 41 +++++++++++++++++++++++++++++++++++++++--
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 6 +++++-
hw/riscv/spike.c | 6 +++---
hw/riscv/virt.c | 7 ++++++-
include/hw/riscv/boot.h | 4 +++-
6 files changed, 57 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 62f94aaf8a..392ca0cb2e 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -23,13 +23,50 @@
#include "exec/cpu-defs.h"
#include "hw/loader.h"
#include "hw/riscv/boot.h"
+#include "hw/boards.h"
#include "elf.h"
-target_ulong riscv_load_kernel(const char *kernel_filename)
+#if defined(TARGET_RISCV32)
+# define KERNEL_BOOT_ADDRESS 0x80400000
+#else
+# define KERNEL_BOOT_ADDRESS 0x80200000
+#endif
+
+static uint64_t kernel_translate(void *opaque, uint64_t addr)
+{
+ MachineState *machine = opaque;
+
+ /*
+ * If the user specified a firmware move the kernel to the offset
+ * start address.
+ */
+ if (machine->firmware) {
+ return (addr & 0x7fffffff) + KERNEL_BOOT_ADDRESS;
+ } else {
+ return addr;
+ }
+}
+
+target_ulong riscv_load_firmware(const char *firmware_filename)
+{
+ uint64_t firmware_entry, firmware_start, firmware_end;
+
+ if (load_elf(firmware_filename, NULL, NULL, NULL,
+ &firmware_entry, &firmware_start, &firmware_end,
+ 0, EM_RISCV, 1, 0) < 0) {
+ error_report("could not load firmware '%s'", firmware_filename);
+ exit(1);
+ }
+
+ return firmware_entry;
+}
+
+target_ulong riscv_load_kernel(MachineState *machine,
+ const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, NULL, NULL, NULL,
+ if (load_elf(kernel_filename, NULL, kernel_translate, machine,
&kernel_entry, NULL, &kernel_high,
0, EM_RISCV, 1, 0) < 0) {
error_report("could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 9d58ae362b..3695c686be 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -118,7 +118,7 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine, machine->kernel_filename);
}
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1b9281bd4a..03a6c64d04 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -266,8 +266,12 @@ static void riscv_sifive_u_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+ if (machine->firmware) {
+ riscv_load_firmware(machine->firmware);
+ }
+
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine, machine->kernel_filename);
}
/* reset vector */
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index e68be00a5f..81cef0dcea 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -186,7 +186,7 @@ static void spike_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine, machine->kernel_filename);
}
/* reset vector */
@@ -274,7 +274,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine, machine->kernel_filename);
}
/* reset vector */
@@ -359,7 +359,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
mask_rom);
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename);
+ riscv_load_kernel(machine, machine->kernel_filename);
}
/* reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5f8c11471b..d3670b5a7c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -380,8 +380,13 @@ static void riscv_virt_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
+ if (machine->firmware) {
+ riscv_load_firmware(machine->firmware);
+ }
+
if (machine->kernel_filename) {
- uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
+ uint64_t kernel_entry = riscv_load_kernel(machine,
+ machine->kernel_filename);
if (machine->initrd_filename) {
hwaddr start;
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f84fd6c2df..6f586939c7 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -20,7 +20,9 @@
#ifndef RISCV_BOOT_H
#define RISCV_BOOT_H
-target_ulong riscv_load_kernel(const char *kernel_filename);
+target_ulong riscv_load_firmware(const char *firmware_filename);
+target_ulong riscv_load_kernel(MachineState *machine,
+ const char *kernel_filename);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
--
2.22.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware Alistair Francis
@ 2019-06-19 0:38 ` Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3 Alistair Francis
` (2 subsequent siblings)
5 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 0:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Extend the RISC-V kernel loader to support uImage and Image files.
A Linux kernel can now be booted with:
qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel Image
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 392ca0cb2e..7f68035a3f 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -67,13 +67,22 @@ target_ulong riscv_load_kernel(MachineState *machine,
uint64_t kernel_entry, kernel_high;
if (load_elf(kernel_filename, NULL, kernel_translate, machine,
- &kernel_entry, NULL, &kernel_high,
- 0, EM_RISCV, 1, 0) < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
+ &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) {
+ return kernel_entry;
+ }
+
+ if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
+ kernel_translate, machine, NULL) > 0) {
+ return kernel_entry;
+ }
+
+ if (load_image_targphys_as(kernel_filename, KERNEL_BOOT_ADDRESS,
+ ram_size, NULL) > 0) {
+ return kernel_entry;
}
- return kernel_entry;
+ error_report("could not load kernel '%s'", kernel_filename);
+ exit(1);
}
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
--
2.22.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
` (2 preceding siblings ...)
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support Alistair Francis
@ 2019-06-19 0:38 ` Alistair Francis
2019-06-19 5:14 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware Alistair Francis
2019-06-19 14:26 ` [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Bin Meng
5 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 0:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
.gitmodules | 3 +++
Makefile | 3 ++-
configure | 1 +
pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
roms/Makefile | 17 +++++++++++++++++
roms/opensbi | 1 +
7 files changed, 24 insertions(+), 1 deletion(-)
create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
create mode 160000 roms/opensbi
diff --git a/.gitmodules b/.gitmodules
index 2857eec763..7a10e72e09 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -55,3 +55,6 @@
[submodule "slirp"]
path = slirp
url = https://git.qemu.org/git/libslirp.git
+[submodule "roms/opensbi"]
+ path = roms/opensbi
+ url = https://github.com/riscv/opensbi.git
diff --git a/Makefile b/Makefile
index cfb18f1525..fb6638f9ec 100644
--- a/Makefile
+++ b/Makefile
@@ -761,7 +761,8 @@ palcode-clipper \
u-boot.e500 u-boot-sam460-20100605.bin \
qemu_vga.ndrv \
edk2-licenses.txt \
-hppa-firmware.img
+hppa-firmware.img \
+opensbi-riscv32-fw_jump.elf opensbi-riscv64-fw_jump.elf
DESCS=50-edk2-i386-secure.json 50-edk2-x86_64-secure.json \
60-edk2-aarch64.json 60-edk2-arm.json 60-edk2-i386.json 60-edk2-x86_64.json
diff --git a/configure b/configure
index b091b82cb3..75372a7b4f 100755
--- a/configure
+++ b/configure
@@ -7936,6 +7936,7 @@ for bios_file in \
$source_path/pc-bios/*.rom \
$source_path/pc-bios/*.dtb \
$source_path/pc-bios/*.img \
+ $source_path/pc-bios/*.elf \
$source_path/pc-bios/openbios-* \
$source_path/pc-bios/u-boot.* \
$source_path/pc-bios/edk2-*.fd.bz2 \
diff --git a/pc-bios/opensbi-riscv32-fw_jump.elf b/pc-bios/opensbi-riscv32-fw_jump.elf
new file mode 100644
index 0000000000000000000000000000000000000000..e526b03eaad419953831f2114ea3aa0fdcc1924b
GIT binary patch
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diff --git a/pc-bios/opensbi-riscv64-fw_jump.elf b/pc-bios/opensbi-riscv64-fw_jump.elf
new file mode 100644
index 0000000000000000000000000000000000000000..f5926c1d80d8b82be68ac0e194b475e410d8b5ac
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HcmV?d00001
diff --git a/roms/Makefile b/roms/Makefile
index 078d3fb705..f79220791c 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -37,6 +37,8 @@ find-cross-prefix = $(subst gcc,,$(notdir $(call find-cross-gcc,$(1))))
powerpc64_cross_prefix := $(call find-cross-prefix,powerpc64)
powerpc_cross_prefix := $(call find-cross-prefix,powerpc)
x86_64_cross_prefix := $(call find-cross-prefix,x86_64)
+riscv32_cross_prefix := $(call find-cross-prefix,riscv32)
+riscv64_cross_prefix := $(call find-cross-prefix,riscv64)
# tag our seabios builds
SEABIOS_EXTRAVERSION="-prebuilt.qemu.org"
@@ -62,6 +64,8 @@ default:
@echo " u-boot.e500 -- update u-boot.e500"
@echo " u-boot.sam460 -- update u-boot.sam460"
@echo " efi -- update UEFI (edk2) platform firmware"
+ @echo " opensbi32 -- update OpenSBI for 32-bit"
+ @echo " opensbi64 -- update OpenSBI for 64-bit"
@echo " clean -- delete the files generated by the previous" \
"build targets"
@@ -162,6 +166,18 @@ skiboot:
efi: edk2-basetools
$(MAKE) -f Makefile.edk2
+opensbi32:
+ $(MAKE) -C opensbi \
+ CROSS_COMPILE=$(riscv32_cross_prefix) \
+ PLATFORM="qemu/virt"
+ cp opensbi/build/platform/qemu/virt/firmware/fw_jump.elf ../pc-bios/opensbi-riscv32-fw_jump.elf
+
+opensbi64:
+ $(MAKE) -C opensbi \
+ CROSS_COMPILE=$(riscv64_cross_prefix) \
+ PLATFORM="qemu/virt"
+ cp opensbi/build/platform/qemu/virt/firmware/fw_jump.elf ../pc-bios/opensbi-riscv64-fw_jump.elf
+
clean:
rm -rf seabios/.config seabios/out seabios/builds
$(MAKE) -C sgabios clean
@@ -173,3 +189,4 @@ clean:
$(MAKE) -C u-boot-sam460ex distclean
$(MAKE) -C skiboot clean
$(MAKE) -f Makefile.edk2 clean
+ $(MAKE) -C opensbi clean
diff --git a/roms/opensbi b/roms/opensbi
new file mode 160000
index 0000000000..ca20ac0cd4
--- /dev/null
+++ b/roms/opensbi
@@ -0,0 +1 @@
+Subproject commit ca20ac0cd4c099006d4eea4d9ac7bd7b58e2ae0f
--
2.22.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
` (3 preceding siblings ...)
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3 Alistair Francis
@ 2019-06-19 0:38 ` Alistair Francis
2019-06-19 5:16 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-06-19 14:26 ` [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Bin Meng
5 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 0:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
If the user hasn't specified a firmware to load (with -bios) or
specified no bios (with -bios none) then load OpenSBI by default. This
allows users to boot a RISC-V kernel with just -kernel.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 28 ++++++++++++++++++++++++++++
hw/riscv/sifive_u.c | 4 +---
hw/riscv/virt.c | 4 +---
include/hw/riscv/boot.h | 1 +
4 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 7f68035a3f..5f021591ed 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu-common.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "exec/cpu-defs.h"
@@ -32,6 +33,12 @@
# define KERNEL_BOOT_ADDRESS 0x80200000
#endif
+#if defined(TARGET_RISCV32)
+# define BIOS_FILENAME "opensbi-riscv32-fw_jump.elf"
+#else
+# define BIOS_FILENAME "opensbi-riscv64-fw_jump.elf"
+#endif
+
static uint64_t kernel_translate(void *opaque, uint64_t addr)
{
MachineState *machine = opaque;
@@ -47,6 +54,27 @@ static uint64_t kernel_translate(void *opaque, uint64_t addr)
}
}
+void riscv_find_and_load_firmware(MachineState *machine)
+{
+ char *firmware_filename;
+
+ if (!machine->firmware) {
+ /* The user didn't specify a firmware, default to OpenSBI */
+ firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BIOS_FILENAME);
+ } else {
+ firmware_filename = machine->firmware;
+ }
+
+ if (strcmp(firmware_filename, "none")) {
+ /* If not "none" load the firmware */
+ riscv_load_firmware(firmware_filename);
+ }
+
+ if (!machine->firmware) {
+ g_free(firmware_filename);
+ }
+}
+
target_ulong riscv_load_firmware(const char *firmware_filename)
{
uint64_t firmware_entry, firmware_start, firmware_end;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 03a6c64d04..77666d0f4d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -266,9 +266,7 @@ static void riscv_sifive_u_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
- if (machine->firmware) {
- riscv_load_firmware(machine->firmware);
- }
+ riscv_find_and_load_firmware(machine);
if (machine->kernel_filename) {
riscv_load_kernel(machine, machine->kernel_filename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d3670b5a7c..2a7e850666 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -380,9 +380,7 @@ static void riscv_virt_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
- if (machine->firmware) {
- riscv_load_firmware(machine->firmware);
- }
+ riscv_find_and_load_firmware(machine);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine,
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 6f586939c7..df2e2480e6 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -20,6 +20,7 @@
#ifndef RISCV_BOOT_H
#define RISCV_BOOT_H
+void riscv_find_and_load_firmware(MachineState *machine);
target_ulong riscv_load_firmware(const char *firmware_filename);
target_ulong riscv_load_kernel(MachineState *machine,
const char *kernel_filename);
--
2.22.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3 Alistair Francis
@ 2019-06-19 5:14 ` Anup Patel
2019-06-19 15:18 ` Bin Meng
0 siblings, 1 reply; 30+ messages in thread
From: Anup Patel @ 2019-06-19 5:14 UTC (permalink / raw)
To: Alistair Francis; +Cc: alistair23, Palmer Dabbelt, qemu-riscv, QEMU Developers
On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> .gitmodules | 3 +++
> Makefile | 3 ++-
> configure | 1 +
> pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> roms/Makefile | 17 +++++++++++++++++
> roms/opensbi | 1 +
> 7 files changed, 24 insertions(+), 1 deletion(-)
> create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
> create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
> create mode 160000 roms/opensbi
>
The OpenSBI firmwares are platform specific so we should have
machine directory under pc-bios/ directory
So for virt machine we will have:
pc-bios/riscv32/virt/fw_jump.elf
pc-bios/riscv64/virt/fw_jump.elf
Regards,
Anup
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware Alistair Francis
@ 2019-06-19 5:16 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2019-06-19 5:16 UTC (permalink / raw)
To: Alistair Francis; +Cc: alistair23, Palmer Dabbelt, qemu-riscv, QEMU Developers
On Wed, Jun 19, 2019 at 6:21 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> If the user hasn't specified a firmware to load (with -bios) or
> specified no bios (with -bios none) then load OpenSBI by default. This
> allows users to boot a RISC-V kernel with just -kernel.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/boot.c | 28 ++++++++++++++++++++++++++++
> hw/riscv/sifive_u.c | 4 +---
> hw/riscv/virt.c | 4 +---
> include/hw/riscv/boot.h | 1 +
> 4 files changed, 31 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 7f68035a3f..5f021591ed 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -18,6 +18,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu-common.h"
> #include "qemu/units.h"
> #include "qemu/error-report.h"
> #include "exec/cpu-defs.h"
> @@ -32,6 +33,12 @@
> # define KERNEL_BOOT_ADDRESS 0x80200000
> #endif
>
> +#if defined(TARGET_RISCV32)
> +# define BIOS_FILENAME "opensbi-riscv32-fw_jump.elf"
> +#else
> +# define BIOS_FILENAME "opensbi-riscv64-fw_jump.elf"
> +#endif
Based on my comment on PATCH4, BIOS_FILENAME should
be derived from QEMU machine name and TARGET_RISCVx
Agree ??
Regards,
Anup
> +
> static uint64_t kernel_translate(void *opaque, uint64_t addr)
> {
> MachineState *machine = opaque;
> @@ -47,6 +54,27 @@ static uint64_t kernel_translate(void *opaque, uint64_t addr)
> }
> }
>
> +void riscv_find_and_load_firmware(MachineState *machine)
> +{
> + char *firmware_filename;
> +
> + if (!machine->firmware) {
> + /* The user didn't specify a firmware, default to OpenSBI */
> + firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BIOS_FILENAME);
> + } else {
> + firmware_filename = machine->firmware;
> + }
> +
> + if (strcmp(firmware_filename, "none")) {
> + /* If not "none" load the firmware */
> + riscv_load_firmware(firmware_filename);
> + }
> +
> + if (!machine->firmware) {
> + g_free(firmware_filename);
> + }
> +}
> +
> target_ulong riscv_load_firmware(const char *firmware_filename)
> {
> uint64_t firmware_entry, firmware_start, firmware_end;
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 03a6c64d04..77666d0f4d 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -266,9 +266,7 @@ static void riscv_sifive_u_init(MachineState *machine)
> /* create device tree */
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> - if (machine->firmware) {
> - riscv_load_firmware(machine->firmware);
> - }
> + riscv_find_and_load_firmware(machine);
>
> if (machine->kernel_filename) {
> riscv_load_kernel(machine, machine->kernel_filename);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index d3670b5a7c..2a7e850666 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -380,9 +380,7 @@ static void riscv_virt_board_init(MachineState *machine)
> memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
> mask_rom);
>
> - if (machine->firmware) {
> - riscv_load_firmware(machine->firmware);
> - }
> + riscv_find_and_load_firmware(machine);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine,
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index 6f586939c7..df2e2480e6 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -20,6 +20,7 @@
> #ifndef RISCV_BOOT_H
> #define RISCV_BOOT_H
>
> +void riscv_find_and_load_firmware(MachineState *machine);
> target_ulong riscv_load_firmware(const char *firmware_filename);
> target_ulong riscv_load_kernel(MachineState *machine,
> const char *kernel_filename);
> --
> 2.22.0
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
` (4 preceding siblings ...)
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware Alistair Francis
@ 2019-06-19 14:26 ` Bin Meng
2019-06-19 14:29 ` Alistair Francis
5 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-19 14:26 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> This is an RFC as it will break ALL current users! See below for details.
>
> This series consolidates the current RISC-V kernel loading
> impelementation while also adding support for the -bios option and more
> advanced kernel image types.
>
> After consolidating the kernel loading we can extend the boot loader to
> support a -bios option. We can also extend the kernel loading options to
> support not just ELF files but other standard formats.
>
> Finally we can include the OpenSBI firmware by default for QEMU users.
>
> At the end of this series we are in the good place of no longer
> requiring users to build firmware to boot a kernel. Instead users can
> just run QEMu with the -kernel option and everything will work. They can
This is great. I like booting kernel directly for testing without
bothering the firmware stuff.
> also override the firmware with their own using the -bios option. Using
> "-bios none" will result in no firmware being loaded (as it is today).
>
> !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
>
> Unfortunately this series (patch 5 specifically) results in all current
> Linux boots being broken as users are already loading in their own
> firmware, which overlaps with the now included default. They will
> see this error:
>
> rom: requested regions overlap (rom phdr #0: ./images/qemuriscv64/fw_jump.elf. free=0x0000000080008090, addr=0x0000000080000000)
> qemu-system-riscv64: rom check and register reset failed
>
> If a current user specieifies "-bios none" their flow will continue
> working. A user can instead no longer load their firmware and
> use the default or they can load their firmware with the -bios option.
>
> At the moment the best idea I have to not break all users is to only
> include the default firmware if the user specifies "-bios opensbi".
> That is change the default to not loading the firmware. Then we can work
> on updating documentation and maybe in future change the default to
> include a firmware and anyone who doesn't want a default firmware can
> specify "-bios none".
>
> Any other ideas on how to not break everything?
>
>
>
> Alistair Francis (5):
> hw/riscv: Split out the boot functions
> hw/riscv: Add support for loading a firmware
> hw/riscv: Extend the kernel loading support
> roms: Add OpenSBI version 0.3
> hw/riscv: Load OpenSBI as the default firmware
>
> .gitmodules | 3 +
> Makefile | 3 +-
> configure | 1 +
> hw/riscv/Makefile.objs | 1 +
> hw/riscv/boot.c | 143 ++++++++++++++++++++++++++++
> hw/riscv/sifive_e.c | 17 +---
> hw/riscv/sifive_u.c | 19 +---
> hw/riscv/spike.c | 21 +---
> hw/riscv/virt.c | 54 ++---------
> include/hw/riscv/boot.h | 30 ++++++
> pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
Since we are considering adding "bios" images, I prefer to add the
pure binary images instead of ELF images here.
> roms/Makefile | 17 ++++
> roms/opensbi | 1 +
> 14 files changed, 216 insertions(+), 94 deletions(-)
> create mode 100644 hw/riscv/boot.c
> create mode 100644 include/hw/riscv/boot.h
> create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
> create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
> create mode 160000 roms/opensbi
Regards,
Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-19 14:26 ` [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Bin Meng
@ 2019-06-19 14:29 ` Alistair Francis
2019-06-19 14:42 ` Bin Meng
0 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 14:29 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > This is an RFC as it will break ALL current users! See below for details.
> >
> > This series consolidates the current RISC-V kernel loading
> > impelementation while also adding support for the -bios option and more
> > advanced kernel image types.
> >
> > After consolidating the kernel loading we can extend the boot loader to
> > support a -bios option. We can also extend the kernel loading options to
> > support not just ELF files but other standard formats.
> >
> > Finally we can include the OpenSBI firmware by default for QEMU users.
> >
> > At the end of this series we are in the good place of no longer
> > requiring users to build firmware to boot a kernel. Instead users can
> > just run QEMu with the -kernel option and everything will work. They can
>
> This is great. I like booting kernel directly for testing without
> bothering the firmware stuff.
That's the goal! Now we just need to not break everything.
>
> > also override the firmware with their own using the -bios option. Using
> > "-bios none" will result in no firmware being loaded (as it is today).
> >
> > !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
> >
> > Unfortunately this series (patch 5 specifically) results in all current
> > Linux boots being broken as users are already loading in their own
> > firmware, which overlaps with the now included default. They will
> > see this error:
> >
> > rom: requested regions overlap (rom phdr #0: ./images/qemuriscv64/fw_jump.elf. free=0x0000000080008090, addr=0x0000000080000000)
> > qemu-system-riscv64: rom check and register reset failed
> >
> > If a current user specieifies "-bios none" their flow will continue
> > working. A user can instead no longer load their firmware and
> > use the default or they can load their firmware with the -bios option.
> >
> > At the moment the best idea I have to not break all users is to only
> > include the default firmware if the user specifies "-bios opensbi".
> > That is change the default to not loading the firmware. Then we can work
> > on updating documentation and maybe in future change the default to
> > include a firmware and anyone who doesn't want a default firmware can
> > specify "-bios none".
> >
> > Any other ideas on how to not break everything?
> >
> >
> >
> > Alistair Francis (5):
> > hw/riscv: Split out the boot functions
> > hw/riscv: Add support for loading a firmware
> > hw/riscv: Extend the kernel loading support
> > roms: Add OpenSBI version 0.3
> > hw/riscv: Load OpenSBI as the default firmware
> >
> > .gitmodules | 3 +
> > Makefile | 3 +-
> > configure | 1 +
> > hw/riscv/Makefile.objs | 1 +
> > hw/riscv/boot.c | 143 ++++++++++++++++++++++++++++
> > hw/riscv/sifive_e.c | 17 +---
> > hw/riscv/sifive_u.c | 19 +---
> > hw/riscv/spike.c | 21 +---
> > hw/riscv/virt.c | 54 ++---------
> > include/hw/riscv/boot.h | 30 ++++++
> > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
>
> Since we are considering adding "bios" images, I prefer to add the
> pure binary images instead of ELF images here.
I didn't think about that. Can we just boot them in QEMU like we do
with the ELFs?
Alistair
>
> > roms/Makefile | 17 ++++
> > roms/opensbi | 1 +
> > 14 files changed, 216 insertions(+), 94 deletions(-)
> > create mode 100644 hw/riscv/boot.c
> > create mode 100644 include/hw/riscv/boot.h
> > create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
> > create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
> > create mode 160000 roms/opensbi
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-19 14:29 ` Alistair Francis
@ 2019-06-19 14:42 ` Bin Meng
2019-06-19 18:23 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-19 14:42 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 10:30 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis
> > <alistair.francis@wdc.com> wrote:
> > >
> > > This is an RFC as it will break ALL current users! See below for details.
> > >
> > > This series consolidates the current RISC-V kernel loading
> > > impelementation while also adding support for the -bios option and more
> > > advanced kernel image types.
> > >
> > > After consolidating the kernel loading we can extend the boot loader to
> > > support a -bios option. We can also extend the kernel loading options to
> > > support not just ELF files but other standard formats.
> > >
> > > Finally we can include the OpenSBI firmware by default for QEMU users.
> > >
> > > At the end of this series we are in the good place of no longer
> > > requiring users to build firmware to boot a kernel. Instead users can
> > > just run QEMu with the -kernel option and everything will work. They can
> >
> > This is great. I like booting kernel directly for testing without
> > bothering the firmware stuff.
>
> That's the goal! Now we just need to not break everything.
>
> >
> > > also override the firmware with their own using the -bios option. Using
> > > "-bios none" will result in no firmware being loaded (as it is today).
> > >
> > > !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
> > >
> > > Unfortunately this series (patch 5 specifically) results in all current
> > > Linux boots being broken as users are already loading in their own
> > > firmware, which overlaps with the now included default. They will
> > > see this error:
> > >
> > > rom: requested regions overlap (rom phdr #0: ./images/qemuriscv64/fw_jump.elf. free=0x0000000080008090, addr=0x0000000080000000)
> > > qemu-system-riscv64: rom check and register reset failed
> > >
> > > If a current user specieifies "-bios none" their flow will continue
> > > working. A user can instead no longer load their firmware and
> > > use the default or they can load their firmware with the -bios option.
> > >
> > > At the moment the best idea I have to not break all users is to only
> > > include the default firmware if the user specifies "-bios opensbi".
> > > That is change the default to not loading the firmware. Then we can work
> > > on updating documentation and maybe in future change the default to
> > > include a firmware and anyone who doesn't want a default firmware can
> > > specify "-bios none".
> > >
> > > Any other ideas on how to not break everything?
> > >
> > >
> > >
> > > Alistair Francis (5):
> > > hw/riscv: Split out the boot functions
> > > hw/riscv: Add support for loading a firmware
> > > hw/riscv: Extend the kernel loading support
> > > roms: Add OpenSBI version 0.3
> > > hw/riscv: Load OpenSBI as the default firmware
> > >
> > > .gitmodules | 3 +
> > > Makefile | 3 +-
> > > configure | 1 +
> > > hw/riscv/Makefile.objs | 1 +
> > > hw/riscv/boot.c | 143 ++++++++++++++++++++++++++++
> > > hw/riscv/sifive_e.c | 17 +---
> > > hw/riscv/sifive_u.c | 19 +---
> > > hw/riscv/spike.c | 21 +---
> > > hw/riscv/virt.c | 54 ++---------
> > > include/hw/riscv/boot.h | 30 ++++++
> > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> >
> > Since we are considering adding "bios" images, I prefer to add the
> > pure binary images instead of ELF images here.
>
> I didn't think about that. Can we just boot them in QEMU like we do
> with the ELFs?
Yes, use load_image_targphys() instead of load_elf().
Regards,
Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions Alistair Francis
@ 2019-06-19 15:16 ` Bin Meng
2019-06-19 18:24 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-19 15:16 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 8:51 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Split the common RISC-V boot functions into a seperate file. This allows
> us to share the common code.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/Makefile.objs | 1 +
> hw/riscv/boot.c | 69 +++++++++++++++++++++++++++++++++++++++++
> hw/riscv/sifive_e.c | 17 ++--------
> hw/riscv/sifive_u.c | 17 ++--------
> hw/riscv/spike.c | 21 +++----------
> hw/riscv/virt.c | 51 +++---------------------------
> include/hw/riscv/boot.h | 27 ++++++++++++++++
> 7 files changed, 110 insertions(+), 93 deletions(-)
> create mode 100644 hw/riscv/boot.c
> create mode 100644 include/hw/riscv/boot.h
>
> diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> index a65027304a..eb9d4f9ffc 100644
> --- a/hw/riscv/Makefile.objs
> +++ b/hw/riscv/Makefile.objs
> @@ -1,3 +1,4 @@
> +obj-y += boot.o
> obj-$(CONFIG_SPIKE) += riscv_htif.o
> obj-$(CONFIG_HART) += riscv_hart.o
> obj-$(CONFIG_SIFIVE_E) += sifive_e.o
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> new file mode 100644
> index 0000000000..62f94aaf8a
> --- /dev/null
> +++ b/hw/riscv/boot.c
> @@ -0,0 +1,69 @@
> +/*
> + * QEMU RISC-V Boot Helper
> + *
> + * Copyright (c) 2017 SiFive, Inc.
> + * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "qemu/error-report.h"
> +#include "exec/cpu-defs.h"
> +#include "hw/loader.h"
> +#include "hw/riscv/boot.h"
> +#include "elf.h"
> +
> +target_ulong riscv_load_kernel(const char *kernel_filename)
> +{
> + uint64_t kernel_entry, kernel_high;
> +
> + if (load_elf(kernel_filename, NULL, NULL, NULL,
> + &kernel_entry, NULL, &kernel_high,
> + 0, EM_RISCV, 1, 0) < 0) {
> + error_report("could not load kernel '%s'", kernel_filename);
> + exit(1);
> + }
> +
> + return kernel_entry;
> +}
> +
> +hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
> + uint64_t kernel_entry, hwaddr *start)
> +{
> + int size;
> +
> + /* We want to put the initrd far enough into RAM that when the
nits: /* should be on a separate line
> + * kernel is uncompressed it will not clobber the initrd. However
> + * on boards without much RAM we must ensure that we still leave
> + * enough room for a decent sized initrd, and on boards with large
> + * amounts of RAM we must avoid the initrd being so far up in RAM
> + * that it is outside lowmem and inaccessible to the kernel.
> + * So for boards with less than 256MB of RAM we put the initrd
> + * halfway into RAM, and for boards with 256MB of RAM or more we put
> + * the initrd at 128MB.
> + */
[snip]
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware Alistair Francis
@ 2019-06-19 15:16 ` Bin Meng
2019-06-19 15:25 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
0 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-19 15:16 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 8:53 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Add support for loading a firmware file for the virt machine and the
> SiFive U. This can be run with the following command:
>
> qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/boot.c | 41 +++++++++++++++++++++++++++++++++++++++--
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 6 +++++-
> hw/riscv/spike.c | 6 +++---
> hw/riscv/virt.c | 7 ++++++-
> include/hw/riscv/boot.h | 4 +++-
> 6 files changed, 57 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 62f94aaf8a..392ca0cb2e 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -23,13 +23,50 @@
> #include "exec/cpu-defs.h"
> #include "hw/loader.h"
> #include "hw/riscv/boot.h"
> +#include "hw/boards.h"
> #include "elf.h"
>
> -target_ulong riscv_load_kernel(const char *kernel_filename)
> +#if defined(TARGET_RISCV32)
> +# define KERNEL_BOOT_ADDRESS 0x80400000
> +#else
> +# define KERNEL_BOOT_ADDRESS 0x80200000
> +#endif
> +
> +static uint64_t kernel_translate(void *opaque, uint64_t addr)
> +{
> + MachineState *machine = opaque;
> +
> + /*
> + * If the user specified a firmware move the kernel to the offset
> + * start address.
> + */
Why?
> + if (machine->firmware) {
> + return (addr & 0x7fffffff) + KERNEL_BOOT_ADDRESS;
So with both "-bios" and "-kernel", the kernel address will be moved
to another address other than 0x80200000 (for 64-bit). This does not
look good to me.
> + } else {
> + return addr;
> + }
> +}
> +
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support Alistair Francis
@ 2019-06-19 15:16 ` Bin Meng
2019-06-19 21:01 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-19 15:16 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Extend the RISC-V kernel loader to support uImage and Image files.
> A Linux kernel can now be booted with:
>
> qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel Image
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/boot.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 392ca0cb2e..7f68035a3f 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -67,13 +67,22 @@ target_ulong riscv_load_kernel(MachineState *machine,
> uint64_t kernel_entry, kernel_high;
>
> if (load_elf(kernel_filename, NULL, kernel_translate, machine,
> - &kernel_entry, NULL, &kernel_high,
> - 0, EM_RISCV, 1, 0) < 0) {
> - error_report("could not load kernel '%s'", kernel_filename);
> - exit(1);
> + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) {
> + return kernel_entry;
> + }
> +
> + if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
> + kernel_translate, machine, NULL) > 0) {
We should not set the 'kernel_translate' here for uImage.
In fact, the whole kernel_translate() is not necessary.
> + return kernel_entry;
> + }
> +
Regards,
Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3
2019-06-19 5:14 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
@ 2019-06-19 15:18 ` Bin Meng
2019-06-19 18:27 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-19 15:18 UTC (permalink / raw)
To: Anup Patel
Cc: Alistair Francis, Palmer Dabbelt, Alistair Francis,
open list:RISC-V, QEMU Developers
On Wed, Jun 19, 2019 at 1:14 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > .gitmodules | 3 +++
> > Makefile | 3 ++-
> > configure | 1 +
> > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > roms/Makefile | 17 +++++++++++++++++
> > roms/opensbi | 1 +
> > 7 files changed, 24 insertions(+), 1 deletion(-)
> > create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
> > create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
> > create mode 160000 roms/opensbi
> >
>
> The OpenSBI firmwares are platform specific so we should have
> machine directory under pc-bios/ directory
>
> So for virt machine we will have:
> pc-bios/riscv32/virt/fw_jump.elf
> pc-bios/riscv64/virt/fw_jump.elf
And we should only integrate plain binary image for "bios" images here.
pc-bios/riscv32/virt/fw_jump.bin
pc-bios/riscv64/virt/fw_jump.bin
Regards,
Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
2019-06-19 15:16 ` Bin Meng
@ 2019-06-19 15:25 ` Jonathan Behrens
2019-06-19 15:30 ` Bin Meng
0 siblings, 1 reply; 30+ messages in thread
From: Jonathan Behrens @ 2019-06-19 15:25 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Palmer Dabbelt, Alistair Francis,
open list:RISC-V, qemu-devel@nongnu.org Developers
I was actually just writing up the same thing. Shifting all the addresses
in the ELF file by 2 or 4MB is somewhat surprising behavior, especially
because this will apply to segments that are mapped even at much higher
addresses. If you want a segment aligned to a 1GB superpage boundary you
now need to place it slightly below so that it will be bumped up to the
right place. Further, ANDing all addresses with 0x7fffffff makes it
impossible to map anything beyond the first 2GB of RAM.
Jonathan
On Wed, Jun 19, 2019 at 11:16 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> On Wed, Jun 19, 2019 at 8:53 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Add support for loading a firmware file for the virt machine and the
> > SiFive U. This can be run with the following command:
> >
> > qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/boot.c | 41 +++++++++++++++++++++++++++++++++++++++--
> > hw/riscv/sifive_e.c | 2 +-
> > hw/riscv/sifive_u.c | 6 +++++-
> > hw/riscv/spike.c | 6 +++---
> > hw/riscv/virt.c | 7 ++++++-
> > include/hw/riscv/boot.h | 4 +++-
> > 6 files changed, 57 insertions(+), 9 deletions(-)
> >
> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> > index 62f94aaf8a..392ca0cb2e 100644
> > --- a/hw/riscv/boot.c
> > +++ b/hw/riscv/boot.c
> > @@ -23,13 +23,50 @@
> > #include "exec/cpu-defs.h"
> > #include "hw/loader.h"
> > #include "hw/riscv/boot.h"
> > +#include "hw/boards.h"
> > #include "elf.h"
> >
> > -target_ulong riscv_load_kernel(const char *kernel_filename)
> > +#if defined(TARGET_RISCV32)
> > +# define KERNEL_BOOT_ADDRESS 0x80400000
> > +#else
> > +# define KERNEL_BOOT_ADDRESS 0x80200000
> > +#endif
> > +
> > +static uint64_t kernel_translate(void *opaque, uint64_t addr)
> > +{
> > + MachineState *machine = opaque;
> > +
> > + /*
> > + * If the user specified a firmware move the kernel to the offset
> > + * start address.
> > + */
>
> Why?
>
> > + if (machine->firmware) {
> > + return (addr & 0x7fffffff) + KERNEL_BOOT_ADDRESS;
>
> So with both "-bios" and "-kernel", the kernel address will be moved
> to another address other than 0x80200000 (for 64-bit). This does not
> look good to me.
>
> > + } else {
> > + return addr;
> > + }
> > +}
> > +
>
> [snip]
>
> Regards,
> Bin
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
2019-06-19 15:25 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
@ 2019-06-19 15:30 ` Bin Meng
2019-06-19 21:00 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-19 15:30 UTC (permalink / raw)
To: Jonathan Behrens
Cc: Alistair Francis, Palmer Dabbelt, Alistair Francis,
open list:RISC-V, qemu-devel@nongnu.org Developers
Hi,
On Wed, Jun 19, 2019 at 11:26 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>
> I was actually just writing up the same thing. Shifting all the addresses in the ELF file by 2 or 4MB is somewhat surprising behavior, especially because this will apply to segments that are mapped even at much higher addresses. If you want a segment aligned to a 1GB superpage boundary you now need to place it slightly below so that it will be bumped up to the right place. Further, ANDing all addresses with 0x7fffffff makes it impossible to map anything beyond the first 2GB of RAM.
>
Yes, current kernel_translate() logic is tightly coupled to the kernel
entry VA, and if we link kernel at some other address it will just
fail.
> Jonathan
>
> On Wed, Jun 19, 2019 at 11:16 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> On Wed, Jun 19, 2019 at 8:53 AM Alistair Francis
>> <alistair.francis@wdc.com> wrote:
>> >
>> > Add support for loading a firmware file for the virt machine and the
>> > SiFive U. This can be run with the following command:
>> >
>> > qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux
>> >
>> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > ---
>> > hw/riscv/boot.c | 41 +++++++++++++++++++++++++++++++++++++++--
>> > hw/riscv/sifive_e.c | 2 +-
>> > hw/riscv/sifive_u.c | 6 +++++-
>> > hw/riscv/spike.c | 6 +++---
>> > hw/riscv/virt.c | 7 ++++++-
>> > include/hw/riscv/boot.h | 4 +++-
>> > 6 files changed, 57 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
>> > index 62f94aaf8a..392ca0cb2e 100644
>> > --- a/hw/riscv/boot.c
>> > +++ b/hw/riscv/boot.c
>> > @@ -23,13 +23,50 @@
>> > #include "exec/cpu-defs.h"
>> > #include "hw/loader.h"
>> > #include "hw/riscv/boot.h"
>> > +#include "hw/boards.h"
>> > #include "elf.h"
>> >
>> > -target_ulong riscv_load_kernel(const char *kernel_filename)
>> > +#if defined(TARGET_RISCV32)
>> > +# define KERNEL_BOOT_ADDRESS 0x80400000
>> > +#else
>> > +# define KERNEL_BOOT_ADDRESS 0x80200000
>> > +#endif
>> > +
>> > +static uint64_t kernel_translate(void *opaque, uint64_t addr)
>> > +{
>> > + MachineState *machine = opaque;
>> > +
>> > + /*
>> > + * If the user specified a firmware move the kernel to the offset
>> > + * start address.
>> > + */
>>
>> Why?
>>
>> > + if (machine->firmware) {
>> > + return (addr & 0x7fffffff) + KERNEL_BOOT_ADDRESS;
>>
>> So with both "-bios" and "-kernel", the kernel address will be moved
>> to another address other than 0x80200000 (for 64-bit). This does not
>> look good to me.
>>
So why not simply return KERNEL_BOOT_ADDRESS in kernel_translate()?
Regards,
Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-19 14:42 ` Bin Meng
@ 2019-06-19 18:23 ` Alistair Francis
2019-06-20 8:16 ` [Qemu-devel] [Qemu-riscv] " Andrea Bolognani
0 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 18:23 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 7:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 10:30 PM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, Jun 19, 2019 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis
> > > <alistair.francis@wdc.com> wrote:
> > > >
> > > > This is an RFC as it will break ALL current users! See below for details.
> > > >
> > > > This series consolidates the current RISC-V kernel loading
> > > > impelementation while also adding support for the -bios option and more
> > > > advanced kernel image types.
> > > >
> > > > After consolidating the kernel loading we can extend the boot loader to
> > > > support a -bios option. We can also extend the kernel loading options to
> > > > support not just ELF files but other standard formats.
> > > >
> > > > Finally we can include the OpenSBI firmware by default for QEMU users.
> > > >
> > > > At the end of this series we are in the good place of no longer
> > > > requiring users to build firmware to boot a kernel. Instead users can
> > > > just run QEMu with the -kernel option and everything will work. They can
> > >
> > > This is great. I like booting kernel directly for testing without
> > > bothering the firmware stuff.
> >
> > That's the goal! Now we just need to not break everything.
> >
> > >
> > > > also override the firmware with their own using the -bios option. Using
> > > > "-bios none" will result in no firmware being loaded (as it is today).
> > > >
> > > > !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
> > > >
> > > > Unfortunately this series (patch 5 specifically) results in all current
> > > > Linux boots being broken as users are already loading in their own
> > > > firmware, which overlaps with the now included default. They will
> > > > see this error:
> > > >
> > > > rom: requested regions overlap (rom phdr #0: ./images/qemuriscv64/fw_jump.elf. free=0x0000000080008090, addr=0x0000000080000000)
> > > > qemu-system-riscv64: rom check and register reset failed
> > > >
> > > > If a current user specieifies "-bios none" their flow will continue
> > > > working. A user can instead no longer load their firmware and
> > > > use the default or they can load their firmware with the -bios option.
> > > >
> > > > At the moment the best idea I have to not break all users is to only
> > > > include the default firmware if the user specifies "-bios opensbi".
> > > > That is change the default to not loading the firmware. Then we can work
> > > > on updating documentation and maybe in future change the default to
> > > > include a firmware and anyone who doesn't want a default firmware can
> > > > specify "-bios none".
> > > >
> > > > Any other ideas on how to not break everything?
> > > >
> > > >
> > > >
> > > > Alistair Francis (5):
> > > > hw/riscv: Split out the boot functions
> > > > hw/riscv: Add support for loading a firmware
> > > > hw/riscv: Extend the kernel loading support
> > > > roms: Add OpenSBI version 0.3
> > > > hw/riscv: Load OpenSBI as the default firmware
> > > >
> > > > .gitmodules | 3 +
> > > > Makefile | 3 +-
> > > > configure | 1 +
> > > > hw/riscv/Makefile.objs | 1 +
> > > > hw/riscv/boot.c | 143 ++++++++++++++++++++++++++++
> > > > hw/riscv/sifive_e.c | 17 +---
> > > > hw/riscv/sifive_u.c | 19 +---
> > > > hw/riscv/spike.c | 21 +---
> > > > hw/riscv/virt.c | 54 ++---------
> > > > include/hw/riscv/boot.h | 30 ++++++
> > > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > >
> > > Since we are considering adding "bios" images, I prefer to add the
> > > pure binary images instead of ELF images here.
> >
> > I didn't think about that. Can we just boot them in QEMU like we do
> > with the ELFs?
>
> Yes, use load_image_targphys() instead of load_elf().
Ah, that is obvious. I'll update it to use the bin files then.
Alistair
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions
2019-06-19 15:16 ` Bin Meng
@ 2019-06-19 18:24 ` Alistair Francis
0 siblings, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 18:24 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 8:16 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 8:51 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Split the common RISC-V boot functions into a seperate file. This allows
> > us to share the common code.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/Makefile.objs | 1 +
> > hw/riscv/boot.c | 69 +++++++++++++++++++++++++++++++++++++++++
> > hw/riscv/sifive_e.c | 17 ++--------
> > hw/riscv/sifive_u.c | 17 ++--------
> > hw/riscv/spike.c | 21 +++----------
> > hw/riscv/virt.c | 51 +++---------------------------
> > include/hw/riscv/boot.h | 27 ++++++++++++++++
> > 7 files changed, 110 insertions(+), 93 deletions(-)
> > create mode 100644 hw/riscv/boot.c
> > create mode 100644 include/hw/riscv/boot.h
> >
> > diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> > index a65027304a..eb9d4f9ffc 100644
> > --- a/hw/riscv/Makefile.objs
> > +++ b/hw/riscv/Makefile.objs
> > @@ -1,3 +1,4 @@
> > +obj-y += boot.o
> > obj-$(CONFIG_SPIKE) += riscv_htif.o
> > obj-$(CONFIG_HART) += riscv_hart.o
> > obj-$(CONFIG_SIFIVE_E) += sifive_e.o
> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> > new file mode 100644
> > index 0000000000..62f94aaf8a
> > --- /dev/null
> > +++ b/hw/riscv/boot.c
> > @@ -0,0 +1,69 @@
> > +/*
> > + * QEMU RISC-V Boot Helper
> > + *
> > + * Copyright (c) 2017 SiFive, Inc.
> > + * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2 or later, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along with
> > + * this program. If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/units.h"
> > +#include "qemu/error-report.h"
> > +#include "exec/cpu-defs.h"
> > +#include "hw/loader.h"
> > +#include "hw/riscv/boot.h"
> > +#include "elf.h"
> > +
> > +target_ulong riscv_load_kernel(const char *kernel_filename)
> > +{
> > + uint64_t kernel_entry, kernel_high;
> > +
> > + if (load_elf(kernel_filename, NULL, NULL, NULL,
> > + &kernel_entry, NULL, &kernel_high,
> > + 0, EM_RISCV, 1, 0) < 0) {
> > + error_report("could not load kernel '%s'", kernel_filename);
> > + exit(1);
> > + }
> > +
> > + return kernel_entry;
> > +}
> > +
> > +hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
> > + uint64_t kernel_entry, hwaddr *start)
> > +{
> > + int size;
> > +
> > + /* We want to put the initrd far enough into RAM that when the
>
> nits: /* should be on a separate line
Fixed
>
> > + * kernel is uncompressed it will not clobber the initrd. However
> > + * on boards without much RAM we must ensure that we still leave
> > + * enough room for a decent sized initrd, and on boards with large
> > + * amounts of RAM we must avoid the initrd being so far up in RAM
> > + * that it is outside lowmem and inaccessible to the kernel.
> > + * So for boards with less than 256MB of RAM we put the initrd
> > + * halfway into RAM, and for boards with 256MB of RAM or more we put
> > + * the initrd at 128MB.
> > + */
>
> [snip]
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Alistair
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3
2019-06-19 15:18 ` Bin Meng
@ 2019-06-19 18:27 ` Alistair Francis
2019-06-21 5:41 ` Bin Meng
0 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 18:27 UTC (permalink / raw)
To: Bin Meng
Cc: Anup Patel, Palmer Dabbelt, Alistair Francis, open list:RISC-V,
QEMU Developers
On Wed, Jun 19, 2019 at 8:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 1:14 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis
> > <alistair.francis@wdc.com> wrote:
> > >
> > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
> > >
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > ---
> > > .gitmodules | 3 +++
> > > Makefile | 3 ++-
> > > configure | 1 +
> > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > > roms/Makefile | 17 +++++++++++++++++
> > > roms/opensbi | 1 +
> > > 7 files changed, 24 insertions(+), 1 deletion(-)
> > > create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
> > > create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
> > > create mode 160000 roms/opensbi
> > >
> >
> > The OpenSBI firmwares are platform specific so we should have
> > machine directory under pc-bios/ directory
> >
> > So for virt machine we will have:
> > pc-bios/riscv32/virt/fw_jump.elf
> > pc-bios/riscv64/virt/fw_jump.elf
I have updated the names to indicate the machine. The pc-bios directly
appears to be flat (at least for binaries) so I don't want to add
subdirectories.
>
> And we should only integrate plain binary image for "bios" images here.
>
> pc-bios/riscv32/virt/fw_jump.bin
> pc-bios/riscv64/virt/fw_jump.bin
Yep, fixed.
Alistair
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
2019-06-19 15:30 ` Bin Meng
@ 2019-06-19 21:00 ` Alistair Francis
0 siblings, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 21:00 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
Jonathan Behrens, qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 8:30 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi,
>
> On Wed, Jun 19, 2019 at 11:26 PM Jonathan Behrens <fintelia@gmail.com> wrote:
> >
> > I was actually just writing up the same thing. Shifting all the addresses in the ELF file by 2 or 4MB is somewhat surprising behavior, especially because this will apply to segments that are mapped even at much higher addresses. If you want a segment aligned to a 1GB superpage boundary you now need to place it slightly below so that it will be bumped up to the right place. Further, ANDing all addresses with 0x7fffffff makes it impossible to map anything beyond the first 2GB of RAM.
> >
>
> Yes, current kernel_translate() logic is tightly coupled to the kernel
> entry VA, and if we link kernel at some other address it will just
> fail.
I thought this was required but it looks like it isn't. I have remove
the kernel_translate() function.
>
> > Jonathan
> >
> > On Wed, Jun 19, 2019 at 11:16 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >> On Wed, Jun 19, 2019 at 8:53 AM Alistair Francis
> >> <alistair.francis@wdc.com> wrote:
> >> >
> >> > Add support for loading a firmware file for the virt machine and the
> >> > SiFive U. This can be run with the following command:
> >> >
> >> > qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux
> >> >
> >> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> > ---
> >> > hw/riscv/boot.c | 41 +++++++++++++++++++++++++++++++++++++++--
> >> > hw/riscv/sifive_e.c | 2 +-
> >> > hw/riscv/sifive_u.c | 6 +++++-
> >> > hw/riscv/spike.c | 6 +++---
> >> > hw/riscv/virt.c | 7 ++++++-
> >> > include/hw/riscv/boot.h | 4 +++-
> >> > 6 files changed, 57 insertions(+), 9 deletions(-)
> >> >
> >> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> >> > index 62f94aaf8a..392ca0cb2e 100644
> >> > --- a/hw/riscv/boot.c
> >> > +++ b/hw/riscv/boot.c
> >> > @@ -23,13 +23,50 @@
> >> > #include "exec/cpu-defs.h"
> >> > #include "hw/loader.h"
> >> > #include "hw/riscv/boot.h"
> >> > +#include "hw/boards.h"
> >> > #include "elf.h"
> >> >
> >> > -target_ulong riscv_load_kernel(const char *kernel_filename)
> >> > +#if defined(TARGET_RISCV32)
> >> > +# define KERNEL_BOOT_ADDRESS 0x80400000
> >> > +#else
> >> > +# define KERNEL_BOOT_ADDRESS 0x80200000
> >> > +#endif
> >> > +
> >> > +static uint64_t kernel_translate(void *opaque, uint64_t addr)
> >> > +{
> >> > + MachineState *machine = opaque;
> >> > +
> >> > + /*
> >> > + * If the user specified a firmware move the kernel to the offset
> >> > + * start address.
> >> > + */
> >>
> >> Why?
Removed.
> >>
> >> > + if (machine->firmware) {
> >> > + return (addr & 0x7fffffff) + KERNEL_BOOT_ADDRESS;
> >>
> >> So with both "-bios" and "-kernel", the kernel address will be moved
> >> to another address other than 0x80200000 (for 64-bit). This does not
> >> look good to me.
> >>
>
> So why not simply return KERNEL_BOOT_ADDRESS in kernel_translate()?
That's what I am doing now.
Alistair
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
2019-06-19 15:16 ` Bin Meng
@ 2019-06-19 21:01 ` Alistair Francis
2019-06-19 22:06 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 21:01 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 8:16 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Extend the RISC-V kernel loader to support uImage and Image files.
> > A Linux kernel can now be booted with:
> >
> > qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel Image
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/boot.c | 19 ++++++++++++++-----
> > 1 file changed, 14 insertions(+), 5 deletions(-)
> >
> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> > index 392ca0cb2e..7f68035a3f 100644
> > --- a/hw/riscv/boot.c
> > +++ b/hw/riscv/boot.c
> > @@ -67,13 +67,22 @@ target_ulong riscv_load_kernel(MachineState *machine,
> > uint64_t kernel_entry, kernel_high;
> >
> > if (load_elf(kernel_filename, NULL, kernel_translate, machine,
> > - &kernel_entry, NULL, &kernel_high,
> > - 0, EM_RISCV, 1, 0) < 0) {
> > - error_report("could not load kernel '%s'", kernel_filename);
> > - exit(1);
> > + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) {
> > + return kernel_entry;
> > + }
> > +
> > + if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
> > + kernel_translate, machine, NULL) > 0) {
>
> We should not set the 'kernel_translate' here for uImage.
>
> In fact, the whole kernel_translate() is not necessary.
I have removed the kernel_translate() function. I tested loading
uImage files though and they don't seem to work as the image is loaded
at the wrong address.
I have removed uImage loading support from this series. We can look at
it in the future if we decide we want it.
Alistair
>
> > + return kernel_entry;
> > + }
> > +
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
2019-06-19 21:01 ` Alistair Francis
@ 2019-06-19 22:06 ` Alistair Francis
0 siblings, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2019-06-19 22:06 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Jun 19, 2019 at 2:01 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 8:16 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis
> > <alistair.francis@wdc.com> wrote:
> > >
> > > Extend the RISC-V kernel loader to support uImage and Image files.
> > > A Linux kernel can now be booted with:
> > >
> > > qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel Image
> > >
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > ---
> > > hw/riscv/boot.c | 19 ++++++++++++++-----
> > > 1 file changed, 14 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> > > index 392ca0cb2e..7f68035a3f 100644
> > > --- a/hw/riscv/boot.c
> > > +++ b/hw/riscv/boot.c
> > > @@ -67,13 +67,22 @@ target_ulong riscv_load_kernel(MachineState *machine,
> > > uint64_t kernel_entry, kernel_high;
> > >
> > > if (load_elf(kernel_filename, NULL, kernel_translate, machine,
> > > - &kernel_entry, NULL, &kernel_high,
> > > - 0, EM_RISCV, 1, 0) < 0) {
> > > - error_report("could not load kernel '%s'", kernel_filename);
> > > - exit(1);
> > > + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) {
> > > + return kernel_entry;
> > > + }
> > > +
> > > + if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
> > > + kernel_translate, machine, NULL) > 0) {
> >
> > We should not set the 'kernel_translate' here for uImage.
> >
> > In fact, the whole kernel_translate() is not necessary.
>
> I have removed the kernel_translate() function. I tested loading
> uImage files though and they don't seem to work as the image is loaded
> at the wrong address.
>
> I have removed uImage loading support from this series. We can look at
> it in the future if we decide we want it.
Ah, my mistake, it looks like my uImage wasn't built correctly. I'll
keep this in.
Alistair
>
> Alistair
>
> >
> > > + return kernel_entry;
> > > + }
> > > +
> >
> > Regards,
> > Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-19 18:23 ` Alistair Francis
@ 2019-06-20 8:16 ` Andrea Bolognani
2019-06-20 17:59 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Andrea Bolognani @ 2019-06-20 8:16 UTC (permalink / raw)
To: Alistair Francis, Bin Meng
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, 2019-06-19 at 11:23 -0700, Alistair Francis wrote:
> On Wed, Jun 19, 2019 at 7:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > On Wed, Jun 19, 2019 at 10:30 PM Alistair Francis <alistair23@gmail.com> wrote:
> > > On Wed, Jun 19, 2019 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > > >
> > > > Since we are considering adding "bios" images, I prefer to add the
> > > > pure binary images instead of ELF images here.
> > >
> > > I didn't think about that. Can we just boot them in QEMU like we do
> > > with the ELFs?
> >
> > Yes, use load_image_targphys() instead of load_elf().
>
> Ah, that is obvious. I'll update it to use the bin files then.
I'm unclear on the advantages of using one format over the other,
but one question comes to mind: once this is in, we will probably
want to have OpenSBI packaged separately in distributions, the same
way it already happens for SeaBIOS, SLOF and edk2-based firmwares.
Will using either of the formats prevent that from happening?
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-20 8:16 ` [Qemu-devel] [Qemu-riscv] " Andrea Bolognani
@ 2019-06-20 17:59 ` Alistair Francis
2019-06-20 18:43 ` David Abdurachmanov
0 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2019-06-20 17:59 UTC (permalink / raw)
To: Andrea Bolognani
Cc: Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, Palmer Dabbelt
On Thu, Jun 20, 2019 at 1:16 AM Andrea Bolognani <abologna@redhat.com> wrote:
>
> On Wed, 2019-06-19 at 11:23 -0700, Alistair Francis wrote:
> > On Wed, Jun 19, 2019 at 7:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > On Wed, Jun 19, 2019 at 10:30 PM Alistair Francis <alistair23@gmail.com> wrote:
> > > > On Wed, Jun 19, 2019 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > > > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > > > >
> > > > > Since we are considering adding "bios" images, I prefer to add the
> > > > > pure binary images instead of ELF images here.
> > > >
> > > > I didn't think about that. Can we just boot them in QEMU like we do
> > > > with the ELFs?
> > >
> > > Yes, use load_image_targphys() instead of load_elf().
> >
> > Ah, that is obvious. I'll update it to use the bin files then.
>
> I'm unclear on the advantages of using one format over the other,
The main one that I see is that everyone else is already using .bin
and no one else is using .elf.
> but one question comes to mind: once this is in, we will probably
> want to have OpenSBI packaged separately in distributions, the same
> way it already happens for SeaBIOS, SLOF and edk2-based firmwares.
>
> Will using either of the formats prevent that from happening?
Both options allow this.
OE-Core already packages OpenSBI by default, Fedora and Debian are
moving to OpenSBI for RISC-V targets as well.
Any distro that supports the RISC-V toolchain (which is all
upstreamed) can build OpenSBI.
Alistair
>
> --
> Andrea Bolognani / Red Hat / Virtualization
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-20 17:59 ` Alistair Francis
@ 2019-06-20 18:43 ` David Abdurachmanov
2019-06-21 12:35 ` Andrea Bolognani
0 siblings, 1 reply; 30+ messages in thread
From: David Abdurachmanov @ 2019-06-20 18:43 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Palmer Dabbelt, Andrea Bolognani,
qemu-devel@nongnu.org Developers, Alistair Francis, Bin Meng
On Thu, Jun 20, 2019 at 9:18 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Thu, Jun 20, 2019 at 1:16 AM Andrea Bolognani <abologna@redhat.com> wrote:
> >
> > On Wed, 2019-06-19 at 11:23 -0700, Alistair Francis wrote:
> > > On Wed, Jun 19, 2019 at 7:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > On Wed, Jun 19, 2019 at 10:30 PM Alistair Francis <alistair23@gmail.com> wrote:
> > > > > On Wed, Jun 19, 2019 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > > > > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > > > > >
> > > > > > Since we are considering adding "bios" images, I prefer to add the
> > > > > > pure binary images instead of ELF images here.
> > > > >
> > > > > I didn't think about that. Can we just boot them in QEMU like we do
> > > > > with the ELFs?
> > > >
> > > > Yes, use load_image_targphys() instead of load_elf().
> > >
> > > Ah, that is obvious. I'll update it to use the bin files then.
> >
> > I'm unclear on the advantages of using one format over the other,
>
> The main one that I see is that everyone else is already using .bin
> and no one else is using .elf.
>
> > but one question comes to mind: once this is in, we will probably
> > want to have OpenSBI packaged separately in distributions, the same
> > way it already happens for SeaBIOS, SLOF and edk2-based firmwares.
> >
> > Will using either of the formats prevent that from happening?
>
> Both options allow this.
>
> OE-Core already packages OpenSBI by default, Fedora and Debian are
> moving to OpenSBI for RISC-V targets as well.
Fedora uses OpenSBI for the last 2 or 3 months now. I don't plan to update
BBL builds. OpenSBI packages in Fedora/RISCV isn't finalized, but it does
ship *.elf and *.bin files.
>
> Any distro that supports the RISC-V toolchain (which is all
> upstreamed) can build OpenSBI.
>
> Alistair
>
> >
> > --
> > Andrea Bolognani / Red Hat / Virtualization
> >
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3
2019-06-19 18:27 ` Alistair Francis
@ 2019-06-21 5:41 ` Bin Meng
2019-06-21 22:41 ` Alistair Francis
0 siblings, 1 reply; 30+ messages in thread
From: Bin Meng @ 2019-06-21 5:41 UTC (permalink / raw)
To: Alistair Francis
Cc: Anup Patel, Palmer Dabbelt, Alistair Francis, open list:RISC-V,
QEMU Developers
On Thu, Jun 20, 2019 at 2:30 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Jun 19, 2019 at 8:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Wed, Jun 19, 2019 at 1:14 PM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis
> > > <alistair.francis@wdc.com> wrote:
> > > >
> > > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
> > > >
> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > > ---
> > > > .gitmodules | 3 +++
> > > > Makefile | 3 ++-
> > > > configure | 1 +
> > > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > > > roms/Makefile | 17 +++++++++++++++++
> > > > roms/opensbi | 1 +
> > > > 7 files changed, 24 insertions(+), 1 deletion(-)
> > > > create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
> > > > create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
> > > > create mode 160000 roms/opensbi
> > > >
> > >
> > > The OpenSBI firmwares are platform specific so we should have
> > > machine directory under pc-bios/ directory
> > >
> > > So for virt machine we will have:
> > > pc-bios/riscv32/virt/fw_jump.elf
> > > pc-bios/riscv64/virt/fw_jump.elf
>
> I have updated the names to indicate the machine. The pc-bios directly
> appears to be flat (at least for binaries) so I don't want to add
> subdirectories.
>
Should we include pre-built OpenSBI "bios" for "sifive_u" machine too?
> >
> > And we should only integrate plain binary image for "bios" images here.
> >
> > pc-bios/riscv32/virt/fw_jump.bin
> > pc-bios/riscv64/virt/fw_jump.bin
>
> Yep, fixed.
>
Regards,
Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-20 18:43 ` David Abdurachmanov
@ 2019-06-21 12:35 ` Andrea Bolognani
2019-06-27 13:49 ` Andrea Bolognani
0 siblings, 1 reply; 30+ messages in thread
From: Andrea Bolognani @ 2019-06-21 12:35 UTC (permalink / raw)
To: David Abdurachmanov, Alistair Francis
Cc: open list:RISC-V, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers, Palmer Dabbelt
On Thu, 2019-06-20 at 21:43 +0300, David Abdurachmanov wrote:
> On Thu, Jun 20, 2019 at 9:18 PM Alistair Francis <alistair23@gmail.com> wrote:
> > On Thu, Jun 20, 2019 at 1:16 AM Andrea Bolognani <abologna@redhat.com> wrote:
> > > but one question comes to mind: once this is in, we will probably
> > > want to have OpenSBI packaged separately in distributions, the same
> > > way it already happens for SeaBIOS, SLOF and edk2-based firmwares.
> > >
> > > Will using either of the formats prevent that from happening?
> >
> > Both options allow this.
> >
> > OE-Core already packages OpenSBI by default, Fedora and Debian are
> > moving to OpenSBI for RISC-V targets as well.
> >
> > Any distro that supports the RISC-V toolchain (which is all
> > upstreamed) can build OpenSBI.
>
> Fedora uses OpenSBI for the last 2 or 3 months now. I don't plan to update
> BBL builds. OpenSBI packages in Fedora/RISCV isn't finalized, but it does
> ship *.elf and *.bin files.
Sounds good to me, thanks for confirming!
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3
2019-06-21 5:41 ` Bin Meng
@ 2019-06-21 22:41 ` Alistair Francis
0 siblings, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2019-06-21 22:41 UTC (permalink / raw)
To: Bin Meng
Cc: Anup Patel, Palmer Dabbelt, Alistair Francis, open list:RISC-V,
QEMU Developers
On Thu, Jun 20, 2019 at 10:42 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Thu, Jun 20, 2019 at 2:30 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, Jun 19, 2019 at 8:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Wed, Jun 19, 2019 at 1:14 PM Anup Patel <anup@brainfault.org> wrote:
> > > >
> > > > On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis
> > > > <alistair.francis@wdc.com> wrote:
> > > > >
> > > > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
> > > > >
> > > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > > > ---
> > > > > .gitmodules | 3 +++
> > > > > Makefile | 3 ++-
> > > > > configure | 1 +
> > > > > pc-bios/opensbi-riscv32-fw_jump.elf | Bin 0 -> 197988 bytes
> > > > > pc-bios/opensbi-riscv64-fw_jump.elf | Bin 0 -> 200192 bytes
> > > > > roms/Makefile | 17 +++++++++++++++++
> > > > > roms/opensbi | 1 +
> > > > > 7 files changed, 24 insertions(+), 1 deletion(-)
> > > > > create mode 100644 pc-bios/opensbi-riscv32-fw_jump.elf
> > > > > create mode 100644 pc-bios/opensbi-riscv64-fw_jump.elf
> > > > > create mode 160000 roms/opensbi
> > > > >
> > > >
> > > > The OpenSBI firmwares are platform specific so we should have
> > > > machine directory under pc-bios/ directory
> > > >
> > > > So for virt machine we will have:
> > > > pc-bios/riscv32/virt/fw_jump.elf
> > > > pc-bios/riscv64/virt/fw_jump.elf
> >
> > I have updated the names to indicate the machine. The pc-bios directly
> > appears to be flat (at least for binaries) so I don't want to add
> > subdirectories.
> >
>
> Should we include pre-built OpenSBI "bios" for "sifive_u" machine too?
Yep, I am doing that now.
Alistair
>
> > >
> > > And we should only integrate plain binary image for "bios" images here.
> > >
> > > pc-bios/riscv32/virt/fw_jump.bin
> > > pc-bios/riscv64/virt/fw_jump.bin
> >
> > Yep, fixed.
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-riscv] [RFC v1 0/5] RISC-V: Add firmware loading support and default
2019-06-21 12:35 ` Andrea Bolognani
@ 2019-06-27 13:49 ` Andrea Bolognani
0 siblings, 0 replies; 30+ messages in thread
From: Andrea Bolognani @ 2019-06-27 13:49 UTC (permalink / raw)
To: David Abdurachmanov, Alistair Francis
Cc: Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, Palmer Dabbelt
On Fri, 2019-06-21 at 14:35 +0200, Andrea Bolognani wrote:
> On Thu, 2019-06-20 at 21:43 +0300, David Abdurachmanov wrote:
> > On Thu, Jun 20, 2019 at 9:18 PM Alistair Francis <alistair23@gmail.com> wrote:
> > > OE-Core already packages OpenSBI by default, Fedora and Debian are
> > > moving to OpenSBI for RISC-V targets as well.
> > >
> > > Any distro that supports the RISC-V toolchain (which is all
> > > upstreamed) can build OpenSBI.
> >
> > Fedora uses OpenSBI for the last 2 or 3 months now. I don't plan to update
> > BBL builds. OpenSBI packages in Fedora/RISCV isn't finalized, but it does
> > ship *.elf and *.bin files.
>
> Sounds good to me, thanks for confirming!
From further off-list discussion with David, I have learned that
recent Fedora images include an OpenSBI build with embedded U-Boot
payload, such that you only need to have that single file on the host
and pass it to QEMU via -kernel[1] for RISC-V guest boot to work. I
played with it over the past few days, and it works very nicely.
I think this is the result that we want to ultimately reach: a single
RISC-V "firmware" binary installed on the host through an appropriate
distro package, shared among guests, with everything else that is
guest-specific being contained in the corresponding disk image.
This is what other architectures are already doing, with SeaBIOS and
OVMF on x86_64, AAVMF on aarch64 and SLOF on ppc64 all being handled
this way: RISC-V should, where it makes sense, follow suit.
QEMU also recently introduced a JSON-based specification that can be
used to advertise guest firmwares and libvirt already supports it,
which makes firmware configuration either extremely convenient or
entirely automatic for the user: the OpenSBI support should also be
advertised this way.
[1] I guess that'd be -bios after these patches?
--
Andrea Bolognani / Red Hat / Virtualization
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2019-06-27 13:50 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 18:24 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 15:25 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-06-19 15:30 ` Bin Meng
2019-06-19 21:00 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 21:01 ` Alistair Francis
2019-06-19 22:06 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3 Alistair Francis
2019-06-19 5:14 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-06-19 15:18 ` Bin Meng
2019-06-19 18:27 ` Alistair Francis
2019-06-21 5:41 ` Bin Meng
2019-06-21 22:41 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware Alistair Francis
2019-06-19 5:16 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-06-19 14:26 ` [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Bin Meng
2019-06-19 14:29 ` Alistair Francis
2019-06-19 14:42 ` Bin Meng
2019-06-19 18:23 ` Alistair Francis
2019-06-20 8:16 ` [Qemu-devel] [Qemu-riscv] " Andrea Bolognani
2019-06-20 17:59 ` Alistair Francis
2019-06-20 18:43 ` David Abdurachmanov
2019-06-21 12:35 ` Andrea Bolognani
2019-06-27 13:49 ` Andrea Bolognani
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