Re: [PATCH v3 14/16] hw/ppc: Use hreg_store_msr for msr updates

From: "Cédric Le Goater" <clg@kaod.org>
To: Richard Henderson <richard.henderson@linaro.org>,
	<qemu-devel@nongnu.org>
Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org,
	Greg Kurz <groug@kaod.org>,
	david@gibson.dropbear.id.au
Subject: Re: [PATCH v3 14/16] hw/ppc: Use hreg_store_msr for msr updates
Date: Mon, 15 Mar 2021 11:23:06 +0100	[thread overview]
Message-ID: <ea6b23c2-21db-a512-87b5-be5351ff0a74@kaod.org> (raw)
In-Reply-To: <20210314175906.1733746-15-richard.henderson@linaro.org>

On 3/14/21 6:59 PM, Richard Henderson wrote:
> Only one of the three places in hw/ppc that modify msr updated
> hflags.  Even in that case, use the official interface instead
> of a direct call to hreg_compute_hflags.

ppc_store_msr() is the interface to use.

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Greg Kurz <groug@kaod.org>
> ---
>  hw/ppc/pnv_core.c    | 3 ++-
>  hw/ppc/spapr_hcall.c | 3 +--
>  hw/ppc/spapr_rtas.c  | 3 ++-
>  3 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index bd2bf2e044..31f041b9c7 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -29,6 +29,7 @@
>  #include "hw/ppc/pnv_xscom.h"
>  #include "hw/ppc/xics.h"
>  #include "hw/qdev-properties.h"
> +#include "helper_regs.h"
>  
>  static const char *pnv_core_cpu_typename(PnvCore *pc)
>  {
> @@ -54,7 +55,7 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu)
>       */
>      env->gpr[3] = PNV_FDT_ADDR;
>      env->nip = 0x10;
> -    env->msr |= MSR_HVB; /* Hypervisor mode */
> +    hreg_store_msr(env, env->msr | MSR_HVB, true); /* Hypervisor mode */

This is going to have the opposite effect of not setting the HV bit in the 
PowerNV machine. See the comment in powerpc_set_excp_state().

May be commit 1c953ba57ada ("ppc: Fix hreg_store_msr() so that non-HV 
mode cannot alter MSR:HV") needs a fix first.

C.

>  
>      env->spr[SPR_HRMOR] = pc->hrmor;
>  
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 7b5cd3553c..a4f7a09ba8 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -1055,8 +1055,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr,
>      CPUState *cs = CPU(cpu);
>      SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
>  
> -    env->msr |= (1ULL << MSR_EE);
> -    hreg_compute_hflags(env);
> +    hreg_store_msr(env, env->msr | (1ULL << MSR_EE), false);
>  
>      if (spapr_cpu->prod) {
>          spapr_cpu->prod = false;
> diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
> index 8a79f9c628..b9a6b7ef30 100644
> --- a/hw/ppc/spapr_rtas.c
> +++ b/hw/ppc/spapr_rtas.c
> @@ -51,6 +51,7 @@
>  #include "target/ppc/mmu-hash64.h"
>  #include "target/ppc/mmu-book3s-v3.h"
>  #include "migration/blocker.h"
> +#include "helper_regs.h"
>  
>  static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr,
>                                     uint32_t token, uint32_t nargs,
> @@ -162,7 +163,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
>  
>      cpu_synchronize_state(CPU(newcpu));
>  
> -    env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
> +    hreg_store_msr(env, (1ULL << MSR_SF) | (1ULL << MSR_ME), true);
>  
>      /* Enable Power-saving mode Exit Cause exceptions for the new CPU */
>      lpcr = env->spr[SPR_LPCR];
> 