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([2001:8003:e5b0:9f00:dbbc:1945:6e65:ec5]) by smtp.gmail.com with ESMTPSA id d12-20020a17090a498c00b0026b3ed37ddcsm102607pjh.32.2023.09.28.16.43.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Sep 2023 16:43:55 -0700 (PDT) Message-ID: Date: Fri, 29 Sep 2023 09:43:42 +1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH RFC V2 21/37] hw/arm: MADT Tbl change to size the guest with possible vCPUs Content-Language: en-US To: Salil Mehta , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, mst@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, salil.mehta@opnsrc.net, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn References: <20230926100436.28284-1-salil.mehta@huawei.com> <20230926100436.28284-22-salil.mehta@huawei.com> From: Gavin Shan In-Reply-To: <20230926100436.28284-22-salil.mehta@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Salil, On 9/26/23 20:04, Salil Mehta wrote: > Changes required during building of MADT Table by QEMU to accomodate disabled > possible vCPUs. This info shall be used by the guest kernel to size up its > resources during boot time. This pre-sizing of the guest kernel done on > possible vCPUs will facilitate hotplug of the disabled vCPUs. > > This change also caters ACPI MADT GIC CPU Interface flag related changes > recently introduced in the UEFI ACPI 6.5 Specification which allows deferred > virtual CPU online'ing in the Guest Kernel. > > Link: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#gic-cpu-interface-gicc-structure > > Co-developed-by: Salil Mehta > Signed-off-by: Salil Mehta > Co-developed-by: Keqian Zhu > Signed-off-by: Keqian Zhu > Signed-off-by: Salil Mehta > --- > hw/arm/virt-acpi-build.c | 36 ++++++++++++++++++++++++++++++------ > 1 file changed, 30 insertions(+), 6 deletions(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index d27df5030e..cbccd2ca2d 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -700,6 +700,29 @@ static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) > build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ > } > > +static uint32_t virt_acpi_get_gicc_flags(CPUState *cpu) > +{ > + MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); > + > + /* can only exist in 'enabled' state */ > + if (!mc->has_hotpluggable_cpus) { > + return 1; > + } > + > + /* > + * ARM GIC CPU Interface can be 'online-capable' or 'enabled' at boot > + * We MUST set 'online-capable' Bit for all hotpluggable CPUs except the ^^^ bit > + * first/boot CPU. Cold-booted CPUs without 'Id' can also be unplugged. > + * Though as-of-now this is only used as a debugging feature. > + * > + * UEFI ACPI Specification 6.5 > + * Section: 5.2.12.14. GIC CPU Interface (GICC) Structure > + * Table: 5.37 GICC CPU Interface Flags > + * Link: https://uefi.org/specs/ACPI/6.5 > + */ > + return cpu && !cpu->cpu_index ? 1 : (1 << 3); > +} > + I don't understand how a cold-booted CPU can be hot removed if it doesn't have a ID? Besides, how cpu->cpu_index is zero for the first cold-booted CPU? > static void > build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > { > @@ -726,12 +749,13 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > build_append_int_noprefix(table_data, vms->gic_version, 1); > build_append_int_noprefix(table_data, 0, 3); /* Reserved */ > > - for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { > - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); > + for (i = 0; i < MACHINE(vms)->smp.max_cpus; i++) { > + CPUState *cpu = qemu_get_possible_cpu(i); > uint64_t physical_base_address = 0, gich = 0, gicv = 0; > uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0; > - uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? > - PPI(VIRTUAL_PMU_IRQ) : 0; > + uint32_t pmu_interrupt = vms->pmu ? PPI(VIRTUAL_PMU_IRQ) : 0; > + uint32_t flags = virt_acpi_get_gicc_flags(cpu); > + uint64_t mpidr = qemu_get_cpu_archid(i); > qemu_get_cpu_archid() can be dropped since it's called for once. MPIDR can be fetched from ms->possible_cpus->cpus[i].arch_id, which has been initialized pre-hand. > if (vms->gic_version == VIRT_GIC_VERSION_2) { > physical_base_address = memmap[VIRT_GIC_CPU].base; > @@ -746,7 +770,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > build_append_int_noprefix(table_data, i, 4); /* GIC ID */ > build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ > /* Flags */ > - build_append_int_noprefix(table_data, 1, 4); /* Enabled */ > + build_append_int_noprefix(table_data, flags, 4); > /* Parking Protocol Version */ > build_append_int_noprefix(table_data, 0, 4); > /* Performance Interrupt GSIV */ > @@ -760,7 +784,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) > build_append_int_noprefix(table_data, vgic_interrupt, 4); > build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ > /* MPIDR */ > - build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); > + build_append_int_noprefix(table_data, mpidr, 8); > /* Processor Power Efficiency Class */ > build_append_int_noprefix(table_data, 0, 1); > /* Reserved */ Thanks, Gavin