From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz.
Date: Mon, 24 May 2021 11:04:13 -0700 [thread overview]
Message-ID: <ec4abbfd-fccb-a9cd-9dd8-a99bef328d56@linaro.org> (raw)
In-Reply-To: <20210521054816.1784297-1-zhiwei_liu@c-sky.com>
On 5/20/21 10:48 PM, LIU Zhiwei wrote:
> Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz
> is still zero(as we don't use this field), simd_desc will trigger an
> assert.
>
> Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
> Here we pass the value to maxsz and oprsz to bypass the assert.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 89 ++++++++++++++-----------
> 1 file changed, 50 insertions(+), 39 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-05-24 18:08 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-21 5:48 [PATCH] target/riscv: Pass the same value to oprsz and maxsz LIU Zhiwei
2021-05-24 18:04 ` Richard Henderson [this message]
2021-05-25 22:01 ` Alistair Francis
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