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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id a16sm2286767wrt.37.2019.12.09.23.46.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Dec 2019 23:46:23 -0800 (PST) Subject: Re: [PATCH] riscv/sifive_u: fix a memory leak in soc_realize() To: pannengyuan@huawei.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de References: <1575962077-28800-1-git-send-email-pannengyuan@huawei.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 10 Dec 2019 08:46:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <1575962077-28800-1-git-send-email-pannengyuan@huawei.com> Content-Language: en-US X-MC-Unique: ithDc0n9MNCoT2odDZWUFg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/10/19 8:14 AM, pannengyuan@huawei.com wrote: > From: Pan Nengyuan >=20 > Fix a minor memory leak in riscv_sifive_u_soc_realize() >=20 > Reported-by: Euler Robot > Signed-off-by: Pan Nengyuan > --- > hw/riscv/sifive_u.c | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 0140e95..0e12b3c 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *d= ev, Error **errp) > SIFIVE_U_PLIC_CONTEXT_BASE, > SIFIVE_U_PLIC_CONTEXT_STRIDE, > memmap[SIFIVE_U_PLIC].size); > + g_free(plic_hart_config); > sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, > serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_= IRQ)); > sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9