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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id h5sm4030412pjc.9.2019.12.06.10.36.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 10:36:03 -0800 (PST) Subject: Re: [PATCH v4 27/40] target/arm: Add VHE system register redirection and aliasing To: Peter Maydell References: <20191203022937.1474-1-richard.henderson@linaro.org> <20191203022937.1474-28-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 6 Dec 2019 10:36:01 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/6/19 9:24 AM, Peter Maydell wrote: >> + union { >> + /* >> + * Offsets of the secure and non-secure fields in CPUARMState for >> + * the register if it is banked. These fields are only used during >> + * the static registration of a register. During hashing the bank >> + * associated with a given security state is copied to fieldoffset >> + * which is used from there on out. >> + * >> + * It is expected that register definitions use either fieldoffset >> + * or bank_fieldoffsets in the definition but not both. It is also >> + * expected that both bank offsets are set when defining a banked >> + * register. This use indicates that a register is banked. >> + */ >> + ptrdiff_t bank_fieldoffsets[2]; >> + >> + /* >> + * "Original" writefn and readfn. >> + * For ARMv8.1-VHE register aliases, we overwrite the read/write >> + * accessor functions of various EL1/EL0 to perform the runtime >> + * check for which sysreg should actually be modified, and then >> + * forwards the operation. Before overwriting the accessors, >> + * the original function is copied here, so that accesses that >> + * really do go to the EL1/EL0 version proceed normally. >> + * (The corresponding EL2 register is linked via opaque.) >> + */ >> + struct { >> + CPReadFn *orig_readfn; >> + CPWriteFn *orig_writefn; >> + }; > > Does this really need to be a union ? It's not clear to me > why we know the two halves of it are never used at the same time. We don't really need to use a union. I should probably change that. I think AJB had the same question vs one of the previous revisions. We know they're not used at the same time because bank_fieldoffsets is only used *before* the structure is duplicated and added into the hash table (overwriting .fieldoffset depending on the bank as they are duplicated), and orig_{read,write}fn are only used *after* the structure has been added to the hash table. >> +static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, >> + uint64_t value) >> +{ >> + CPWriteFn *writefn; >> + >> + if (redirect_for_e2h(env)) { >> + /* Switch to the saved EL2 version of the register. */ >> + ri = ri->opaque; >> + writefn = ri->writefn; >> + } else { >> + writefn = ri->orig_writefn; >> + } >> + if (writefn == NULL) { >> + writefn = raw_write; >> + } >> + writefn(env, ri, value); >> +} > > I see how this works when we have a readfn or writefn, > but how does the redirection work where the access > goes directly via .fieldoffset ? When there is no .writefn, we use raw_write, which uses fieldoffset. r~