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([2602:ae:1544:6601:8931:d1e4:9c7f:b1c5]) by smtp.gmail.com with ESMTPSA id f11-20020a63510b000000b0050be183459bsm15640833pgb.34.2023.03.25.22.17.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Mar 2023 22:17:05 -0700 (PDT) Message-ID: Date: Sat, 25 Mar 2023 22:17:03 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups Content-Language: en-US From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, palmer@dabbelt.com, zhiwei_liu@linux.alibaba.com, fei2.wu@intel.com References: <20230325105429.1142530-1-richard.henderson@linaro.org> In-Reply-To: <20230325105429.1142530-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/25/23 03:54, Richard Henderson wrote: > This builds on Fei and Zhiwei's SUM and TB_FLAGS changes. > > * Reclaim 5 TB_FLAGS bits, since we nearly ran out. > > * Using cpu_mmu_index(env, true) is insufficient to implement > HLVX properly. While that chooses the correct mmu_idx, it > does not perform the read with execute permission. > I add a new tcg interface to perform a read-for-execute with > an arbitrary mmu_idx. This is still not 100% compliant, but > it's closer. > > * Handle mstatus.MPV in cpu_mmu_index. > * Use vsstatus.SUM when required for MMUIdx_S_SUM. > * Cleanups for get_physical_address. > > While this passes check-avocado, I'm sure that's insufficient. > Please have a close look. Somewhere after either patch 16 or 17, when env->virt is considered in riscv_cpu_mmu_index and a few other bugs are fixed, we can do --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -591,11 +591,6 @@ void riscv_cpu_set_virt_enabled return; } - /* Flush the TLB on all virt mode changes. */ - if (get_field(env->virt, VIRT_ONOFF) != enable) { - tlb_flush(env_cpu(env)); - } - env->virt = set_field(env->virt, VIRT_ONOFF, enable); if (enable) { -- %< -- Because we're no longer trying to overlap the VS and HS tlbs on the same mmuidx. I have been pondering additional changes that would avoid flushing for MXR changes, so that user-lookups from M-mode firmware gets the same advantage as has just been done for SUM. But this is complicated by needing 12 (!) more mmuidx, which cannot currently be represented, nor does it even seem like the best idea. r~