From: Richard Henderson <richard.henderson@linaro.org>
To: Xiaojuan Yang <yangxiaojuan@loongson.cn>, qemu-devel@nongnu.org
Cc: Song Gao <gaosong@loongson.cn>
Subject: Re: [RFC PATCH v2 08/30] target/loongarch: Add LoongArch CSR/IOCSR instruction
Date: Thu, 11 Nov 2021 18:43:40 +0100 [thread overview]
Message-ID: <f8e9fc82-ee40-fd40-3a8c-733c315b726e@linaro.org> (raw)
In-Reply-To: <1636594528-8175-9-git-send-email-yangxiaojuan@loongson.cn>
On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
> This includes:
> - CSRRD
> - CSRWR
> - CSRXCHG
> - IOCSR{RD/WR}.{B/H/W/D}
I think IOCSR should be in a separate patch.
It's completely unrelated to the other CSRs.
> +target_ulong helper_csr_rdq(CPULoongArchState *env, uint64_t csr)
> +{
> + int64_t v;
> +
> + switch (csr) {
> + case LOONGARCH_CSR_PGD:
> + if (env->CSR_TLBRERA & 0x1) {
> + v = env->CSR_TLBRBADV;
> + } else {
> + v = env->CSR_BADV;
> + }
> +
> + if ((v >> 63) & 0x1) {
> + v = env->CSR_PGDH;
> + } else {
> + v = env->CSR_PGDL;
> + }
> + v = v & TARGET_PHYS_MASK;
This csr is defined to be GRLEN bits; I this mask looks wrong.
> + default:
> + assert(0);
g_assert_not_reached.
> + switch (csr) {
> + case LOONGARCH_CSR_ASID:
> + old_v = env->CSR_ASID;
> + env->CSR_ASID = val;
Mask the write to the field; you don't want to corrupt ASIDBITS, or the other read-only bits.
> + case LOONGARCH_CSR_TCFG:
> + old_v = env->CSR_TCFG;
> + cpu_loongarch_store_stable_timer_config(env, val);
> + break;
> + case LOONGARCH_CSR_TINTCLR:
> + old_v = 0;
> + qemu_irq_lower(env->irq[IRQ_TIMER]);
The interrupt is not documented to clear on any write; only writes of 1 to bit 0.
> + default:
> + assert(0);
g_assert_not_reached.
> + }
> +
> + return old_v;
> +}
> +
> +target_ulong helper_csr_xchgq(CPULoongArchState *env, target_ulong val,
> + target_ulong mask, uint64_t csr)
> +{
> + target_ulong tmp;
> + target_ulong v = val & mask;
I think it would be less confusing to name the input parameter new_val, and the local
temporary old_val.
> +#define CASE_CSR_XCHGQ(csr) \
> + case LOONGARCH_CSR_ ## csr: \
> + { \
> + val = env->CSR_ ## csr; \
> + env->CSR_ ## csr = (env->CSR_ ## csr) & (~mask); \
> + env->CSR_ ## csr = (env->CSR_ ## csr) | v; \
old_val = env->CSR_##csr;
env->CSR_##csr = (old_val & ~mask) | (new_val & mask);
> + switch (csr) {
> + CASE_CSR_XCHGQ(CRMD)
I wonder if all of this would be better with a table of offsets, which could be shared
with the translator.
#define CSR_OFF(X) [LOONGARCH_CSR_##X] = offsetof(CPUArchState, CSR_##X)
static const int csr_offsets[] = {
CSR_OFF(CRMD),
...
};
int cpu_csr_offset(unsigned csr_num)
{
if (csr_num < ARRAY_SIZE(csr_offsets)) {
return csr_offsets[csr_num];
}
return 0;
}
Which reduces this function to
unsigned csr_offset = cpu_csr_offset(csr_num);
if (csr_offset == 0) {
/* CSR is undefined: read as 0, write ignored. */
return 0;
}
uint64_t *csr = (void *)env + csr_offset;
uint64_t old_val = *csr;
new_val = (new_val & mask) | (old_val & ~mask);
*csr = (old_val & ~mask) | (new_val & mask);
if (csr_num == LOONGARCH_CSR_TCFG) {
cpu_loongarch_store_stable_timer_config(env, new_val);
} else {
*csr = new_val;
}
return old_val;
> +uint64_t helper_iocsr_read(CPULoongArchState *env, target_ulong r_addr,
> + uint32_t size)
> +{
> + LoongArchMachineState *lams = LOONGARCH_MACHINE(qdev_get_machine());
> + int cpuid = env_cpu(env)->cpu_index;
> +
> + if (((r_addr & 0xff00) == 0x1000) || ((r_addr & 0xff00) == 0x1800)) {
> + r_addr = r_addr + ((target_ulong)(cpuid & 0x3) << 8);
> + }
This looks to be something that should be controlled by the address space assigned to each
cpu.
But it's hard to tell.
Where is the documentation for this? I didn't immediately find it in 3A5000 Technical
Reference Manual, Chapter 10.
> +void helper_iocsr_write(CPULoongArchState *env, target_ulong w_addr,
> + target_ulong val, uint32_t size)
> +{
> + LoongArchMachineState *lams = LOONGARCH_MACHINE(qdev_get_machine());
> + int cpuid = env_cpu(env)->cpu_index;
> + int mask, i;
> +
> + /*
> + * For IPI send, Mail send, ANY send adjust addr and val
> + * according to their real meaning
> + */
> + if (w_addr == 0x1040) { /* IPI send */
> + cpuid = (val >> 16) & 0x3ff;
> + val = 1UL << (val & 0x1f);
> + w_addr = 0x1008;
I don't see any interrupts actually being raised?
> +static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
> +{
> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> +
> + gen_helper_check_plv(cpu_env);
You don't need an external call. PLV should be part of TB_FLAGS, so you can check this
during translation.
> + case LOONGARCH_CSR_TVAL:
> + gen_helper_csr_rdq(dest, cpu_env, tcg_constant_i64(a->csr));
> + break;
> + default:
> + assert(0);
The assert was definitely wrong, as it allows incorrect programs to crash qemu. In
addition, unknown csr read as 0.
> + CASE_CSR_WRQ(MISC)
You don't actually support any of the MISC bits yet.
You should make this register read-only until you do.
How many more registers are read-only, or have read-only fields that you are not checking?
r~
next prev parent reply other threads:[~2021-11-11 17:44 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 1:34 [RFC PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
2021-11-11 1:34 ` [RFC PATCH v2 01/30] target/loongarch: Update README Xiaojuan Yang
2021-11-11 11:50 ` chen huacai
2021-11-15 3:34 ` yangxiaojuan
2021-11-11 1:35 ` [RFC PATCH v2 02/30] target/loongarch: Add CSR registers definition Xiaojuan Yang
2021-11-11 13:29 ` Richard Henderson
2021-11-12 2:14 ` yangxiaojuan
2021-11-12 7:14 ` Richard Henderson
2021-11-11 13:33 ` Richard Henderson
2021-11-11 1:35 ` [RFC PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2021-11-11 13:30 ` Richard Henderson
2021-11-11 1:35 ` [RFC PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch Xiaojuan Yang
2021-11-11 13:36 ` Richard Henderson
2021-11-12 2:24 ` yangxiaojuan
2021-11-11 1:35 ` [RFC PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 06/30] target/loongarch: Add stabletimer support Xiaojuan Yang
2021-11-11 14:34 ` Richard Henderson
2021-11-11 1:35 ` [RFC PATCH v2 07/30] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2021-11-11 15:53 ` Richard Henderson
2021-11-17 6:37 ` yangxiaojuan
2021-11-17 6:59 ` Richard Henderson
2021-11-11 1:35 ` [RFC PATCH v2 08/30] target/loongarch: Add LoongArch CSR/IOCSR instruction Xiaojuan Yang
2021-11-11 17:43 ` Richard Henderson [this message]
2021-11-17 8:48 ` yangxiaojuan
2021-11-11 1:35 ` [RFC PATCH v2 09/30] target/loongarch: Add TLB instruction support Xiaojuan Yang
2021-11-11 18:14 ` Richard Henderson
2021-11-17 7:29 ` yangxiaojuan
2021-11-17 8:22 ` Richard Henderson
2021-11-17 8:53 ` yangxiaojuan
2021-11-11 1:35 ` [RFC PATCH v2 10/30] target/loongarch: Add other core instructions support Xiaojuan Yang
2021-11-14 10:19 ` Richard Henderson
2021-11-11 1:35 ` [RFC PATCH v2 11/30] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 12/30] target/loongarch: Add timer related instructions support Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 13/30] target/loongarch: Add gdb support Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 14/30] target/loongarch: Implement privilege instructions disassembly Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 15/30] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson Platform Xiaojuan Yang
2021-11-11 13:17 ` Mark Cave-Ayland
2021-11-11 1:35 ` [RFC PATCH v2 16/30] hw/loongarch: Add a virt LoongArch 3A5000 board support Xiaojuan Yang
2021-11-11 14:17 ` Mark Cave-Ayland
2021-11-11 1:35 ` [RFC PATCH v2 17/30] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC) Xiaojuan Yang
2021-11-11 14:22 ` Mark Cave-Ayland
2021-11-11 1:35 ` [RFC PATCH v2 18/30] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2021-11-11 14:28 ` Mark Cave-Ayland
2021-11-11 1:35 ` [RFC PATCH v2 19/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2021-11-11 14:37 ` Mark Cave-Ayland
2021-11-11 1:35 ` [RFC PATCH v2 20/30] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2021-11-11 14:40 ` Mark Cave-Ayland
2021-11-11 1:35 ` [RFC PATCH v2 21/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2021-11-11 14:49 ` Mark Cave-Ayland
2021-11-25 8:20 ` yangxiaojuan
2021-11-26 8:19 ` Mark Cave-Ayland
2021-11-11 1:35 ` [RFC PATCH v2 22/30] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 23/30] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 24/30] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 25/30] hw/loongarch: Add default bios startup support Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 26/30] hw/loongarch: Add -kernel and -initrd options support Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 27/30] hw/loongarch: Add LoongArch smbios support Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 28/30] hw/loongarch: Add LoongArch acpi support Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 29/30] hw/loongarch: Add machine->possible_cpus Xiaojuan Yang
2021-11-11 1:35 ` [RFC PATCH v2 30/30] hw/loongarch: Add Numa support Xiaojuan Yang
2021-11-11 14:58 ` [RFC PATCH v2 00/30] Add Loongarch softmmu support Mark Cave-Ayland
2021-11-12 1:26 ` yangxiaojuan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f8e9fc82-ee40-fd40-3a8c-733c315b726e@linaro.org \
--to=richard.henderson@linaro.org \
--cc=gaosong@loongson.cn \
--cc=qemu-devel@nongnu.org \
--cc=yangxiaojuan@loongson.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).