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From: Tony Nguyen <tony.nguyen@bt.com>
To: qemu-devel@nongnu.org
Cc: Tony Nguyen <tony.nguyen@bt.com>,
	Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	Richard Henderson <richard.henderson@linaro.org>,
	Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [Qemu-devel] [PATCH v9 19/20] target/sparc: Add TLB entry with attributes
Date: Sat, 24 Aug 2019 04:36:57 +1000	[thread overview]
Message-ID: <f8fcc3138570c460ef289a6b34ba7715ba36f99e.1566466906.git.tony.nguyen@bt.com> (raw)
In-Reply-To: <cover.1566466906.git.tony.nguyen@bt.com>

Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/mmu_helper.c | 32 ++++++++++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index cbd1e91179..826e14b6f0 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -88,7 +88,7 @@ static const int perm_table[2][8] = {
 };
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
-                                int *prot, int *access_index,
+                                int *prot, int *access_index, MemTxAttrs *attrs,
                                 target_ulong address, int rw, int mmu_idx,
                                 target_ulong *page_size)
 {
@@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     target_ulong vaddr;
     target_ulong page_size;
     int error_code = 0, prot, access_index;
+    MemTxAttrs attrs = {};
 
     /*
      * TODO: If we ever need tlb_vaddr_to_host for this target,
@@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     assert(!probe);
 
     address &= TARGET_PAGE_MASK;
-    error_code = get_physical_address(env, &paddr, &prot, &access_index,
+    error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
                                       address, access_type,
                                       mmu_idx, &page_size);
     vaddr = address;
@@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
     return 0;
 }
 
-static int get_physical_address_data(CPUSPARCState *env,
-                                     hwaddr *physical, int *prot,
+static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
+                                     int *prot, MemTxAttrs *attrs,
                                      target_ulong address, int rw, int mmu_idx)
 {
     CPUState *cs = env_cpu(env);
@@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env,
     return 1;
 }
 
-static int get_physical_address_code(CPUSPARCState *env,
-                                     hwaddr *physical, int *prot,
+static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
+                                     int *prot, MemTxAttrs *attrs,
                                      target_ulong address, int mmu_idx)
 {
     CPUState *cs = env_cpu(env);
@@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env,
 }
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
-                                int *prot, int *access_index,
+                                int *prot, int *access_index, MemTxAttrs *attrs,
                                 target_ulong address, int rw, int mmu_idx,
                                 target_ulong *page_size)
 {
@@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
     }
 
     if (rw == 2) {
-        return get_physical_address_code(env, physical, prot, address,
+        return get_physical_address_code(env, physical, prot, attrs, address,
                                          mmu_idx);
     } else {
-        return get_physical_address_data(env, physical, prot, address, rw,
-                                         mmu_idx);
+        return get_physical_address_data(env, physical, prot, attrs, address,
+                                         rw, mmu_idx);
     }
 }
 
@@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     target_ulong vaddr;
     hwaddr paddr;
     target_ulong page_size;
+    MemTxAttrs attrs = {};
     int error_code = 0, prot, access_index;
 
     address &= TARGET_PAGE_MASK;
-    error_code = get_physical_address(env, &paddr, &prot, &access_index,
+    error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
                                       address, access_type,
                                       mmu_idx, &page_size);
     if (likely(error_code == 0)) {
@@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                                    env->dmmu.mmu_primary_context,
                                    env->dmmu.mmu_secondary_context);
 
-        tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
+        tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
+                                page_size);
         return true;
     }
     if (probe) {
@@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
 {
     target_ulong page_size;
     int prot, access_index;
+    MemTxAttrs attrs = {};
 
-    return get_physical_address(env, phys, &prot, &access_index, addr, rw,
-                                mmu_idx, &page_size);
+    return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
+                                rw, mmu_idx, &page_size);
 }
 
 #if defined(TARGET_SPARC64)
-- 
2.23.0



  parent reply	other threads:[~2019-08-23 18:54 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-23  1:19 [Qemu-devel] [PATCH v9 00/20] Invert Endian bit in SPARCv9 MMU TTE Tony Nguyen
2019-08-23  1:02 ` Tony Nguyen
2019-08-23  2:29 ` Richard Henderson
2019-08-23 12:25   ` tony.nguyen
2019-08-23 16:46     ` Richard Henderson
2019-08-23 18:51     ` Richard Henderson
2019-08-23 18:10 ` [Qemu-devel] [PATCH v9 01/20] tcg: TCGMemOp is now accelerator independent MemOp Tony Nguyen
2019-08-23 18:29 ` [Qemu-devel] [PATCH v9 02/20] memory: Introduce size_memop Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 03/20] target/mips: Access MemoryRegion with MemOp Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 04/20] hw/s390x: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 05/20] hw/intc/armv7m_nic: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 06/20] hw/virtio: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 07/20] hw/vfio: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 08/20] exec: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 09/20] cputlb: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 10/20] memory: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 11/20] hw/s390x: Hard code size with MO_{8|16|32|64} Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 12/20] target/mips: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 13/20] exec: " Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 14/20] memory: Access MemoryRegion with endianness Tony Nguyen
2019-08-23 19:04   ` Richard Henderson
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 15/20] cputlb: Replace size and endian operands for MemOp Tony Nguyen
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 16/20] memory: Single byte swap along the I/O path Tony Nguyen
2019-08-23 19:12   ` Richard Henderson
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 17/20] cpu: TLB_FLAGS_MASK bit to force memory slow path Tony Nguyen
2019-08-23 22:27   ` Richard Henderson
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 18/20] cputlb: Byte swap memory transaction attribute Tony Nguyen
2019-08-23 18:36 ` Tony Nguyen [this message]
2019-08-23 18:36 ` [Qemu-devel] [PATCH v9 20/20] target/sparc: sun4u Invert Endian TTE bit Tony Nguyen

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